Move FSP-only attributes to common targeting for Open Power

- Added default lane masks to Hostboot system XML files
- Added PCIE config related module IDs and reason codes
- Added new packing function to combine 4x uint8 into 1x uint32
- Added dynamic PCIE config for SP-less environments
- Moved PCIE attributes into common attribute definition
- Attached new PCIE attributes to common target definition
- Defaulted PCIE lanes per proc appropriately for all proc chips
- Added CDM_DOMAIN attribute into common attribute definition
- Attached + defaulted CDM domain in common target definition
- Updated common MRW parser to customize the new PCIE attributes

Change-Id: I3779ca6e6a4803d7e78e21e47a92e0b1a09e657d
RTC: 113488
CMVC-coreq: 942076
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/13997
Tested-by: Jenkins Server
Reviewed-by: STEPHEN M. CPREK <smcprek@us.ibm.com>
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

1 files changed, 32 insertions, 0 deletions

diff --git a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
index 84e5e6dd8..d20e6db99 100644
--- a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
@@ -676,6 +676,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Venice n0p0 EX units -->
@@ -1907,6 +1911,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Venice n0p1 EX units -->
@@ -3137,6 +3145,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Venice n0p2 EX units -->
@@ -4367,6 +4379,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Venice n0p3 EX units -->
@@ -5597,6 +5613,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Venice n0p4 EX units -->
@@ -6796,6 +6816,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Venice n0p5 EX units -->
@@ -7993,6 +8017,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Venice n0p6 EX units -->
@@ -9190,6 +9218,10 @@
              <field><id>writeCycleTime</id><value>0x05</value></field>
          </default>
      </attribute>
+    <attribute>
+        <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0xFFFF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <!-- Venice n0p7 EX units -->