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authorThi Tran <thi@us.ibm.com>2012-03-01 08:36:31 -0600
committerA. Patrick Williams III <iawillia@us.ibm.com>2012-03-08 13:47:27 -0600
commita3b4a0ff044b60b2af8082fd5256b1926e8b35b5 (patch)
treef91c2829cb6e9071ae948d9f845bd3d752fd4bf4 /src/usr/pore/poreve/porevesrc
parent7838a7409307f1106aaa6df42f1909e6824de197 (diff)
downloadtalos-hostboot-a3b4a0ff044b60b2af8082fd5256b1926e8b35b5.tar.gz
talos-hostboot-a3b4a0ff044b60b2af8082fd5256b1926e8b35b5.zip
VSBE code change to run SBE cen_sbe_tp_chiplet_init1
Updated with Review comments Change-Id: I745f0cd19b5e3159bba590f4efa9eab6fec71779 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/710 Tested-by: Jenkins Server Reviewed-by: MIKE J. JONES <mjjones@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/pore/poreve/porevesrc')
-rw-r--r--src/usr/pore/poreve/porevesrc/pib2cfam.C49
-rw-r--r--src/usr/pore/poreve/porevesrc/poreve.C215
-rw-r--r--src/usr/pore/poreve/porevesrc/poreve.H15
-rw-r--r--src/usr/pore/poreve/porevesrc/sbevital.C16
4 files changed, 68 insertions, 227 deletions
diff --git a/src/usr/pore/poreve/porevesrc/pib2cfam.C b/src/usr/pore/poreve/porevesrc/pib2cfam.C
index cf6100767..648df8822 100644
--- a/src/usr/pore/poreve/porevesrc/pib2cfam.C
+++ b/src/usr/pore/poreve/porevesrc/pib2cfam.C
@@ -21,21 +21,13 @@
//
// IBM_PROLOG_END
// -*- mode: C++; c-file-style: "linux"; -*-
-// $Id: pib2cfam.C,v 1.9 2012/01/09 21:22:50 jeshua Exp $
+// $Id: pib2cfam.C,v 1.10 2012/02/27 22:52:31 jeshua Exp $
/// \file pib2cfam.C
-/// \brief A temporary hack while waiting for hardware updates - a simple
-/// PibSlave that maps a small range of PIB addresses to CFAM addresses.
-///
-/// \todo Verify the assumption that the high-order 32 bits of the 64-bit data
-/// are the bits that are read and written to the CFAM register.
+/// \brief A simple PibSlave that maps a small range of PIB addresses to CFAM
+/// addresses.
#include "pib2cfam.H"
-//JDS TODO - remove the ECMD headers once we've got attribute support
-#ifndef __HOSTBOOT_MODULE
-#include "fapiSharedUtils.H"
-#include "ecmdUtils.H"
-#endif
using namespace vsbe;
@@ -56,30 +48,21 @@ Pib2Cfam::~Pib2Cfam()
static uint32_t
translateAddress(uint32_t address, fapi::Target* i_target)
{
- //JDS TODO - change this to get attribute ATTR_FSI_GP_REG_SCOM_ACCESS
- bool fsi_gpreg_scom_access = false;
-#ifndef __HOSTBOOT_MODULE
- ecmdChipData chipdata;
- ecmdChipTarget e_target;
- uint32_t rc;
- std::string chip_type;
-
- fapiTargetToEcmdTarget( *i_target, e_target);
- rc = ecmdGetChipData(e_target, chipdata);
- if( rc ) printf( "Problem with getchipdata\n" );
- chip_type = chipdata.chipType;
-
- if( chip_type == "centaur" ) {
- fsi_gpreg_scom_access = false;
- } else {
- fsi_gpreg_scom_access = true;
+ uint8_t fsi_gpreg_scom_access = 0;
+ fapi::ReturnCode frc;
+
+ frc = FAPI_ATTR_GET( ATTR_FSI_GP_REG_SCOM_ACCESS, i_target, fsi_gpreg_scom_access );
+ if(!frc.ok()) {
+ FAPI_ERR( "Unable to get ATTR_FSI_GP_REG_SCOM_ACCESS for target\n" );
+//JDS TODO - create an actual fapi error
+// FAPI_SET_HWP_ERROR( frc, "Unable to get ATTR_FSI_GP_REG_SCOM_ACCESS for target\n" );
}
-#endif
+
if( fsi_gpreg_scom_access ) {
- return (address - 0x00050000) + 0x2800;
+ return (address - 0x00050000) + 0x2800;
} else {
- return (address - 0x00050000) + 0x1000;
+ return (address - 0x00050000) + 0x1000;
}
}
@@ -106,7 +89,7 @@ Pib2Cfam::operation(Transaction& io_transaction)
case 0x0005001B:
rc = fapiGetCfamRegister(*iv_target,
translateAddress(io_transaction.iv_address, iv_target),
- *iv_dataBuffer);
+ *iv_dataBuffer);
if (rc.ok()) {
io_transaction.iv_data =
((uint64_t)iv_dataBuffer->getWord(0)) << 32;
@@ -134,7 +117,7 @@ Pib2Cfam::operation(Transaction& io_transaction)
iv_dataBuffer->setWord(0, io_transaction.iv_data >> 32);
rc = fapiPutCfamRegister(*iv_target,
translateAddress(io_transaction.iv_address, iv_target),
- *iv_dataBuffer);
+ *iv_dataBuffer);
if (rc.ok()) {
me = ME_SUCCESS;
} else {
diff --git a/src/usr/pore/poreve/porevesrc/poreve.C b/src/usr/pore/poreve/porevesrc/poreve.C
index e0a841cdd..eb2a89ede 100644
--- a/src/usr/pore/poreve/porevesrc/poreve.C
+++ b/src/usr/pore/poreve/porevesrc/poreve.C
@@ -20,7 +20,7 @@
// Origin: 30
//
// IBM_PROLOG_END
-// $Id: poreve.C,v 1.15 2011/12/14 22:11:51 bcbrock Exp $
+// $Id: poreve.C,v 1.16 2012/02/27 22:54:15 jeshua Exp $
/// \file poreve.C
/// \brief The PORE Virtual Environment
@@ -276,190 +276,51 @@ PoreVe::PoreVe(const PoreIbufId i_id,
#endif // PM_HACKS
-#ifdef VBU_HACKS
- // Configure the temporary Pib2Cfam component
+ // Configure the Pib2Cfam component to remap MBOX scom addresses to cfam addresses
+ uint8_t fsi_gpreg_scom_access;
+ fapi::ReturnCode frc;
- iv_pib2Cfam.configure(&iv_slaveTarget,
- &iv_dataBuffer,
- PIB2CFAM_PIB_BASE,
- PIB2CFAM_PIB_SIZE,
- ACCESS_MODE_READ | ACCESS_MODE_WRITE);
+ //JDS TODO - uncomment this when the model actually works
+// frc = FAPI_ATTR_GET( ATTR_FSI_GP_REG_SCOM_ACCESS, &iv_slaveTarget, fsi_gpreg_scom_access );
+ fsi_gpreg_scom_access = 0;
- iv_pib.attachPrimarySlave(&iv_pib2Cfam);
-
- // Configure the temporary sbeVital component
-
- iv_sbeVital.configure(&iv_slaveTarget,
- &iv_dataBuffer,
- SBEVITAL_PIB_BASE,
- SBEVITAL_PIB_SIZE,
- ACCESS_MODE_READ | ACCESS_MODE_WRITE);
-
- iv_pib.attachPrimarySlave(&iv_sbeVital);
+ if(!frc.ok()) {
+ FAPI_ERR( "Unable to get ATTR_FSI_GP_REG_SCOM_ACCESS for target\n" );
+ //JDS TODO - create an actual fapi error
+ // FAPI_SET_HWP_ERROR( frc, "Unable to get ATTR_FSI_GP_REG_SCOM_ACCESS for target\n" );
+ }
+ if( !fsi_gpreg_scom_access ) {
+ iv_pib2Cfam.configure(&iv_slaveTarget,
+ &iv_dataBuffer,
+ PIB2CFAM_PIB_BASE,
+ PIB2CFAM_PIB_SIZE,
+ ACCESS_MODE_READ | ACCESS_MODE_WRITE);
-#ifndef SIMPLE_VBU_HACKS_ONLY
+ iv_pib.attachPrimarySlave(&iv_pib2Cfam);
+ }
- // The VBU_HACKS above are simple - they don't require complex eCMD support so
- // we can test them easily with the poreve/test/fapistub test case.
+ // Configure the sbeVital register emulation
+ uint8_t use_hw_sbe_vital_register;
- // The VBU hacks below are complicated to emulate, so we don't even try in
- // the test/fapistub test case.
+ // JDS TODO - this needs to be done with an attribute (ATTR_USE_HW_SBE_VITAL_REGISTER requested)
+// frc = FAPI_ATTR_GET( ATTR_USE_HW_SBE_VITAL_REGISTER, &iv_slaveTarget, use_hw_sbe_vital_register );
+// if(!frc.ok()) {
+// FAPI_ERR( "Unable to get ATTR_USE_HW_SBE_VITAL_REGISTER for target\n" );
+// //JDS TODO - create an actual fapi error
+// // FAPI_SET_HWP_ERROR( frc, "Unable to get ATTR_USE_HW_SBE_VITAL_REGISTER for target\n" );
+// }
+ use_hw_sbe_vital_register = 0; //JDS TODO - TMP until the attribute is supported and the hardware allows access to the register
- // Configure the Broadside scan component if using BROADSIDE scan
- //JDS TODO - add a check for broadside scan mode
- ecmdConfigValid_t validOutput;
- std::string tmpStr;
- uint32_t tmpNum;
- uint32_t rc;
- ecmdChipTarget e_target;
+ if( !use_hw_sbe_vital_register ) {
+ iv_sbeVital.configure(&iv_slaveTarget,
+ &iv_dataBuffer,
+ SBEVITAL_PIB_BASE,
+ SBEVITAL_PIB_SIZE,
+ ACCESS_MODE_READ | ACCESS_MODE_WRITE);
- //JDS TODO - change this to get attribute
- fapiTargetToEcmdTarget( iv_slaveTarget, e_target);
- rc = ecmdGetConfiguration(e_target, "SIM_BROADSIDE_MODE",
- validOutput, tmpStr, tmpNum );
- if( rc ||
- validOutput == ECMD_CONFIG_VALID_FIELD_NONE ||
- validOutput == ECMD_CONFIG_VALID_FIELD_NUMERIC )
- {
- FAPI_ERR( "Unable to determine SIM_BROADSIDE_MODE\n" );
+ iv_pib.attachPrimarySlave(&iv_sbeVital);
}
- else
- {
- size_t pos = tmpStr.find( "scan" );
- if( pos != (uint32_t)-1 )
- {
-// iv_bsscan_ex00.configure(&iv_slaveTarget,
-// &iv_dataBuffer,
-// BSSCAN_PIB_BASE | EX00_PIB_BASE,
-// BSSCAN_PIB_SIZE,
-// ACCESS_MODE_READ | ACCESS_MODE_WRITE);
-
-// iv_pib.attachPrimarySlave(&iv_bsscan_ex00);
-
- iv_bsscan_ex01.configure(&iv_slaveTarget,
- &iv_dataBuffer,
- BSSCAN_PIB_BASE | EX01_PIB_BASE,
- BSSCAN_PIB_SIZE,
- ACCESS_MODE_READ | ACCESS_MODE_WRITE);
-
- iv_pib.attachPrimarySlave(&iv_bsscan_ex01);
-
- iv_bsscan_ex02.configure(&iv_slaveTarget,
- &iv_dataBuffer,
- BSSCAN_PIB_BASE | EX02_PIB_BASE,
- BSSCAN_PIB_SIZE,
- ACCESS_MODE_READ | ACCESS_MODE_WRITE);
-
- iv_pib.attachPrimarySlave(&iv_bsscan_ex02);
-
- iv_bsscan_ex03.configure(&iv_slaveTarget,
- &iv_dataBuffer,
- BSSCAN_PIB_BASE | EX03_PIB_BASE,
- BSSCAN_PIB_SIZE,
- ACCESS_MODE_READ | ACCESS_MODE_WRITE);
-
- iv_pib.attachPrimarySlave(&iv_bsscan_ex03);
-
- iv_bsscan_ex04.configure(&iv_slaveTarget,
- &iv_dataBuffer,
- BSSCAN_PIB_BASE | EX04_PIB_BASE,
- BSSCAN_PIB_SIZE,
- ACCESS_MODE_READ | ACCESS_MODE_WRITE);
-
- iv_pib.attachPrimarySlave(&iv_bsscan_ex04);
-
- iv_bsscan_ex05.configure(&iv_slaveTarget,
- &iv_dataBuffer,
- BSSCAN_PIB_BASE | EX05_PIB_BASE,
- BSSCAN_PIB_SIZE,
- ACCESS_MODE_READ | ACCESS_MODE_WRITE);
-
- iv_pib.attachPrimarySlave(&iv_bsscan_ex05);
-
- iv_bsscan_ex06.configure(&iv_slaveTarget,
- &iv_dataBuffer,
- BSSCAN_PIB_BASE | EX06_PIB_BASE,
- BSSCAN_PIB_SIZE,
- ACCESS_MODE_READ | ACCESS_MODE_WRITE);
-
- iv_pib.attachPrimarySlave(&iv_bsscan_ex06);
-
-// iv_bsscan_ex07.configure(&iv_slaveTarget,
-// &iv_dataBuffer,
-// BSSCAN_PIB_BASE | EX07_PIB_BASE,
-// BSSCAN_PIB_SIZE,
-// ACCESS_MODE_READ | ACCESS_MODE_WRITE);
-
-// iv_pib.attachPrimarySlave(&iv_bsscan_ex07);
-
-// iv_bsscan_ex08.configure(&iv_slaveTarget,
-// &iv_dataBuffer,
-// BSSCAN_PIB_BASE | EX08_PIB_BASE,
-// BSSCAN_PIB_SIZE,
-// ACCESS_MODE_READ | ACCESS_MODE_WRITE);
-
-// iv_pib.attachPrimarySlave(&iv_bsscan_ex08);
-
- iv_bsscan_ex09.configure(&iv_slaveTarget,
- &iv_dataBuffer,
- BSSCAN_PIB_BASE | EX09_PIB_BASE,
- BSSCAN_PIB_SIZE,
- ACCESS_MODE_READ | ACCESS_MODE_WRITE);
-
- iv_pib.attachPrimarySlave(&iv_bsscan_ex09);
-
- iv_bsscan_ex10.configure(&iv_slaveTarget,
- &iv_dataBuffer,
- BSSCAN_PIB_BASE | EX10_PIB_BASE,
- BSSCAN_PIB_SIZE,
- ACCESS_MODE_READ | ACCESS_MODE_WRITE);
-
- iv_pib.attachPrimarySlave(&iv_bsscan_ex10);
-
- iv_bsscan_ex11.configure(&iv_slaveTarget,
- &iv_dataBuffer,
- BSSCAN_PIB_BASE | EX11_PIB_BASE,
- BSSCAN_PIB_SIZE,
- ACCESS_MODE_READ | ACCESS_MODE_WRITE);
-
- iv_pib.attachPrimarySlave(&iv_bsscan_ex11);
-
- iv_bsscan_ex12.configure(&iv_slaveTarget,
- &iv_dataBuffer,
- BSSCAN_PIB_BASE | EX12_PIB_BASE,
- BSSCAN_PIB_SIZE,
- ACCESS_MODE_READ | ACCESS_MODE_WRITE);
-
- iv_pib.attachPrimarySlave(&iv_bsscan_ex12);
-
- iv_bsscan_ex13.configure(&iv_slaveTarget,
- &iv_dataBuffer,
- BSSCAN_PIB_BASE | EX13_PIB_BASE,
- BSSCAN_PIB_SIZE,
- ACCESS_MODE_READ | ACCESS_MODE_WRITE);
-
- iv_pib.attachPrimarySlave(&iv_bsscan_ex13);
-
- iv_bsscan_ex14.configure(&iv_slaveTarget,
- &iv_dataBuffer,
- BSSCAN_PIB_BASE | EX14_PIB_BASE,
- BSSCAN_PIB_SIZE,
- ACCESS_MODE_READ | ACCESS_MODE_WRITE);
-
- iv_pib.attachPrimarySlave(&iv_bsscan_ex14);
-
-// iv_bsscan_ex15.configure(&iv_slaveTarget,
-// &iv_dataBuffer,
-// BSSCAN_PIB_BASE | EX15_PIB_BASE,
-// BSSCAN_PIB_SIZE,
-// ACCESS_MODE_READ | ACCESS_MODE_WRITE);
-
-// iv_pib.attachPrimarySlave(&iv_bsscan_ex15);
- } //end SIM_BROADSIDE_MODE has scan
- } //end was able to read SIM_BROADSIDE_MODE
-
-#endif // SIMPLE_VBU_HACKS_ONLY
-#endif // VBU_HACKS
+
}
diff --git a/src/usr/pore/poreve/porevesrc/poreve.H b/src/usr/pore/poreve/porevesrc/poreve.H
index 4c2281940..41c64e7e0 100644
--- a/src/usr/pore/poreve/porevesrc/poreve.H
+++ b/src/usr/pore/poreve/porevesrc/poreve.H
@@ -23,7 +23,7 @@
#ifndef __VSBE_POREVE_H
#define __VSBE_POREVE_H
-// $Id: poreve.H,v 1.18 2011/12/16 21:47:59 bcbrock Exp $
+// $Id: poreve.H,v 1.20 2012/02/27 22:50:53 jeshua Exp $
/// \file poreve.H
/// \brief The PORE Virtual Environment
@@ -76,10 +76,11 @@
#include "poremodel.H"
#include "pore.H"
-#ifdef VBU_HACKS
#include "pib2cfam.H"
-#include "bsscan.H"
#include "sbevital.H"
+
+#ifdef VBU_HACKS
+#include "bsscan.H"
#endif // VBU_HACKS
#ifndef POREVE_STATISTICS
@@ -119,7 +120,7 @@ namespace vsbe {
//////////////////////////////////////////////////////////////////////
/// The PIB base address of the OTPROM memory controller
- const uint32_t OTPROM_PIB_BASE = 0x00010000;
+ const uint32_t OTPROM_PIB_BASE = 0x00018000;
/// The number of PIB \e registers defined by the OTPROM memory controller
///
@@ -500,13 +501,13 @@ public:
OciSlaveWritable iv_pmc;
#endif // PM_HACKS
-#ifdef VBU_HACKS
- /// The temporary Pib2Cfam PIB Slave
+ /// The Pib2Cfam PIB Slave
Pib2Cfam iv_pib2Cfam;
- /// The temporary sbeVital PIB Slave
+ /// The sbeVital PIB Slave
SbeVital iv_sbeVital;
+#ifdef VBU_HACKS
/// The Broadside Scan components for each EX
// Bsscan iv_bsscan_ex00;
Bsscan iv_bsscan_ex01;
diff --git a/src/usr/pore/poreve/porevesrc/sbevital.C b/src/usr/pore/poreve/porevesrc/sbevital.C
index 1a80337db..d8e09a29c 100644
--- a/src/usr/pore/poreve/porevesrc/sbevital.C
+++ b/src/usr/pore/poreve/porevesrc/sbevital.C
@@ -21,16 +21,13 @@
//
// IBM_PROLOG_END
// -*- mode: C++; c-file-style: "linux"; -*-
-// $Id: sbevital.C,v 1.1 2011/09/19 00:25:32 jeshua Exp $
+// $Id: sbevital.C,v 1.3 2012/02/27 22:51:37 jeshua Exp $
/// \file sbevital.C
-/// \brief A temporary hack to create the SBE vital reg before HW has it
+/// \brief Emulate the SBE vital register in software
///
-#ifdef VBU_HACKS
#include "sbevital.H"
-#include "fapiSharedUtils.H"
-#include "ecmdUtils.H"
using namespace vsbe;
@@ -52,17 +49,16 @@ SbeVital::~SbeVital()
fapi::ReturnCode
SbeVital::operation(Transaction& io_transaction)
{
- fapi::ReturnCode rc=0;
+ fapi::ReturnCode rc=(fapi::ReturnCodes)0;
ModelError me;
- FAPI_INF("In sbeVital\n");
-
- //On a ring write, put the data into the ring
+ //On a scom write, put the data into the register
if( io_transaction.iv_mode == ACCESS_MODE_WRITE)
{
iv_data = io_transaction.iv_data >> 32;
me = ME_SUCCESS;
}
+ //On a scom read, get the data from the register
else if( io_transaction.iv_mode == ACCESS_MODE_READ )
{
io_transaction.iv_data = ((uint64_t)(iv_data)) << 32;
@@ -76,7 +72,7 @@ SbeVital::operation(Transaction& io_transaction)
io_transaction.busError(me);
return rc;
}
-#endif
+
/* Local Variables: */
/* c-basic-offset: 4 */
/* End: */
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