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| author | Zane Shelley <zshelle@us.ibm.com> | 2017-05-31 15:03:36 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-06-09 17:14:33 -0400 |
| commit | 9df63900351645431ba629bfa49fd236829daaf6 (patch) | |
| tree | 7b42d4f2e005709d466c0cf0e8b40aa13a55473d /src/usr/isteps/istep21 | |
| parent | 826713fa254a1255a42c4c4a8968b3ae3b7d0ea9 (diff) | |
| download | talos-hostboot-9df63900351645431ba629bfa49fd236829daaf6.tar.gz talos-hostboot-9df63900351645431ba629bfa49fd236829daaf6.zip | |
fixed compilation errors when IPLTIME_CHECKSTOP_ANALYSIS is enabled
Not all compile errors have been resolved because occCheckstop.C is not
getting built at this time. This config will not be enabled as default
until after the IPL support is complete.
Change-Id: I9b2892c9bcae1929de2c871a71174a2f27d88d76
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41181
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/isteps/istep21')
| -rw-r--r-- | src/usr/isteps/istep21/call_host_runtime_setup.C | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/src/usr/isteps/istep21/call_host_runtime_setup.C b/src/usr/isteps/istep21/call_host_runtime_setup.C index 2cfeeccb1..0654239cd 100644 --- a/src/usr/isteps/istep21/call_host_runtime_setup.C +++ b/src/usr/isteps/istep21/call_host_runtime_setup.C @@ -45,6 +45,11 @@ #include <hbotcompid.H> +#ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS + #include <isteps/pm/occAccess.H> + #include <isteps/pm/occCheckstop.H> +#endif + using namespace ERRORLOG; using namespace ISTEP; using namespace ISTEP_ERROR; @@ -237,15 +242,19 @@ void* call_host_runtime_setup (void *io_pArgs) //0: mainstore, 1: SRAM. We want to use mainstore after this point //Get master proc - TargetService & tS = targetService(); + TARGETING::TargetService & tS = TARGETING::targetService(); TARGETING::Target* masterproc = NULL; tS.masterProcChipTargetHandle( masterproc ); //Clear (up to and including the IPL flag) + size_t sz_data = HBOCC::OCC_OFFSET_IPL_FLAG + 6; + size_t sz_dw = sizeof(uint64_t); + uint64_t l_occAppData[(sz_data+(sz_dw-1))/sz_dw]; + memset( l_occAppData, 0x00, sizeof(l_occAppData) ); + const uint32_t l_SramAddrApp = HBOCC::OCC_SRAM_ADDRESS; - ecmdDataBufferBase l_occAppData((HBOCC::OCC_OFFSET_IPL_FLAG + 6) - * 8 /* bits */); - l_err = HBOCC::writeSRAM(masterproc, l_SramAddrApp, l_occAppData); + l_err = HBOCC::writeSRAM( masterproc, l_SramAddrApp, l_occAppData, + sz_data ); if(l_err) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, |
