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| author | Nick Bofferding <bofferdn@us.ibm.com> | 2017-11-27 11:58:12 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-11-30 11:48:03 -0500 |
| commit | 98e55542894206f5b1442eaa470a0df7c81b70f5 (patch) | |
| tree | 3d1be5690b1c8e4ecbd52e8592d8dfbde2528b77 /src/usr/isteps/istep14 | |
| parent | c4d83bcbb421d786a0d5ff1e08d5bc53c365ba41 (diff) | |
| download | talos-hostboot-98e55542894206f5b1442eaa470a0df7c81b70f5.tar.gz talos-hostboot-98e55542894206f5b1442eaa470a0df7c81b70f5.zip | |
Secure Boot: Blacklist: Init PSI bridge BAR and FSP BAR properly for security
Change-Id: I96639c0e61a101170802ba9a96cd785d0388e985
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50057
Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/isteps/istep14')
| -rw-r--r-- | src/usr/isteps/istep14/call_proc_exit_cache_contained.C | 34 |
1 files changed, 0 insertions, 34 deletions
diff --git a/src/usr/isteps/istep14/call_proc_exit_cache_contained.C b/src/usr/isteps/istep14/call_proc_exit_cache_contained.C index abbc8fcdd..aa20dd2d2 100644 --- a/src/usr/isteps/istep14/call_proc_exit_cache_contained.C +++ b/src/usr/isteps/istep14/call_proc_exit_cache_contained.C @@ -326,40 +326,6 @@ void* call_proc_exit_cache_contained (void *io_pArgs) } } - //Set PSI and FSP BARs, activate the PSI link BAR - //TODO RTC 150260 Re-evaluate if this should be deleted or enabled -// uint64_t psi = l_masterProc->getAttr<ATTR_PSI_BRIDGE_BASE_ADDR>(); - uint64_t fsp = l_masterProc->getAttr<ATTR_FSP_BASE_ADDR>(); -// psi |= 0x1; //turn on enable bit for PSI, FSP is in PSI Init HWP - -// l_errl = deviceWrite( l_masterProc, -// &psi, -// scom_size, -// DEVICE_SCOM_ADDRESS(PU_PSI_BRIDGE_BAR_REG) ); - if ( l_errl ) - { - // Create IStep error log and cross reference to error that - // occurred - l_stepError.addErrorDetails( l_errl ); - - // Commit Error - errlCommit( l_errl, HWPF_COMP_ID ); - } - - l_errl = deviceWrite( l_masterProc, - &fsp, - scom_size, - DEVICE_SCOM_ADDRESS(PU_PSI_BRIDGE_FSP_BAR_REG) ); - if ( l_errl ) - { - // Create IStep error log and cross reference to error that - // occurred - l_stepError.addErrorDetails( l_errl ); - - // Commit Error - errlCommit( l_errl, HWPF_COMP_ID ); - } - // Call the function to extend VMM to 48MEG int rc = mm_extend(); |
