Fill in ATTR_PROC_PCIE_IOVALID_ENABLE based on functional PHBs

Change-Id: I26d81859b3a214d580cab97ca76d7fa7d93cdbd6
CQ: SW371816
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33336
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 94 insertions, 2 deletions

diff --git a/src/usr/isteps/istep14/call_proc_pcie_config.C b/src/usr/isteps/istep14/call_proc_pcie_config.C
index 9cd22379c..7c0697317 100644
--- a/src/usr/isteps/istep14/call_proc_pcie_config.C
+++ b/src/usr/isteps/istep14/call_proc_pcie_config.C
@@ -47,13 +47,102 @@ using   namespace   TARGETING;
 
 namespace ISTEP_14
 {
+
+/******************************************************************
+* compareChipUnits
+*
+* Check if chip unit of l_t1 > l_t2
+*
+*******************************************************************/
+bool compareChipUnits(TARGETING::Target *l_t1,
+                      TARGETING::Target *l_t2)
+{
+    bool l_result = false;
+    assert((l_t1 != NULL) && (l_t2 != NULL));
+
+    l_result = l_t1->getAttr<TARGETING::ATTR_CHIP_UNIT>() >
+               l_t2->getAttr<TARGETING::ATTR_CHIP_UNIT>();
+
+    return l_result;
+}
+
+
+/******************************************************************
+* setup_pcie_iovalid_enable
+*
+* Setup ATTR_PROC_PCIE_IOVALID_ENABLE on i_procTarget's PEC children
+*
+*******************************************************************/
+void setup_pcie_iovalid_enable(const TARGETING::Target * i_procTarget)
+{
+    // Get list of PEC chiplets downstream from the given proc chip
+    TARGETING::TargetHandleList l_pecList;
+
+    getChildAffinityTargetsByState( l_pecList,
+                          i_procTarget,
+                          TARGETING::CLASS_NA,
+                          TARGETING::TYPE_PEC,
+                          TARGETING::UTIL_FILTER_ALL);
+
+    for (auto l_pecTarget : l_pecList)
+    {
+        // Get list of PHB chiplets downstream from the given PEC chiplet
+        TARGETING::TargetHandleList l_phbList;
+
+        getChildAffinityTargetsByState( l_phbList,
+                          const_cast<TARGETING::Target*>(l_pecTarget),
+                          TARGETING::CLASS_NA,
+                          TARGETING::TYPE_PHB,
+                          TARGETING::UTIL_FILTER_ALL);
+
+
+        // default to all invalid
+        ATTR_PROC_PCIE_IOVALID_ENABLE_type l_iovalid = 0;
+
+        // arrange phb targets from largest to smallest based on unit
+        // ex.  PHB5, PHB4, PHB3
+        std::sort(l_phbList.begin(),l_phbList.end(),compareChipUnits);
+        for(uint32_t k = 0; k<l_phbList.size(); ++k)
+        {
+            const fapi2::Target<fapi2::TARGET_TYPE_PHB>
+                l_fapi_phb_target(l_phbList[k]);
+
+            if(l_fapi_phb_target.isFunctional())
+            {
+                TRACDCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                    "PHB%d functional",
+                    (l_phbList[k])->getAttr<TARGETING::ATTR_CHIP_UNIT>());
+
+                // filled in bitwise,
+                // largest PHB unit on the right to smallest leftword
+                // ex. l_iovalid = 0b00000110 : PHB3, PHB4 functional, PHB5 not
+                l_iovalid |= (1<<k);
+            }
+            else
+            {
+                TRACDCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                    "PHB%d not functional",
+                    (l_phbList[k])->getAttr<TARGETING::ATTR_CHIP_UNIT>());
+            }
+        }
+
+        TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                "PROC %.8X PEC%d -> ATTR_PROC_PCIE_IOVALID_ENABLE: 0x%02X",
+                TARGETING::get_huid(i_procTarget),
+                l_pecTarget->getAttr<TARGETING::ATTR_CHIP_UNIT>(),
+                l_iovalid);
+
+        l_pecTarget->setAttr<TARGETING::ATTR_PROC_PCIE_IOVALID_ENABLE>(l_iovalid);
+    }
+}
+
 void* call_proc_pcie_config (void *io_pArgs)
 {
     errlHndl_t  l_errl  =   NULL;
 
     IStepError  l_stepError;
 
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                "call_proc_pcie_config entry" );
 
     TARGETING::TargetHandleList l_procChips;
@@ -67,6 +156,9 @@ void* call_proc_pcie_config (void *io_pArgs)
         TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
                 "target HUID %.8X", TARGETING::get_huid(l_procChip));
 
+        // setup ATTR_PROC_PCIE_IOINVALID_ENABLE for this processor
+        setup_pcie_iovalid_enable(l_procChip);
+
         //  call the HWP with each fapi::Target
         FAPI_INVOKE_HWP( l_errl, p9_pcie_config, l_fapi_cpu_target );
 
@@ -93,7 +185,7 @@ void* call_proc_pcie_config (void *io_pArgs)
         }
     }
 
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                "call_proc_pcie_config exit" );
 
     // end task, returning any errorlogs to IStepDisp