Update MPIPL path for fused mode improvements

In DD1 we always only booted with a single core until istep 16.
In DD2 we can boot in fused mode. There were a couple places where
we were assuming that we were booting with a single core, this commit
addresses those places

Change-Id: Idbcefc4c73c7f7a70d76fe60d3f1080d97634d25
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43618
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>

1 files changed, 5 insertions, 5 deletions

diff --git a/src/usr/isteps/istep06/host_discover_targets.C b/src/usr/isteps/istep06/host_discover_targets.C
index 88b2f4114..364e30b5d 100644
--- a/src/usr/isteps/istep06/host_discover_targets.C
+++ b/src/usr/isteps/istep06/host_discover_targets.C
@@ -286,10 +286,10 @@ errlHndl_t powerDownSlaveQuads()
     TARGETING::TargetHandleList l_eqTargetList;
     getAllChiplets(l_eqTargetList, TARGETING::TYPE_EQ, true);
     uint64_t EX_0_CME_SCOM_SICR_SCOM1 = 0x1001203E;
-    uint64_t CME_SCOM_SICR_PM_EXIT_C0_MASK = 0x0800000000000000;
+    uint64_t CME_SCOM_SICR_PM_EXIT_C0_AND_C1_MASK = 0x0C00000000000000;
     uint64_t CPPM_CORE_POWMAN_MODE_REG = 0x200F0108;
     uint64_t SET_WKUP_SELECT_MASK = 0x0004000000000000;
-    size_t   MASK_SIZE = sizeof(CME_SCOM_SICR_PM_EXIT_C0_MASK);
+    size_t   MASK_SIZE = sizeof(CME_SCOM_SICR_PM_EXIT_C0_AND_C1_MASK);
 
 
 
@@ -338,15 +338,15 @@ errlHndl_t powerDownSlaveQuads()
             //TODO 171763 Core state setup for MPIPL should be done in a HWP
             for(const auto & l_ex_child : l_exChildren)
             {
-                // Clear bit 4 of CME_SCOM_SICR which sets PM_EXIT
+                // Clear bits 4 & 5 of CME_SCOM_SICR which sets PM_EXIT for C0 and C1 respectively
                 l_err = deviceWrite(l_ex_child,
-                                    &CME_SCOM_SICR_PM_EXIT_C0_MASK,
+                                    &CME_SCOM_SICR_PM_EXIT_C0_AND_C1_MASK,
                                     MASK_SIZE,
                                     DEVICE_SCOM_ADDRESS(EX_0_CME_SCOM_SICR_SCOM1)); //0x1001203E
                 if(l_err)
                 {
                     TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                              "Error clearing bit 4 of CME_SCOM_SICR on ex %d", l_ex_child->getAttr<TARGETING::ATTR_CHIP_UNIT>());
+                              "Error clearing bits 4 and 5 of CME_SCOM_SICR on ex %d", l_ex_child->getAttr<TARGETING::ATTR_CHIP_UNIT>());
                     break;
                 }
             }