Adding interface changes to provide BMC information to HDAT

Change-Id: I3ad70f2886fe8c0fc420bf490effbde33e477010
RTC:161648
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30994
Reviewed-by: VENKATESH SAINATH <venkatesh.sainath@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>

3 files changed, 46 insertions, 34 deletions

diff --git a/src/usr/ipmi/ipmidd.C b/src/usr/ipmi/ipmidd.C
index 99c4971c7..35f1d53f5 100644
--- a/src/usr/ipmi/ipmidd.C
+++ b/src/usr/ipmi/ipmidd.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2016                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -61,37 +61,6 @@ TRAC_INIT(&g_trac_ipmi, IPMI_COMP_NAME, 6*KILOBYTE, TRACE::BUFFER_SLOW);
 #define IPMI_TRAC(printf_string,args...) \
     TRACFCOMP(g_trac_ipmi,"dd: " printf_string,##args)
 
-enum {
-    // Registers. These are fixed for LPC/BT so we can hard-wire them
-    REG_CONTROL = 0xE4,
-    REG_HOSTBMC = 0xE5,
-    REG_INTMASK = 0xE6,
-
-    // Control register bits. The control register is interesting in that
-    // writing 0's never does anything; all registers are either set to 1
-    // when written with a 1 or toggled (1/0) when written with a one. So,
-    // we don't ever need to read-modify-write, we can just write an or'd
-    // mask of bits.
-    CTRL_B_BUSY        = (1 << 7),
-    CTRL_H_BUSY        = (1 << 6),
-    CTRL_OEM0          = (1 << 5),
-    CTRL_SMS_ATN       = (1 << 4),
-    CTRL_B2H_ATN       = (1 << 3),
-    CTRL_H2B_ATN       = (1 << 2),
-    CTRL_CLR_RD_PTR    = (1 << 1),
-    CTRL_CLR_WR_PTR    = (1 << 0),
-
-    IDLE_STATE = (CTRL_B_BUSY | CTRL_B2H_ATN |
-                  CTRL_SMS_ATN | CTRL_H2B_ATN),
-
-    // Bit in the INMASK register which signals to the BMC
-    // to reset it's end of things.
-    INT_BMC_HWRST      = (1 << 7),
-
-    // How long to sychronously wait for the device to change state (in ns)
-    WAIT_TIME = 100000000,
-};
-
 /**
  * @brief Performs an IPMI Message Read Operation
  * This function performs a IPMI Message Read operation. It follows a
diff --git a/src/usr/ipmi/ipmidd.H b/src/usr/ipmi/ipmidd.H
index 2faed9b3b..cb72d0076 100644
--- a/src/usr/ipmi/ipmidd.H
+++ b/src/usr/ipmi/ipmidd.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2016                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -33,6 +33,37 @@
  *  @brief Provides the interfaces to the IPMI Device Driver
  */
 
+enum {
+    // Registers. These are fixed for LPC/BT so we can hard-wire them
+    REG_CONTROL = 0xE4,
+    REG_HOSTBMC = 0xE5,
+    REG_INTMASK = 0xE6,
+
+    // Control register bits. The control register is interesting in that
+    // writing 0's never does anything; all registers are either set to 1
+    // when written with a 1 or toggled (1/0) when written with a one. So,
+    // we don't ever need to read-modify-write, we can just write an or'd
+    // mask of bits.
+    CTRL_B_BUSY        = (1 << 7),
+    CTRL_H_BUSY        = (1 << 6),
+    CTRL_OEM0          = (1 << 5),
+    CTRL_SMS_ATN       = (1 << 4),
+    CTRL_B2H_ATN       = (1 << 3),
+    CTRL_H2B_ATN       = (1 << 2),
+    CTRL_CLR_RD_PTR    = (1 << 1),
+    CTRL_CLR_WR_PTR    = (1 << 0),
+
+    IDLE_STATE = (CTRL_B_BUSY | CTRL_B2H_ATN |
+                  CTRL_SMS_ATN | CTRL_H2B_ATN),
+
+    // Bit in the INMASK register which signals to the BMC
+    // to reset it's end of things.
+    INT_BMC_HWRST      = (1 << 7),
+
+    // How long to sychronously wait for the device to change state (in ns)
+    WAIT_TIME = 100000000,
+};
+
 /**
  *  @brief IPMI Device Driver Class
  *     Provides read/write message capabilities.
diff --git a/src/usr/ipmi/ipmirp.C b/src/usr/ipmi/ipmirp.C
index b4fbfc047..c7e702e0f 100644
--- a/src/usr/ipmi/ipmirp.C
+++ b/src/usr/ipmi/ipmirp.C
@@ -1103,8 +1103,20 @@ namespace IPMI
      */
     BmcInfo_t getBmcInfo(void)
     {
-        //@TODO-RTC:161648-Fill in data
         BmcInfo_t l_info;
+
+        l_info.bulkTransferLpcBaseAddr = REG_HOSTBMC;
+        static size_t size = sizeof(uint8_t);
+        l_info.bulkTransferSize = size;
+        l_info.chipVersion = cpu_dd_level();
+        l_info.smsAttnInterrupt = CTRL_SMS_ATN;
+        l_info.bmcToHostInterrupt = CTRL_B2H_ATN;
+
+        //TODO RTC:162537 Add in non-generic bmc vendors AMI, Aten and OpenBmc
+        char l_vendor[32] = "openpower,generic";
+        strncpy(l_info.bmcVendor,l_vendor,sizeof(l_info.bmcVendor));
+
+
         return l_info;
     }