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author | Dan Crowell <dcrowell@us.ibm.com> | 2017-02-28 17:00:11 -0600 |
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committer | Matthew A. Ploetz <maploetz@us.ibm.com> | 2017-03-09 11:35:06 -0500 |
commit | db08661c9db59150909a98c37a37edfde92a442c (patch) | |
tree | 6c65a3ef60a7e75071bb9f30a79dfcee133237ad /src/usr/intr | |
parent | c70e7f7817bba97fc5d5661f63ab2b5587855417 (diff) | |
download | talos-hostboot-db08661c9db59150909a98c37a37edfde92a442c.tar.gz talos-hostboot-db08661c9db59150909a98c37a37edfde92a442c.zip |
Create PVR routines to handle DD2 changes
Created new PVR_t structure that understands how to decode the
PVR for Nimbus DD1 and future versions.
Change-Id: Ie7e6f62d65fb1a3e11b1021f1600e7421b8c30a9
RTC: 160361
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37303
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
Diffstat (limited to 'src/usr/intr')
-rw-r--r-- | src/usr/intr/intrrp.C | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C index fe010ed11..85d8f54f1 100644 --- a/src/usr/intr/intrrp.C +++ b/src/usr/intr/intrrp.C @@ -51,6 +51,7 @@ #include <fsi/fsiif.H> #include <arch/ppc.H> #include <arch/pirformat.H> +#include <arch/pvrformat.H> #include <config.h> #include <p9_misc_scom_addresses.H> @@ -397,11 +398,13 @@ errlHndl_t IntrRp::resetIntUnit(intr_hdlr_t* i_proc) TARGETING::Target* procTarget = i_proc->proc; do { - - //TODO RTC 160361 - Replace attribute with EC check. Anything greater - // DD20 should do the HW-based reset - uint8_t l_doHwReset = - iv_masterHdlr->proc->getAttr<TARGETING::ATTR_XIVE_HW_RESET>(); + //Anything greater than DD10 should do the HW-based reset + bool l_doHwReset = true; + uint32_t l_pvr = mmio_pvr_read() & 0xFFFFFFFF; + if( (l_pvr & PVR_t::CHIP_DD_MASK) == PVR_t::IS_NIMBUS_DD1 ) + { + l_doHwReset = false; + } if (l_doHwReset) { |