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| author | Dean Sanner <dsanner@us.ibm.com> | 2016-12-21 05:48:10 -0600 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2016-12-21 13:14:35 -0500 |
| commit | abc4a878dc90b34f48ec66554776717490fd2efb (patch) | |
| tree | ac76e26df51c8c5e2a8acd3fd781cc5968085137 /src/usr/intr | |
| parent | c9db2498d867484bb5caf94ebf299634635f375e (diff) | |
| download | talos-hostboot-abc4a878dc90b34f48ec66554776717490fd2efb.tar.gz talos-hostboot-abc4a878dc90b34f48ec66554776717490fd2efb.zip | |
Disable PSI INT during handoff to payload
Change-Id: Ieada68446c7ccf72cceb1c1610ba6e2adc2f6cbf
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34127
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/usr/intr')
| -rw-r--r-- | src/usr/intr/intrrp.C | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C index d84f542ab..b6a48758b 100644 --- a/src/usr/intr/intrrp.C +++ b/src/usr/intr/intrrp.C @@ -466,6 +466,13 @@ errlHndl_t IntrRp::disableInterrupts(intr_hdlr_t *i_proc) do { + //Disable Incoming PSI Interrupts + PSIHB_SW_INTERFACES_t * l_psihb_ptr = i_proc->psiHbBaseAddr; + + //Clear bit to disable PSI CEC interrupts + l_psihb_ptr->psihbcr = + (l_psihb_ptr->psihbcr & ~PSI_BRIDGE_INTP_STATUS_CTL_DISABLE_PSI); + //Pull thread context to register - View Section 4.4.4.15 of the // XIVE spec. Doing a 1b MMIO read will clear the cams VT bit. volatile uint8_t * l_pull_thread_ptr = (uint8_t *)iv_xiveTmBar1Address; |
