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| author | Dean Sanner <dsanner@us.ibm.com> | 2017-01-07 07:36:08 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-01-12 11:51:01 -0500 |
| commit | 7566526dcc42c2b15968be8796634b9e3a043cc6 (patch) | |
| tree | 975f2bdc3012ebd06d3d3e95efb3d35cd0521fe1 /src/usr/intr | |
| parent | 8f6e6c4e220d3128c0969b93a6f176b3820e3325 (diff) | |
| download | talos-hostboot-7566526dcc42c2b15968be8796634b9e3a043cc6.tar.gz talos-hostboot-7566526dcc42c2b15968be8796634b9e3a043cc6.zip | |
Need to access XIVE Thread management area with master thread
Change-Id: I9700b328dbc96a3a746be91b9d50de3752073aae
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34530
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/intr')
| -rw-r--r-- | src/usr/intr/intrrp.C | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C index de32b60cb..212aa4ea2 100644 --- a/src/usr/intr/intrrp.C +++ b/src/usr/intr/intrrp.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2016 */ +/* Contributors Listed Below - COPYRIGHT 2011,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -477,6 +477,12 @@ errlHndl_t IntrRp::disableInterrupts(intr_hdlr_t *i_proc) l_psihb_ptr->psihbcr = (l_psihb_ptr->psihbcr & ~PSI_BRIDGE_INTP_STATUS_CTL_DISABLE_PSI); + //The XIVE HW is expecting these MMIO accesses to come from the + // core/thread they were setup (master core, thread 0) + // These functions will ensure this code executes there + task_affinity_pin(); + task_affinity_migrate_to_master(); + //Pull thread context to register - View Section 4.4.4.15 of the // XIVE spec. Doing a 1b MMIO read will clear the cams VT bit. volatile uint8_t * l_pull_thread_ptr = (uint8_t *)iv_xiveTmBar1Address; @@ -490,6 +496,9 @@ errlHndl_t IntrRp::disableInterrupts(intr_hdlr_t *i_proc) sync(); TRACFCOMP(g_trac_intr, INFO_MRK"LSI Mode inactive (cams_vt)"); + //MMIO Complete, rest of code can run on any thread + task_affinity_unpin(); + // Unset Physical Thread Enable register in the PC space for the master // core - Simply reset both regs. uint64_t * l_ic_ptr = i_proc->xiveIcBarAddr; |
