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| author | Dean Sanner <dsanner@us.ibm.com> | 2016-04-27 06:08:35 -0500 |
|---|---|---|
| committer | Matthew A. Ploetz <maploetz@us.ibm.com> | 2016-07-07 12:13:44 -0400 |
| commit | 3032116e9cf00de3b38736a37652cbb99a904d7b (patch) | |
| tree | e9223e0748fc0bdd14aac7916e6ee839469fc07f /src/usr/intr | |
| parent | 89675ddf45b0bf157253de6989e535f66b73aedb (diff) | |
| download | talos-hostboot-3032116e9cf00de3b38736a37652cbb99a904d7b.tar.gz talos-hostboot-3032116e9cf00de3b38736a37652cbb99a904d7b.zip | |
Close timing window between PSUDD and INTR
Change-Id: Ifb6ab16bbb06335c7b898c77ffe308b6ff78ef86
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23719
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
Diffstat (limited to 'src/usr/intr')
| -rw-r--r-- | src/usr/intr/intrrp.C | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C index c09e19559..25bf01d82 100644 --- a/src/usr/intr/intrrp.C +++ b/src/usr/intr/intrrp.C @@ -211,8 +211,9 @@ void IntrRp::acknowledgeInterrupt() //A uint16 store from the Acknowledge Hypervisor Interrupt // offset in the Thread Management BAR space signals // the interrupt is acknowledged - uint16_t * l_ack_int_ptr = (uint16_t *)iv_xiveTmBar1Address; + volatile uint16_t * l_ack_int_ptr = (uint16_t *)iv_xiveTmBar1Address; l_ack_int_ptr += ACK_HYPERVISOR_INT_REG_OFFSET; + eieio(); uint16_t l_ackRead = *l_ack_int_ptr; TRACFCOMP(g_trac_intr, "IntrRp::acknowledgeInterrupt(), read result: %16x", l_ackRead); @@ -370,7 +371,7 @@ errlHndl_t IntrRp::enableInterrupts() uint64_t * l_ic_ptr = iv_xiveIcBarAddress; l_ic_ptr += XIVE_IC_BAR_INT_PC_MMIO_REG_OFFSET; - XIVE_IC_THREAD_CONTEXT_t * l_xive_ic_ptr = + volatile XIVE_IC_THREAD_CONTEXT_t * l_xive_ic_ptr = reinterpret_cast<XIVE_IC_THREAD_CONTEXT_t *>(l_ic_ptr); TRACFCOMP(g_trac_intr, INFO_MRK"IntrRp::enableInterrupts() " @@ -399,6 +400,7 @@ errlHndl_t IntrRp::enableInterrupts() " Set phys_thread_enable1_reg: 0x%016lx", l_enable); l_xive_ic_ptr->phys_thread_enable1_set = l_enable; } + eieio(); //Set bit to configure LSI mode for HB cec interrupts volatile XIVE_IVPE_THREAD_CONTEXT_t * this_ivpe_ptr = @@ -856,7 +858,7 @@ errlHndl_t IntrRp::sendEOI(uint64_t& i_intSource) TRACDCOMP(g_trac_intr, "IntrRp::sendEOI read response: %lx", eoiRead); //EOI Part 2 - LSI ESB Internal to the IVPE - uint64_t * l_lsiEoi = iv_xiveIcBarAddress; + volatile uint64_t * l_lsiEoi = iv_xiveIcBarAddress; l_lsiEoi += XIVE_IC_LSI_EOI_OFFSET; uint64_t l_intPending = *l_lsiEoi; @@ -1047,7 +1049,7 @@ errlHndl_t IntrRp::handlePsuInterrupt(ext_intr_t i_type) uint32_t l_addr = PSI_BRIDGE_PSU_DOORBELL_REG; size_t scom_len = sizeof(uint64_t); uint64_t reg = 0x0; - uint64_t l_elapsed_time_ns = 0; + uint64_t l_num_yields = 0; TARGETING::Target* procTarget = NULL; TARGETING::targetService().masterProcChipTargetHandle( procTarget ); @@ -1072,15 +1074,15 @@ errlHndl_t IntrRp::handlePsuInterrupt(ext_intr_t i_type) TRACDCOMP(g_trac_intr, "Host/SBE Mailbox " "response. Wait for Polling to handle" " response"); - nanosleep(0,10000); - l_elapsed_time_ns += 10000; + task_yield(); // allow PSU mbox task to handle + l_num_yields += 1; } else { //Polling Complete break; } - if (l_elapsed_time_ns > MAX_PSU_LONG_TIMEOUT_NS) + if (l_num_yields > 30) { TRACFCOMP(g_trac_intr, "PSU Timeout hit"); /*@ errorlog tag |
