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| author | crgeddes <crgeddes@us.ibm.com> | 2017-07-11 13:31:18 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-07-13 23:31:52 -0400 |
| commit | 1e7e41d6f38c44956764e2871d8f0a85df28b4be (patch) | |
| tree | fe512010f13cfcc987f5c9b0eb2715df33f933df /src/usr/intr | |
| parent | bf8d0080fc142dc2f515ee81002d64da43bf073e (diff) | |
| download | talos-hostboot-1e7e41d6f38c44956764e2871d8f0a85df28b4be.tar.gz talos-hostboot-1e7e41d6f38c44956764e2871d8f0a85df28b4be.zip | |
Set fused core enabled on the thread cntxt reg after resetting XIVE HW
In DD2 we are using the HW to reset the XIVE unit. We found that we
need to set the fused mode enabled bit in the INT thread context
register after the XIVE unit is restarted so this commit adds that
to the XIVE unit reset path.
Change-Id: I2c962fd67b60fc70ad431704ea83ca56eb5cb23f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42998
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/usr/intr')
| -rw-r--r-- | src/usr/intr/intrrp.C | 33 | ||||
| -rw-r--r-- | src/usr/intr/intrrp.H | 2 |
2 files changed, 35 insertions, 0 deletions
diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C index 9f418691b..8448ae158 100644 --- a/src/usr/intr/intrrp.C +++ b/src/usr/intr/intrrp.C @@ -544,6 +544,39 @@ errlHndl_t IntrRp::resetIntUnit(intr_hdlr_t* i_proc) TRACFCOMP(g_trac_intr, "Error resetting XIVE INT unit"); break; } + + //Additional settings for fused mode + //Needed because the HW XIVE reset clears too much HW state + if (is_fused_mode()) + { + //Do a Read-Modify-Write on INT Thread Context Register + //setting the FUSED_CORE_EN bit as the 'modify' part + uint64_t l_int_tctxt_reg = 0x0; + l_err = deviceRead(procTarget, + &l_int_tctxt_reg, + size, + DEVICE_SCOM_ADDRESS(PU_INT_TCTXT_CFG)); + + if (l_err) + { + TRACFCOMP(g_trac_intr, "Error reading the INT_TCTXT_CFG(%lx) scom register", + PU_INT_TCTXT_CFG); + break; + } + + l_int_tctxt_reg |= INT_TCTXT_CFG_FUSE_CORE_EN; + + l_err = deviceWrite(procTarget, + &l_int_tctxt_reg, + size, + DEVICE_SCOM_ADDRESS(PU_INT_TCTXT_CFG)); + if (l_err) + { + TRACFCOMP(g_trac_intr, "Error writing %lx the INT_TCTXT_CFG(%lx) scom register", + l_int_tctxt_reg, PU_INT_TCTXT_CFG ); + break; + } + } } else { diff --git a/src/usr/intr/intrrp.H b/src/usr/intr/intrrp.H index b7be87bab..db6669989 100644 --- a/src/usr/intr/intrrp.H +++ b/src/usr/intr/intrrp.H @@ -213,6 +213,8 @@ namespace INTR PSI_BRIDGE_INTP_STATUS_CTL_RESET = 0x4000000000000000ULL, PSI_BRIDGE_INTP_STATUS_CTL_DISABLE_PSI = 0x1000000000000000ULL, + INT_TCTXT_CFG_FUSE_CORE_EN = 0x0800000000000000, + XIVE_RESET_INT_CQ_RST_CTL_SCOM_ADDR = 0x05013023, XIVE_RESET_POWERBUS_QUIESCE_ENABLE = 0x4000000000000000, XIVE_RESET_POWERBUS_QUIESCE_TIMEOUT = 1000000, //1 millisecond |
