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authorDean Sanner <dsanner@us.ibm.com>2014-03-03 10:32:00 -0600
committerA. Patrick Williams III <iawillia@us.ibm.com>2014-03-04 12:29:06 -0600
commit90dd26565dee4aef37f78dce2f0f33e84bb83106 (patch)
tree5201d3c87e69b0f21bfcddaf26522d17c491e00b /src/usr/intr
parent611851d7dc6ab1f47ce9cebfb70470d4fdab78b4 (diff)
downloadtalos-hostboot-90dd26565dee4aef37f78dce2f0f33e84bb83106.tar.gz
talos-hostboot-90dd26565dee4aef37f78dce2f0f33e84bb83106.zip
Workaround invalid SBE use of IPI inject register
Change-Id: I40600399daf2ef563b534bd91143a4f45d00ff79 CQ: SW248610 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9273 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/intr')
-rw-r--r--src/usr/intr/intrrp.C29
1 files changed, 29 insertions, 0 deletions
diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C
index ed86cdfe6..5fb278363 100644
--- a/src/usr/intr/intrrp.C
+++ b/src/usr/intr/intrrp.C
@@ -656,6 +656,35 @@ void IntrRp::msgHandler()
}
break;
+ case MSG_INTR_ISSUE_SBE_MBOX_WA:
+ {
+ //The SBE IPI injection on master winkle wakeup
+ //can clobber a pending mailbox interrupt in the ICP
+ //To workaround need to issue EOI on mailbox. If
+ //mbx intr is not hot this does nothing, if it is
+ //then the EOI will cause intr to be represented
+
+ //This is safe on FSPless since the PSI intr are
+ //always setup on master chip
+ uint64_t baseAddr = iv_baseAddr +
+ cpuOffsetAddr(iv_masterCpu);
+ uint32_t * xirrAddress =
+ reinterpret_cast<uint32_t*>(baseAddr + XIRR_OFFSET);
+
+ //Generate the mailbox IRSN for this node
+ uint32_t l_irsn = makeXISR(iv_masterCpu, ISN_FSI);
+ l_irsn |= CPPR_MASK; //set all CPPR bits - allow any INTR
+
+ TRACFCOMP(g_trac_intr,
+ "MBX SBE WA Issue EOI to %x",l_irsn);
+ *xirrAddress = l_irsn; //Issue EOI
+
+ // Acknowlege msg
+ msg->data[1] = 0;
+ msg_respond(iv_msgQ, msg);
+ }
+ break;
+
case MSG_INTR_SHUTDOWN:
{
TRACFCOMP(g_trac_intr,"Shutdown event received");
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