XIVE CAMS is 1 byte access, disable VPC Pull error

Change-Id: Ie3177e8c3cadc2e927c88e07250383c312f994a7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24281
Tested-by: Jenkins Server
Tested-by: FSP CI Jenkins
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>

3 files changed, 120 insertions, 4 deletions

diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C
index 4df934758..2ec9d9a72 100644
--- a/src/usr/intr/intrrp.C
+++ b/src/usr/intr/intrrp.C
@@ -52,6 +52,7 @@
 #include <arch/ppc.H>
 #include <arch/pirformat.H>
 #include <config.h>
+#include <p9_misc_scom_addresses.H>
 
 #define INTR_TRACE_NAME INTR_COMP_NAME
 
@@ -308,6 +309,14 @@ errlHndl_t IntrRp::resetIntUnit()
             break;
         }
 
+        l_err = enableVPCPullErr(procTarget);
+        if (l_err)
+        {
+            TRACFCOMP(g_trac_intr, "Error re-enabling VPC Pull Err");
+            break;
+        }
+
+
     } while (0);
 
     if (l_err)
@@ -344,8 +353,10 @@ errlHndl_t IntrRp::enableInterrupts()
         //Set bit to configure LSI mode for HB cec interrupts
         XIVE_IVPE_THREAD_CONTEXT_t * this_ivpe_ptr =
           reinterpret_cast<XIVE_IVPE_THREAD_CONTEXT_t *> (iv_xiveTmBar1Address);
-        this_ivpe_ptr->cams = XIVE_IVPE_QW3_LSI_ENABLE;
+        this_ivpe_ptr->cams_vt = XIVE_IVPE_QW3_LSI_ENABLE;
+        eieio();
 
+        TRACFCOMP(g_trac_intr, INFO_MRK"LSI Mode active (cams_vt)");
    } while (0);
 
     //TODO RTC 150260 - Determine if any error checking can be done above, if so
@@ -961,6 +972,14 @@ errlHndl_t IntrRp::setInterruptBARs(TARGETING::Target * i_target)
             break;
         }
 
+        //Turn off VPC error when in LSI mode
+        l_err = disableVPCPullErr(i_target);
+        if (l_err)
+        {
+            TRACFCOMP(g_trac_intr, "Error masking VPC Pull Lsi Err");
+            break;
+        }
+
         l_err = setXiveIvpeTmBAR1(i_target);
         if (l_err)
         {
@@ -2705,7 +2724,78 @@ errlHndl_t IntrRp::setXiveIcBAR(TARGETING::Target * i_target)
         iv_xiveIcBarAddress =
                reinterpret_cast<uint64_t *>
                (mmio_dev_map(l_xiveIcBarAddress, 40*PAGE_SIZE));
+    } while(0);
+
+    return l_err;
+}
+
+errlHndl_t IntrRp::disableVPCPullErr(TARGETING::Target * i_target)
+{
+    errlHndl_t l_err = NULL;
+    size_t size;
+
+    do {
+        uint64_t l_vpcErrCnfg;
+        size = sizeof(l_vpcErrCnfg);
+        l_err = deviceRead(i_target,
+                            &l_vpcErrCnfg,
+                            size,
+                            DEVICE_SCOM_ADDRESS(PU_INT_PC_VPC_ERR_CFG1));
+
+        if(l_err)
+        {
+            TRACFCOMP(g_trac_intr,ERR_MRK"Unable to read VPC Err Cnfg");
+            break;
+        }
+
+        l_vpcErrCnfg &= ~XIVE_IC_VPC_PULL_ERR;
+        l_err = deviceWrite(i_target,
+                            &l_vpcErrCnfg,
+                            size,
+                            DEVICE_SCOM_ADDRESS(PU_INT_PC_VPC_ERR_CFG1));
 
+        if(l_err)
+        {
+            TRACFCOMP(g_trac_intr,ERR_MRK"Unable to write VPC Err Cnfg");
+            break;
+        }
+
+
+    } while(0);
+
+    return l_err;
+}
+
+errlHndl_t IntrRp::enableVPCPullErr(TARGETING::Target * i_target)
+{
+    errlHndl_t l_err = NULL;
+    size_t size;
+
+    do {
+        uint64_t l_vpcErrCnfg;
+        size = sizeof(l_vpcErrCnfg);
+        l_err = deviceRead(i_target,
+                            &l_vpcErrCnfg,
+                            size,
+                            DEVICE_SCOM_ADDRESS(PU_INT_PC_VPC_ERR_CFG1));
+
+        if(l_err)
+        {
+            TRACFCOMP(g_trac_intr,ERR_MRK"Unable to read VPC Err Cnfg");
+            break;
+        }
+
+        l_vpcErrCnfg |= XIVE_IC_VPC_PULL_ERR;
+        l_err = deviceWrite(i_target,
+                            &l_vpcErrCnfg,
+                            size,
+                            DEVICE_SCOM_ADDRESS(PU_INT_PC_VPC_ERR_CFG1));
+
+        if(l_err)
+        {
+            TRACFCOMP(g_trac_intr,ERR_MRK"Unable to write VPC Err Cnfg");
+            break;
+        }
     } while(0);
 
     return l_err;
diff --git a/src/usr/intr/intrrp.H b/src/usr/intr/intrrp.H
index 5141544b0..869bb1cd4 100644
--- a/src/usr/intr/intrrp.H
+++ b/src/usr/intr/intrrp.H
@@ -197,13 +197,14 @@ namespace INTR
                 XIVE_IC_ESB_EOI_OFFSET = 0x3000,
                 XIVE_IC_LSI_EOI_OFFSET =
                                         XIVE_IC_ESB_EOI_OFFSET/sizeof(uint64_t),
+                XIVE_IC_VPC_PULL_ERR = 0x0000000200000000,
 
                 //XIVE IVPE (Presentation Engine) Constants
                 XIVE_IVPE_TM_BAR1_SCOM_ADDR = 0x05013012,
                 XIVE_IVPE_TM_BAR1_MMIO_OFFSET = 0x0006020000000000ULL,
                 XIVE_IVPE_TM_BAR1_VALIDATE = 0x8000000000000000ULL,
                 XIVE_IVPE_QW3_OFFSET = 0x38,
-                XIVE_IVPE_QW3_LSI_ENABLE = 0x81000000,
+                XIVE_IVPE_QW3_LSI_ENABLE = 0x81,
 
                 PSI_BRIDGE_INTP_STATUS_CTL_SCOM_ADDR = 0x0501290E,
                 PSI_BRIDGE_INTP_STATUS_CTL_ENABLE = 0x8000000000000000ULL,
@@ -320,7 +321,10 @@ namespace INTR
                 uint8_t inc; //Age increment - 0x5
                 uint8_t age; //Thread age since last selected - 0x6
                 uint8_t pipr; //Pending Interrupt Priority Register - 0x7
-                uint32_t cams; //qw0/1/2/3 - 0x8
+                uint8_t cams_vt;   //qw0/1/2/3 - 0x8
+                uint8_t cams_rsv;  //qw0/1/2/3 - 0x9
+                uint8_t cams_rsv1; //qw0/1/2/3 - 0xA
+                uint8_t cams_prio; //qw0/1/2/3 - 0xB
             };
 
             #define PSIHB_SW_INTERFACES_SIZE (sizeof(PSIHB_SW_INTERFACES_t))
@@ -544,6 +548,24 @@ namespace INTR
             errlHndl_t setXiveIcBAR(TARGETING::Target * i_target);
 
             /**
+             * When in LSI mode the IC VPC flags and error, thus we
+             * need to disable while we use, and enable after we clean
+             * up
+             * @param[in] i_target, the Target.
+             * @return Errorlog from DeviceWrite
+             */
+            errlHndl_t disableVPCPullErr(TARGETING::Target * i_target);
+
+            /**
+             * When in LSI mode the IC VPC flags and error, thus we
+             * need to disable while we use, and enable after we clean
+             * up
+             * @param[in] i_target, the Target.
+             * @return Errorlog from DeviceWrite
+             */
+            errlHndl_t enableVPCPullErr(TARGETING::Target * i_target);
+
+            /**
              * Reset Interrupt Unit (both the XIVE and PSIHB Interrupt Units)
              * @return Errorlog from DeviceWrite
              */
diff --git a/src/usr/intr/makefile b/src/usr/intr/makefile
index 2ccfc14c5..db3a35a44 100644
--- a/src/usr/intr/makefile
+++ b/src/usr/intr/makefile
@@ -5,7 +5,9 @@
 #
 # OpenPOWER HostBoot Project
 #
-# COPYRIGHT International Business Machines Corp. 2011,2014
+# Contributors Listed Below - COPYRIGHT 2011,2016
+# [+] International Business Machines Corp.
+#
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -27,4 +29,6 @@ OBJS += intrrp.o
 
 SUBDIRS += test.d
 
+EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/common/include/
+
 include ${ROOTPATH}/config.mk