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| author | Patrick Williams <iawillia@us.ibm.com> | 2012-03-02 14:46:53 -0600 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2012-03-21 16:10:12 -0500 |
| commit | 368e90dff4f15530ba286e90c3cee574f58a1783 (patch) | |
| tree | f1f86938caa4bec6ece00e966c5781fd52ac7175 /src/usr/intr | |
| parent | 606503c551de7b751c6a0b78df2b0c43bd9446cd (diff) | |
| download | talos-hostboot-368e90dff4f15530ba286e90c3cee574f58a1783.tar.gz talos-hostboot-368e90dff4f15530ba286e90c3cee574f58a1783.zip | |
Support P8 mambo model and Murano proc.
RTC: 38206
Change-Id: Iab79041931db533ad6b6ebd057c1ef9fe4c4b8cc
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/714
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/intr')
| -rw-r--r-- | src/usr/intr/intrrp.H | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/src/usr/intr/intrrp.H b/src/usr/intr/intrrp.H index bb407bc02..43e7eaaa7 100644 --- a/src/usr/intr/intrrp.H +++ b/src/usr/intr/intrrp.H @@ -28,6 +28,7 @@ #include <limits.h> #include <errl/errlentry.H> #include <sys/msg.h> +#include <sys/misc.h> #include <intr/interrupt.H> #include <map> @@ -50,7 +51,7 @@ namespace INTR /** * Constructor */ - IntrRp() : + IntrRp() : iv_msgQ(NULL), iv_baseAddr(0), iv_masterCpu(0), @@ -100,7 +101,7 @@ namespace INTR /** * cpu PIR register - * @note TODO P7 bits - thread 2, core 3, chip 2, node 3, + * @note TODO P7 bits - thread 2, core 3, chip 2, node 3, * P8 will be different. Need P8 book IV */ struct PIR_t @@ -136,7 +137,7 @@ namespace INTR errlHndl_t _init(); /** - * Message handler + * Message handler */ void msgHandler(); @@ -173,7 +174,19 @@ namespace INTR { uint64_t offset = (i_pir.nodeId * 8) + i_pir.chipId; offset <<= 20; - offset |= static_cast<uint64_t>(i_pir.coreId) << 14; + switch (cpu_core_type()) + { + case CORE_POWER7: + case CORE_POWER7_PLUS: + offset |= static_cast<uint64_t>(i_pir.coreId) << 14; + break; + + case CORE_POWER8_MURANO: + case CORE_POWER8_VENICE: + default: + offset |= static_cast<uint64_t>(i_pir.coreId) << 15; + break; + } offset |= static_cast<uint64_t>(i_pir.threadId) << 12; return offset; } |
