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author | Doug Gilbert <dgilbert@us.ibm.com> | 2013-06-07 15:28:26 -0500 |
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committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-07-01 10:19:34 -0500 |
commit | 771ff7ddf36fa45b3e21238521dc6974385da12a (patch) | |
tree | 3a246472d6974a3e0f6eb35056d5ad409e601f7f /src/usr/intr/intrrp.C | |
parent | d125363f31f9277d1791966e5c694580d1b5e6fe (diff) | |
download | talos-hostboot-771ff7ddf36fa45b3e21238521dc6974385da12a.tar.gz talos-hostboot-771ff7ddf36fa45b3e21238521dc6974385da12a.zip |
Prevent flood of interrupts early in host boot start-up on MPIPL.
RTC: 72995
CQ: SW181350
Change-Id: Ia1061c4fc28987227a8cb5f02a539de9851863b8
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4922
Tested-by: Jenkins Server
Reviewed-by: Van H. Lee <vanlee@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/intr/intrrp.C')
-rw-r--r-- | src/usr/intr/intrrp.C | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C index 39ea2d470..a8dd2ca6d 100644 --- a/src/usr/intr/intrrp.C +++ b/src/usr/intr/intrrp.C @@ -219,6 +219,14 @@ errlHndl_t IntrRp::_init() err = NULL; } } + else + { + // The XIRR should be clean at this point, if not there is a + // serious problem. The routine will assert if an interrupt is + // found. + cleanCheck(); + } + // Set up the interrupt provider registers // NOTE: It's only possible to set up the master core at this point. @@ -1550,6 +1558,52 @@ errlHndl_t IntrRp::hw_disableIntrMpIpl() return err; } +void IntrRp::cleanCheck() +{ + TARGETING::TargetHandleList procCores; + getAllChiplets(procCores, TYPE_CORE); + + for(TARGETING::TargetHandleList::iterator + core = procCores.begin(); + core != procCores.end(); + ++core) + { + const TARGETING::Target * proc = getParentChip(*core); + + FABRIC_CHIP_ID_ATTR chip = proc->getAttr<ATTR_FABRIC_CHIP_ID>(); + FABRIC_NODE_ID_ATTR node = proc->getAttr<ATTR_FABRIC_NODE_ID>(); + CHIP_UNIT_ATTR coreId = + (*core)->getAttr<TARGETING::ATTR_CHIP_UNIT>(); + + PIR_t pir(0); + pir.nodeId = node; + pir.chipId = chip; + pir.coreId = coreId; + + size_t threads = cpu_thread_count(); + for(size_t thread = 0; thread < threads; ++thread) + { + pir.threadId = thread; + uint64_t xirrAddr = + cpuOffsetAddr(pir) + iv_baseAddr + XIRR_RO_OFFSET; + uint32_t * xirrPtr = reinterpret_cast<uint32_t*>(xirrAddr); + uint32_t xirr = (*xirrPtr) & 0x00FFFFFF; // mask off CPPR + + if(xirr != 0) + { + // mbox is not available at this point. + // errl is not functional at this point. + // This is probably a bug in SIMICS or FSP or HARDWARE + TRACFCOMP(g_trac_intr, ERR_MRK + "Unexpected early interrupt on non-mpipl path." + " xirr = %x", + xirr); + assert(xirr == 0); + } + } + } +} + //---------------------------------------------------------------------------- // External interfaces //---------------------------------------------------------------------------- |