Disable resetting on INT unit during MPIPL

Previously we were trying to pull the thead context before clearing
out the phs_thread_enabled regs when we initialized the intrrp
during mpipl. However I found that attempting this is causing a
recoverable fir which down the road creates a predictive gard
record. We don't need to be calling this in DD1. Not sure for DD2
yet but I have a story to revist

Change-Id: Ibb7d11463e80285354fda1355105cb58e2101ea7
RTC:172905
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39344
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 15 insertions, 2 deletions

diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C
index 85d8f54f1..c41a4cab8 100644
--- a/src/usr/intr/intrrp.C
+++ b/src/usr/intr/intrrp.C
@@ -137,7 +137,18 @@ errlHndl_t IntrRp::resetIntpForMpipl()
             {
                 PSIHB_SW_INTERFACES_t * this_psihb_ptr = (*targ_itr)->psiHbBaseAddr;
                 this_psihb_ptr->icr = PSI_BRIDGE_INTP_STATUS_CTL_RESET;
-                resetIntUnit(*targ_itr);
+
+                // TODO RTC: 172905 due to a DD1 workaround we have to do a SW reset
+                // The SW is causing a recoverable fir when we attemp to pull
+                // the thread context. The workaround earlier in the SBE's
+                // MPIPL steps is clearing out the phys_thread_enable regs
+                // so we can't pull thread context. All the SW reset is doing
+                // is enabling LSI interrutps (we do later) and clear the
+                // phys_thread_enabled regs which are already 0
+                // Still need to determine if we can skip this in DD2
+
+                //resetIntUnit(*targ_itr);
+
                 //Turn off VPC error when in LSI mode
                 err = disableVPCPullErr(*targ_itr);
                 if (err)
@@ -153,8 +164,10 @@ errlHndl_t IntrRp::resetIntpForMpipl()
         this_psihb_ptr->icr = PSI_BRIDGE_INTP_STATUS_CTL_RESET;
         TRACFCOMP(g_trac_intr, "Reset PSIHB INTR Complete");
 
+        // TODO RTC: 172905 Still need to determine if we can skip this in DD2
+        // (same as above)
         //Reset XIVE Interrupt unit
-        resetIntUnit(iv_masterHdlr);
+        //resetIntUnit(iv_masterHdlr);
 
         //Turn off VPC error when in LSI mode
         err = disableVPCPullErr(iv_masterHdlr);