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| author | Timothy Pearson <tpearson@raptorengineering.com> | 2019-04-18 06:28:50 +0000 |
|---|---|---|
| committer | Raptor Engineering Development Team <support@raptorengineering.com> | 2020-02-19 20:15:52 +0000 |
| commit | adf98ab745f8a950d589dad390146d23c34d9cca (patch) | |
| tree | 3f62fd3f25fb63c0d518157a332cc0f9264b496d /src/usr/initservice | |
| parent | d86c20f59ea1d977b0eb2ed7e2acf911ac037356 (diff) | |
| download | talos-hostboot-adf98ab745f8a950d589dad390146d23c34d9cca.tar.gz talos-hostboot-adf98ab745f8a950d589dad390146d23c34d9cca.zip | |
Add detailed ISTEP output option to hostboot
Output detailed ISTEP data over LPC port 81h/82h in support of RCS
Talos II systems. These systems will deadlock due to FSI silicon bugs
in the CPUs unless the BMC is aware of the current ISTEP data in order
to properly sequence BMC-side FSI service startup.
Diffstat (limited to 'src/usr/initservice')
| -rw-r--r-- | src/usr/initservice/istepdispatcher/HBconfig | 5 | ||||
| -rw-r--r-- | src/usr/initservice/istepdispatcher/istepdispatcher.C | 27 |
2 files changed, 32 insertions, 0 deletions
diff --git a/src/usr/initservice/istepdispatcher/HBconfig b/src/usr/initservice/istepdispatcher/HBconfig index 7987f8ef3..ccbd43854 100644 --- a/src/usr/initservice/istepdispatcher/HBconfig +++ b/src/usr/initservice/istepdispatcher/HBconfig @@ -21,6 +21,11 @@ config ISTEP_LPC_PORT80_DEBUG help Writes ISTEP progress to LPC port 80h. +config ISTEP_LPC_PORT8X_DEBUG + default n + help + Writes detailed ISTEP progress to LPC port 81h / 82h. + config HANG_ON_MFG_SRC_TERM default y help diff --git a/src/usr/initservice/istepdispatcher/istepdispatcher.C b/src/usr/initservice/istepdispatcher/istepdispatcher.C index 61d359bef..4680bb82c 100644 --- a/src/usr/initservice/istepdispatcher/istepdispatcher.C +++ b/src/usr/initservice/istepdispatcher/istepdispatcher.C @@ -2524,6 +2524,33 @@ errlHndl_t IStepDispatcher::sendProgressCode(bool i_needsLock) port80_val++; #endif +#ifdef CONFIG_ISTEP_LPC_PORT8X_DEBUG + // Detailed istep output for consumption by BMC on e.g. RCS Talos II systems. + // + // Due to FSI silicon issues, those platforms may fail to start correctly + // if the BMC is not aware of the exact ISTEP being run to control BMC + // service sequencing. + // + // NEVER output fake values here, only real ISTEP data. + // Data is latched in on write to port 82h + uint8_t port81_val = iv_curIStep & 0xff; + uint8_t port82_val = iv_curSubStep & 0xff; + size_t port81_len = sizeof(port81_val); + size_t port82_len = sizeof(port82_val); + // Write port 81h first + err = deviceWrite(TARGETING::MASTER_PROCESSOR_CHIP_TARGET_SENTINEL, + &port81_val, port81_len, + DEVICE_LPC_ADDRESS(LPC::TRANS_IO, 0x81)); + delete err; // this is debug only, ignore any errors + err = NULL; + // Then write port 82h, latching in the full 16-bit value for read + err = deviceWrite(TARGETING::MASTER_PROCESSOR_CHIP_TARGET_SENTINEL, + &port82_val, port82_len, + DEVICE_LPC_ADDRESS(LPC::TRANS_IO, 0x82)); + delete err; // this is debug only, ignore any errors + err = NULL; +#endif + #ifdef CONFIG_CONSOLE_OUTPUT_PROGRESS //--- Display step on serial console if ((iv_curIStep != lastIstep) || (iv_curSubStep != lastSubstep)) |
