hb-istep in debug framework

Change-Id: I21d95952e526e3ade6399c2f7e022e0897ae4610
RTC: 38308
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/959
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

3 files changed, 47 insertions, 38 deletions

diff --git a/src/usr/initservice/istepdispatcher/istepdispatcher.C b/src/usr/initservice/istepdispatcher/istepdispatcher.C
index 1738343a4..a628cc3b0 100644
--- a/src/usr/initservice/istepdispatcher/istepdispatcher.C
+++ b/src/usr/initservice/istepdispatcher/istepdispatcher.C
@@ -1,26 +1,26 @@
-//  IBM_PROLOG_BEGIN_TAG
-//  This is an automatically generated prolog.
-//
-//  $Source: src/usr/initservice/istepdispatcher/istepdispatcher.C $
-//
-//  IBM CONFIDENTIAL
-//
-//  COPYRIGHT International Business Machines Corp. 2011
-//
-//  p1
-//
-//  Object Code Only (OCO) source materials
-//  Licensed Internal Code Source Materials
-//  IBM HostBoot Licensed Internal Code
-//
-//  The source code for this program is not published or other-
-//  wise divested of its trade secrets, irrespective of what has
-//  been deposited with the U.S. Copyright Office.
-//
-//  Origin: 30
-//
-//  IBM_PROLOG_END
-
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/initservice/istepdispatcher/istepdispatcher.C $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2011 - 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
 /**
  *  @file istepdispatcher.C
  *
@@ -135,6 +135,8 @@ void IStepDispatcher::init( errlHndl_t  &io_rtaskRetErrl )
             //  should never happen...
             assert( l_spTaskTid > 0 );
 
+            //  sptask will turn on the ready bit when it is up.
+
             // IStep single-step
             singleStepISteps( io_rtaskRetErrl );
         }
@@ -276,7 +278,6 @@ void    IStepDispatcher::runAllISteps( errlHndl_t   &io_rtaskRetErrl )
 
 void    IStepDispatcher::singleStepISteps( errlHndl_t   &io_rtaskRetErrl )
 {
-    SPLESS::SPLessSts   l_StsReg;
     uint32_t    l_Type      =   0;
     uint32_t    l_IStep     =   0;
     uint32_t    l_Substep   =   0;
@@ -285,10 +286,6 @@ void    IStepDispatcher::singleStepISteps( errlHndl_t   &io_rtaskRetErrl )
     errlHndl_t  l_errl      =   NULL;
     uint32_t    l_PLID      =   0;
 
-    //  tell VPO and Simics that we're ready
-    l_StsReg.hdr.readybit   =   1;
-    SPLESS::writeSts( l_StsReg );
-
     mutex_lock(&iv_poll_mutex);  // make sure this is only poller
 
     while ( 1 )
@@ -788,7 +785,7 @@ void IStepDispatcher::handleSPlessBreakPoint( uint32_t i_info )
                         static_cast<uint32_t>( iv_pMsg->data[0] >> 32 ),
                         static_cast<uint32_t>( iv_pMsg->data[0] & 0xffffffff ) );
 
-                //  reply back to SPLEss
+                //  reply back FSP/console
                 msg_respond( iv_msgQ, iv_pMsg );
             }   // end else
         }   // end while
diff --git a/src/usr/initservice/istepdispatcher/splesscommon.C b/src/usr/initservice/istepdispatcher/splesscommon.C
index 9dc615a24..fdba904de 100644
--- a/src/usr/initservice/istepdispatcher/splesscommon.C
+++ b/src/usr/initservice/istepdispatcher/splesscommon.C
@@ -259,14 +259,9 @@ void    writeSts(  SPLessSts   &io_rsts )
                                                        g_SPLess_pMasterProcChip );
     }
 
-    // $$ save - mem g_SPLess_Status_Reg =   io_rsts.val64;
-    // $$ save mmio_scratch_write( MMIO_SCRATCH_IPLSTEP_STATUS, io_rsts.val64 );
     size_t  op_size =   sizeof( uint64_t );
-    DeviceFW::deviceWrite(
-              g_SPLess_pMasterProcChip,
-              &(io_rsts.val64),
-              op_size,
-              DEVICE_SCOM_ADDRESS( MBOX_SCRATCH_REG2 )  );
+
+    //  Write Status reg first
     // status reg lo is GMB2E4 - mailbox scratchpad 1  { regs 0 -3 }
     uint64_t    swap    =
         ((static_cast<uint64_t>(io_rsts.lo32) << 32 ) & 0xffffffff00000000) ;
@@ -276,6 +271,14 @@ void    writeSts(  SPLessSts   &io_rsts )
               op_size,
               DEVICE_SCOM_ADDRESS( MBOX_SCRATCH_REG1 )  );
 
+    // $$ save - mem g_SPLess_Status_Reg =   io_rsts.val64;
+    // $$ save mmio_scratch_write( MMIO_SCRATCH_IPLSTEP_STATUS, io_rsts.val64 );
+    DeviceFW::deviceWrite(
+              g_SPLess_pMasterProcChip,
+              &(io_rsts.val64),
+              op_size,
+              DEVICE_SCOM_ADDRESS( MBOX_SCRATCH_REG2 )  );
+
 #ifdef  SPLESS_DEBUG
     printk( "writeSts hi 0x%x\n", io_rsts.hi32 );
     printk( "writeSts lo 0x%x\n", io_rsts.lo32 );
diff --git a/src/usr/initservice/istepdispatcher/sptask.C b/src/usr/initservice/istepdispatcher/sptask.C
index 34d8a013a..84c37c261 100644
--- a/src/usr/initservice/istepdispatcher/sptask.C
+++ b/src/usr/initservice/istepdispatcher/sptask.C
@@ -245,6 +245,11 @@ void    userConsoleComm( void *  io_msgQ )
             l_sts.substep           =   l_cmd.substep;
             //  status should be set now, write to Status Reg.
 
+            // write the intermediate value back to the console.
+            TRACDCOMP( g_trac_initsvc,
+                    "userConsoleComm Write status 0x%x.%x",
+                    static_cast<uint32_t>( l_sts.val64 >> 32 ),
+                    static_cast<uint32_t>( l_sts.val64 & 0x0ffffffff ) );
             writeSts( l_sts );
 
             //  if shutdown issued, end this task
@@ -258,8 +263,12 @@ void    userConsoleComm( void *  io_msgQ )
             //      the running bit turn on.
             //      Please save the following in case we have to turn this
             //      back on.
-            // $$ l_cmd.val64 =   0;
-            // $$ writeCmd( l_cmd );
+
+            // write the intermediate value back to the console.
+            TRACDCOMP( g_trac_initsvc,
+                    "userConsoleComm Clear Command reg" );
+            l_cmd.val64 =   0;
+            writeCmd( l_cmd );
         }   //  endif   gobit