Move PCI mem addresses below 46 bits for NVIDIA CUDA Adapter

Change-Id: Ia162ac38be1f0aa92ef1e6168c94a4de26634fd4
CQ: SW251480
Backport: release-fips810
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9978
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

1 files changed, 31 insertions, 5 deletions

diff --git a/src/usr/hwpf/plat/fapiPlatAttributeService.C b/src/usr/hwpf/plat/fapiPlatAttributeService.C
index 7567a7bd0..25e2a50c1 100644
--- a/src/usr/hwpf/plat/fapiPlatAttributeService.C
+++ b/src/usr/hwpf/plat/fapiPlatAttributeService.C
@@ -933,14 +933,40 @@ fapi::ReturnCode fapiPlatGetProcPcieBarBaseAddr (
             l_pProcTarget->tryGetAttr<TARGETING::ATTR_PHB_BASE_ADDRS>(
                 l_phbRegs);
 
-            //  BAR # 0 are the PCIE mem 64
-            //  BAR # 1 are the PCIE mem 32
+            //  BAR # 0 are the PCIE mem 64, 64GB window
+            //  BAR # 1 are the PCIE mem 32, 2GB window
             //  BAR # 2 are the PHB REGS
+
+            //If we are in sapphire mode we need to shift the PCI
+            //Mem addresses down below the 48 bit limit for an NVIDA
+            //adapter.  This is a workaround for GA1 so the adapter
+            //can be supported.  Largest (theoretically dimm) is 1TB,
+            //so max mem is ~32TB for non brazos system.
+
+            //Place mem64 @ 59TB-63TB (0x00003B0000000000)
+            //Place mem32 @ 63.875TB-64TB (0x00030FE000000000)
+
+            //TODO RTC 100773 -- Fix this the correct way by
+            //having base addresses per payload type
+
+            //We will change the base addr down 4 bits, but need to keep
+            //the proc/node offsets the same
             for ( uint8_t u=0; u < 3; u++ )
             {
-               o_pcieBarBase[u][0]  =  l_pciMem64[u];
-               o_pcieBarBase[u][1]  =  l_pciMem32[u];
-               o_pcieBarBase[u][2]  =  l_phbRegs[u];
+               if(TARGETING::is_sapphire_load())
+               {
+                   o_pcieBarBase[u][0] = SAPPHIRE_PCIE_BAR0_BASE |
+                                     (l_pciMem64[u] & PCIE_BAR0_OFFSET_MASK);
+                   o_pcieBarBase[u][1] = SAPPHIRE_PCIE_BAR1_BASE |
+                                     (l_pciMem32[u] & PCIE_BAR1_OFFSET_MASK);
+               }
+               else
+               {
+                   o_pcieBarBase[u][0] = l_pciMem64[u];
+                   o_pcieBarBase[u][1] = l_pciMem32[u];
+               }
+
+               o_pcieBarBase[u][2] = l_phbRegs[u];
 
                FAPI_DBG( "fapiPlatGetProcPcieBarBaseAddr: Unit %d : %p %p %p",
                          u,