diff options
author | Christian Geddes <crgeddes@us.ibm.com> | 2019-04-25 13:04:51 -0500 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-05-14 14:54:03 -0500 |
commit | b95951684667a2d77a76e589505e4250a0f02751 (patch) | |
tree | 45117e7be05d6b04787717bcb95b818d0f3d8a75 /src/usr/hwas/test | |
parent | 7ddeb4b85db8f85f1ddffcda0943efeba58e20f9 (diff) | |
download | talos-hostboot-b95951684667a2d77a76e589505e4250a0f02751.tar.gz talos-hostboot-b95951684667a2d77a76e589505e4250a0f02751.zip |
Force Axone simics to read all VPD from HW with config flags
This commit will set the config flags to always read from HW
rather than the old VPD cache in PNOR. Until this point in Axone
we were still using an old copy of MVPD that we write into PNOR
during the startup simics scripts. From this commit onward we will
use the actual VPD simics provides. To handle this, some updates
we needed to the PG rules for Axone.
Change-Id: Ie06cefe1aec37edfc4c379ee1173bc51fc6bbe1f
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76519
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/hwas/test')
-rw-r--r-- | src/usr/hwas/test/hwas1test.H | 259 |
1 files changed, 229 insertions, 30 deletions
diff --git a/src/usr/hwas/test/hwas1test.H b/src/usr/hwas/test/hwas1test.H index 6784d4408..759ad7ad7 100644 --- a/src/usr/hwas/test/hwas1test.H +++ b/src/usr/hwas/test/hwas1test.H @@ -48,8 +48,74 @@ #include <targeting/common/commontargeting.H> #include <targeting/common/utilFilter.H> +const uint16_t pgDataAllGoodAxone[HWAS::VPD_CP00_PG_DATA_ENTRIES] = + {(uint16_t)HWAS::VPD_CP00_PG_FSI_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_PERVASIVE_GOOD_AXONE, + (uint16_t)HWAS::VPD_CP00_PG_N0_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_N1_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_N2_GOOD_AXONE, + (uint16_t)HWAS::VPD_CP00_PG_N3_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_XBUS_GOOD_CUMULUS, + (uint16_t)HWAS::VPD_CP00_PG_MCxx_GOOD_AXONE, + (uint16_t)HWAS::VPD_CP00_PG_MCxx_GOOD_AXONE, + (uint16_t)HWAS::VPD_CP00_PG_OBUS_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_OBUS_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_OBUS_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_OBUS_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_PCIx_GOOD[0], + (uint16_t)HWAS::VPD_CP00_PG_PCIx_GOOD[1], + (uint16_t)HWAS::VPD_CP00_PG_PCIx_GOOD[2], + (uint16_t)HWAS::VPD_CP00_PG_EPx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_EPx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_EPx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_EPx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_EPx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_EPx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD, + (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD}; + // Buffer with all good data (CUMULUS chip) -const uint16_t pgDataAllGood[HWAS::VPD_CP00_PG_DATA_ENTRIES] = +const uint16_t pgDataAllGoodCumulus[HWAS::VPD_CP00_PG_DATA_ENTRIES] = {(uint16_t)HWAS::VPD_CP00_PG_FSI_GOOD, (uint16_t)HWAS::VPD_CP00_PG_PERVASIVE_GOOD, (uint16_t)HWAS::VPD_CP00_PG_N0_GOOD, @@ -371,9 +437,20 @@ public: ? (uint16_t)VPD_CP00_PG_RESERVED_GOOD : (uint16_t)VPD_CP00_PG_OBUS_GOOD; uint16_t pgData[VPD_CP00_PG_DATA_ENTRIES]; - memcpy(pgData, - pgDataAllGood, - VPD_CP00_PG_DATA_LENGTH); + + if(MODEL_AXONE == l_model) + { + memcpy(pgData, + pgDataAllGoodAxone, + VPD_CP00_PG_DATA_LENGTH); + } + else + { + memcpy(pgData, + pgDataAllGoodCumulus, + VPD_CP00_PG_DATA_LENGTH); + } + pgData[VPD_CP00_PG_XBUS_INDEX] = l_xbus; pgData[VPD_CP00_PG_OB0_INDEX + 1] = l_obus12; pgData[VPD_CP00_PG_OB0_INDEX + 2] = l_obus12; @@ -460,9 +537,18 @@ public: l_mask); } - // Restore the "all good" data - pgData[VPD_CP00_PG_PERVASIVE_INDEX] = - (uint16_t)VPD_CP00_PG_PERVASIVE_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[VPD_CP00_PG_PERVASIVE_INDEX] = + (uint16_t)VPD_CP00_PG_PERVASIVE_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[VPD_CP00_PG_PERVASIVE_INDEX] = + (uint16_t)VPD_CP00_PG_PERVASIVE_GOOD; + } } TS_INFO( "testHWASisChipFunctional: N0 is not functional"); @@ -562,6 +648,19 @@ public: // Restore the "all good" data pgData[VPD_CP00_PG_N2_INDEX] = (uint16_t)VPD_CP00_PG_N2_GOOD; + + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[VPD_CP00_PG_N2_INDEX] = + (uint16_t)VPD_CP00_PG_N2_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[VPD_CP00_PG_N2_INDEX] = + (uint16_t)VPD_CP00_PG_N2_GOOD; + } } TS_INFO( "testHWASisChipFunctional: N3 is not functional"); @@ -686,9 +785,20 @@ public: ? (uint16_t)VPD_CP00_PG_RESERVED_GOOD : (uint16_t)VPD_CP00_PG_OBUS_GOOD; uint16_t pgData[VPD_CP00_PG_DATA_ENTRIES]; - memcpy(pgData, - pgDataAllGood, - VPD_CP00_PG_DATA_LENGTH); + + if(MODEL_AXONE == l_model) + { + memcpy(pgData, + pgDataAllGoodAxone, + VPD_CP00_PG_DATA_LENGTH); + } + else + { + memcpy(pgData, + pgDataAllGoodCumulus, + VPD_CP00_PG_DATA_LENGTH); + } + pgData[VPD_CP00_PG_XBUS_INDEX] = l_xbus; pgData[VPD_CP00_PG_OB0_INDEX + 1] = l_obus12; pgData[VPD_CP00_PG_OB0_INDEX + 2] = l_obus12; @@ -1107,9 +1217,19 @@ public: pDesc->getAttr<ATTR_HUID>()); } - // Restore the "all good" data - pgData[l_indexMC] = VPD_CP00_PG_MCxx_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } } break; @@ -1208,8 +1328,18 @@ public: pDesc->getAttr<ATTR_HUID>()); } - // Restore the "all good" data - pgData[l_indexMC] = VPD_CP00_PG_MCxx_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } } break; @@ -1307,8 +1437,18 @@ public: pDesc->getAttr<ATTR_HUID>()); } - // Restore the "all good" data - pgData[l_indexMC] = VPD_CP00_PG_MCxx_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } } break; @@ -1406,8 +1546,18 @@ public: pDesc->getAttr<ATTR_HUID>()); } - // Restore the "all good" data - pgData[l_indexMC] = VPD_CP00_PG_MCxx_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } } break; @@ -1506,8 +1656,18 @@ public: pDesc->getAttr<ATTR_HUID>()); } - // Restore the "all good" data - pgData[l_indexMC] = VPD_CP00_PG_MCxx_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[l_indexMC] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } } break; @@ -1871,9 +2031,18 @@ public: pDesc->getAttr<ATTR_HUID>()); } - // Restore the "all good" data - pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit * 2]] = - (uint16_t)VPD_CP00_PG_MCxx_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit * 2]] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit * 2]] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } } @@ -1987,9 +2156,18 @@ public: pDesc->getAttr<ATTR_HUID>()); } - // Restore the "all good" data - pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit]] = - (uint16_t)VPD_CP00_PG_MCxx_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit]] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit]] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } } // TEST WITH BAD MAGIC PORT (MCA0 or MCA4) @@ -2038,8 +2216,18 @@ public: pDesc->getAttr<ATTR_HUID>()); } - pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit / 2]] = - (uint16_t)VPD_CP00_PG_MCxx_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit / 2]] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit / 2]] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } // Try bad MCA Port setting for MCA2/3 & MCA6/7 if ( VPD_CP00_PG_MCxx_IOMyy[l_chipUnit / 2] != @@ -2147,8 +2335,19 @@ public: } // Restore the "all good" data - pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit * 2]] = - (uint16_t)VPD_CP00_PG_MCxx_GOOD; + if(MODEL_AXONE == l_model) + { + // Restore the "all good" data + pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit * 2]] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE; + } + else + { + // Restore the "all good" data + pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit * 2]] = + (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } + } |