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| author | Dan Crowell <dcrowell@us.ibm.com> | 2013-07-12 13:01:32 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-08-23 16:17:55 -0500 |
| commit | 3e71b410d1f8d3f5b2970c3b6e4f11ed8a195559 (patch) | |
| tree | 4ae89aec0d6cc35b6e9c3af1caa5e9456e7811d0 /src/usr/fsiscom | |
| parent | 6c82992a3ea6bb0acef08050f5dd110376ca3ac4 (diff) | |
| download | talos-hostboot-3e71b410d1f8d3f5b2970c3b6e4f11ed8a195559.tar.gz talos-hostboot-3e71b410d1f8d3f5b2970c3b6e4f11ed8a195559.zip | |
HB-driven FSI Init (part 1)
With this code an IPL on a single DCM system makes it up into
cen_sbe_tp_chiplet_init1 before it fails due to a Centaur SBE
issue. In addition to changes in the init flow, some updates
have been made to the error recovery/logging paths.
Similar results now seen on 2-DCM system.
Change-Id: I6c4b31ee568919c81d388c99ceb26c24705da9be
RTC: 67844
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5394
Tested-by: Jenkins Server
Reviewed-by: William H. Schwartz <whs@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/fsiscom')
| -rw-r--r-- | src/usr/fsiscom/fsiscom.C | 26 |
1 files changed, 24 insertions, 2 deletions
diff --git a/src/usr/fsiscom/fsiscom.C b/src/usr/fsiscom/fsiscom.C index 983e2d838..d87a6f393 100644 --- a/src/usr/fsiscom/fsiscom.C +++ b/src/usr/fsiscom/fsiscom.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2011,2012 */ +/* COPYRIGHT International Business Machines Corp. 2011,2013 */ /* */ /* p1 */ /* */ @@ -209,6 +209,28 @@ errlHndl_t fsiScomPerformOp(DeviceFW::OperationType i_opType, // it should be done (this layer or somewhere higher in the call stack?) //@todo: May add recover actions later. Currently undefined + //Grab the PIB2OPB Status reg for a XSCOM Block error + if( (l_status & 0x00007000) == 0x00001000 ) //piberr=001 + { + //@todo: Switch to external FSI FFDC interfaces RTC:35064 + TARGETING::Target* l_master = NULL; + TARGETING::targetService(). + masterProcChipTargetHandle(l_master); + + uint64_t scomdata = 0; + size_t scomsize = sizeof(uint64_t); + errlHndl_t l_err2 = DeviceFW::deviceOp( DeviceFW::READ, + l_master, + &scomdata, + scomsize, + DEVICE_XSCOM_ADDRESS(0x00020001)); + if( l_err2 ) { + delete l_err2; + } else { + TRACFCOMP( g_trac_fsiscom, "PIB2OPB Status = %.16X", scomdata ); + } + } + break; } @@ -250,7 +272,7 @@ errlHndl_t fsiScomPerformOp(DeviceFW::OperationType i_opType, //bits 17-19 indicates PCB/PIB error if((l_status & 0x00007000) != 0) { - TRACFCOMP( g_trac_fsiscom, ERR_MRK"fsiScomPerformOp:Read: PCB/PIB error received: l_status=0x%.8X)", l_status); + TRACFCOMP( g_trac_fsiscom, ERR_MRK"fsiScomPerformOp:Read: PCB/PIB error received: l_status=0x%0.8X)", l_status); /*@ * @errortype |
