PRD: Cumulus memory subsystem FIR review

Change-Id: I6800703e531cffdcc8fae52d744d847220e04fdb
RTC: 187481
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57383
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57502
CI-Ready: Zane C. Shelley <zshelle@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>

5 files changed, 217 insertions, 107 deletions

diff --git a/src/usr/diag/prdf/common/plat/p9/p9_dmi.rule b/src/usr/diag/prdf/common/plat/p9/p9_dmi.rule
index 2568d2b16..46602ffa4 100644
--- a/src/usr/diag/prdf/common/plat/p9/p9_dmi.rule
+++ b/src/usr/diag/prdf/common/plat/p9/p9_dmi.rule
@@ -136,7 +136,7 @@ rule rCHIFIR
     CHIFIR & ~CHIFIR_MASK &  CHIFIR_ACT0 &  CHIFIR_ACT1;
 };
 
-group gCHIFIR filter singlebit, cs_root_cause
+group gCHIFIR filter singlebit, cs_root_cause( 0, 2, 4, 5, 6, 12, 14, 15, 16, 32, 36, 40, 41, 42, 43, 46, 61 )
 {
     /** CHIFIR[0]
      *  PE on internal register
@@ -151,7 +151,7 @@ group gCHIFIR filter singlebit, cs_root_cause
     /** CHIFIR[2]
      *  Too many EDI replays due to CRC error
      */
-    (rCHIFIR, bit(2)) ? defaultMaskedError;
+    (rCHIFIR, bit(2)) ? dmi_bus_th_1_UERE;
 
     /** CHIFIR[3]
      *  EDI bus performance degraded by 1%
@@ -161,35 +161,35 @@ group gCHIFIR filter singlebit, cs_root_cause
     /** CHIFIR[4]
      *  DMI entered failed state
      */
-    (rCHIFIR, bit(4)) ? defaultMaskedError; # CUMULUS_10
+    (rCHIFIR, bit(4)) ? dmi_bus_th_1; # CUMULUS_10
 
     /** CHIFIR[5]
      *  Channel initialization timeout
      */
-    (rCHIFIR, bit(5)) ? defaultMaskedError; # CUMULUS_10
+    (rCHIFIR, bit(5)) ? defaultMaskedError;
 
     /** CHIFIR[6]
-     *  Chn interlock err (crc,. No ack, etc)
+     *  Channel interlock error
      */
-    (rCHIFIR, bit(6)) ? self_th_1; # CUMULUS_10
+    (rCHIFIR, bit(6)) ? defaultMaskedError;
 
     /** CHIFIR[7]
-     *  Round trip latency counter overflow
+     *  FRTL counter overflow
      */
     (rCHIFIR, bit(7)) ? defaultMaskedError;
 
     /** CHIFIR[8]
-     *  CRC error detected
+     *  CRC error
      */
-    (rCHIFIR, bit(8)) ? defaultMaskedError;
+    (rCHIFIR, bit(8)) ? dmi_bus_th_1; # CUMULUS_10
 
     /** CHIFIR[9]
-     *  No Ack error detected
+     *  No ack error
      */
     (rCHIFIR, bit(9)) ? defaultMaskedError;
 
     /** CHIFIR[10]
-     *  Sequence ID out of order error detected
+     *  Sequence ID out of order
      */
     (rCHIFIR, bit(10)) ? defaultMaskedError;
 
@@ -201,7 +201,7 @@ group gCHIFIR filter singlebit, cs_root_cause
     /** CHIFIR[12]
      *  UE on replay buffer read
      */
-    (rCHIFIR, bit(12)) ? self_th_1;
+    (rCHIFIR, bit(12)) ? self_th_1_UERE;
 
     /** CHIFIR[13]
      *  Multiple replay
@@ -211,107 +211,112 @@ group gCHIFIR filter singlebit, cs_root_cause
     /** CHIFIR[14]
      *  Replay buffer overrun
      */
-    (rCHIFIR, bit(14)) ? self_th_1; # CUMULUS_10
+    (rCHIFIR, bit(14)) ? self_th_1_UERE;
 
     /** CHIFIR[15]
      *  PE on MCI dataflow or state machine
      */
-    (rCHIFIR, bit(15)) ? self_th_1;
+    (rCHIFIR, bit(15)) ? self_th_1_UERE;
 
     /** CHIFIR[16]
-     *  Checkstop received from Centaur
+     *  Checkstop attn from memory buffer
      */
-    (rCHIFIR, bit(16)) ? analyzeConnectedCentaur;
+    (rCHIFIR, bit(16)) ? analyzeConnectedMembuf_UERE;
 
     /** CHIFIR[17]
-     *  Tracestop received from Centaur
+     *  Tracestop received from memory buffer
      */
     (rCHIFIR, bit(17)) ? defaultMaskedError;
 
     /** CHIFIR[18]
-     *  FPGA int received from Centaur
+     *  FPGA int received from memory buffer
      */
     (rCHIFIR, bit(18)) ? defaultMaskedError;
 
     /** CHIFIR[19]
-     *  Recoverable err received from Centaur
+     *  Recoverable attn from memory buffer
      */
-    (rCHIFIR, bit(19)) ? analyzeConnectedCentaur;
+    (rCHIFIR, bit(19)) ? analyzeConnectedMembuf;
 
     /** CHIFIR[20]
-     *  Special attention received from Centaur
+     *  Special attn from memory buffer
      */
-    (rCHIFIR, bit(20)) ? analyzeConnectedCentaur;
+    (rCHIFIR, bit(20)) ? analyzeConnectedMembuf;
 
     /** CHIFIR[21]
-     *  Maintenance complete from centuar
+     *  Maintenance complete from memory buffer
      */
     (rCHIFIR, bit(21)) ? defaultMaskedError;
 
     /** CHIFIR[22:30]
-     *  Fir bits from MCS
+     *  reserved
      */
     (rCHIFIR, bit(22|23|24|25|26|27|28|29|30)) ? defaultMaskedError;
 
     /** CHIFIR[31]
-     *  Channel sequence error
+     *  USDF sequence error
      */
     (rCHIFIR, bit(31)) ? self_th_1;
 
     /** CHIFIR[32]
-     *  Tag overrun in DSFF
+     *  DSFF tag overrun
      */
-    (rCHIFIR, bit(32)) ? defaultMaskedError; # CUMULUS_10
+    (rCHIFIR, bit(32)) ? self_th_1_UERE;
 
     /** CHIFIR[33]
-     *  DSFF DS Data Error(UE)
+     *  DSFF DS data error
      */
     (rCHIFIR, bit(33)) ? self_th_1;
 
     /** CHIFIR[34:35]
-     *  spare
+     *  reserved
      */
     (rCHIFIR, bit(34|35)) ? defaultMaskedError;
 
     /** CHIFIR[36]
-     *  Rdata Parity error
+     *  Rdata parity error
      */
-    (rCHIFIR, bit(36)) ? self_th_1;
+    (rCHIFIR, bit(36)) ? self_th_1_UERE;
 
     /** CHIFIR[37:39]
-     *  spare
+     *  reserved
      */
     (rCHIFIR, bit(37|38|39)) ? defaultMaskedError;
 
-    /** CHIFIR[40:41]
-     *  DSFF async crossing error
+    /** CHIFIR[40]
+     *  DSFF async cmd parity error
      */
-    (rCHIFIR, bit(40|41)) ? self_th_1;
+    (rCHIFIR, bit(40)) ? self_th_1_UERE;
+
+    /** CHIFIR[41]
+     *  DSFF async cmd sequence error
+     */
+    (rCHIFIR, bit(41)) ? self_th_1_UERE;
 
     /** CHIFIR[42]
      *  DSFF state machine error
      */
-    (rCHIFIR, bit(42)) ? self_th_1;
+    (rCHIFIR, bit(42)) ? self_th_1_UERE;
 
     /** CHIFIR[43]
      *  Recoverable parity error on EICR
      */
-    (rCHIFIR, bit(43)) ? self_th_32perDay;
+    (rCHIFIR, bit(43)) ? self_th_1;
 
     /** CHIFIR[44]
      *  Recoverable parity error on RECR
      */
-    (rCHIFIR, bit(44)) ? self_th_32perDay;
+    (rCHIFIR, bit(44)) ? self_th_1;
 
     /** CHIFIR[45]
      *  CE on WRT or RMW buffer
      */
-    (rCHIFIR, bit(45)) ? self_th_1;
+    (rCHIFIR, bit(45)) ? self_th_32perDay;
 
     /** CHIFIR[46]
      *  UE on WRT or RMW buffer
      */
-    (rCHIFIR, bit(46)) ? self_th_32perDay;
+    (rCHIFIR, bit(46)) ? self_th_1_UERE;
 
     /** CHIFIR[47]
      *  SUE on WRT or RMW buffer
@@ -324,32 +329,32 @@ group gCHIFIR filter singlebit, cs_root_cause
     (rCHIFIR, bit(48|49)) ? self_th_1;
 
     /** CHIFIR[50]
-     *  WDF SCOM Sequence error
+     *  WDF SCOM sequence error
      */
     (rCHIFIR, bit(50)) ? self_th_1;
 
     /** CHIFIR[51]
-     *  WDF State machine error
+     *  WDF state machine error
      */
     (rCHIFIR, bit(51)) ? self_th_1;
 
     /** CHIFIR[52]
-     *  WDF Register parity error
+     *  WDF register parity error
      */
     (rCHIFIR, bit(52)) ? self_th_1;
 
     /** CHIFIR[53]
-     *  WRT scom sequence error
+     *  WRT SCOM sequence error
      */
     (rCHIFIR, bit(53)) ? self_th_1;
 
     /** CHIFIR[54]
-     *  WRT Register parity error.
+     *  WRT register parity error.
      */
     (rCHIFIR, bit(54)) ? self_th_1;
 
     /** CHIFIR[55]
-     *  spare
+     *  reserved
      */
     (rCHIFIR, bit(55)) ? defaultMaskedError;
 
@@ -359,29 +364,24 @@ group gCHIFIR filter singlebit, cs_root_cause
     (rCHIFIR, bit(56)) ? self_th_1;
 
     /** CHIFIR[57]
-     *  WDF Async error
+     *  WDF async error
      */
     (rCHIFIR, bit(57)) ? self_th_1;
 
-    /** CHIFIR[58]
-     *  Read MCA parity error.
-     */
-    (rCHIFIR, bit(58)) ? self_th_1;
-
-    /** CHIFIR[59]
-     *  Read MCA sequence error
+    /** CHIFIR[58:59]
+     *  reserved
      */
-    (rCHIFIR, bit(59)) ? self_th_1;
+    (rCHIFIR, bit(58|59)) ? defaultMaskedError;
 
     /** CHIFIR[60]
      *  Debug/WAT register parity error
      */
-    (rCHIFIR, bit(60)) ? self_th_1;
+    (rCHIFIR, bit(60)) ? defaultMaskedError;
 
     /** CHIFIR[61]
      *  DSFF channel timeout
      */
-    (rCHIFIR, bit(61)) ? self_th_1;
+    (rCHIFIR, bit(61)) ? self_th_1_UERE;
 
     /** CHIFIR[62]
      *  SCOM error
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_dmi_actions.rule b/src/usr/diag/prdf/common/plat/p9/p9_dmi_actions.rule
index 744036fcf..7c9afa71e 100644
--- a/src/usr/diag/prdf/common/plat/p9/p9_dmi_actions.rule
+++ b/src/usr/diag/prdf/common/plat/p9/p9_dmi_actions.rule
@@ -5,7 +5,7 @@
 #
 # OpenPOWER HostBoot Project
 #
-# Contributors Listed Below - COPYRIGHT 2017
+# Contributors Listed Below - COPYRIGHT 2017,2018
 # [+] International Business Machines Corp.
 #
 #
@@ -23,4 +23,27 @@
 #
 # IBM_PROLOG_END_TAG
 
-actionclass analyzeConnectedCentaur { analyze(connected(TYPE_MEMBUF, 0)); };
+actionclass analyzeConnectedMembuf
+{
+    analyze(connected(TYPE_MEMBUF, 0));
+};
+
+actionclass analyzeConnectedMembuf_UERE
+{
+    SueSource;
+    analyzeConnectedMembuf;
+};
+
+actionclass dmi_bus_th_1
+{
+# TODO: RTC 144057
+#    funccall("calloutBusInterfacePlugin");
+    threshold1;
+};
+
+actionclass dmi_bus_th_1_UERE
+{
+    SueSource;
+    dmi_bus_th_1;
+};
+
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_dmi_regs.rule b/src/usr/diag/prdf/common/plat/p9/p9_dmi_regs.rule
index ba0b0601d..d3ad0f0c2 100644
--- a/src/usr/diag/prdf/common/plat/p9/p9_dmi_regs.rule
+++ b/src/usr/diag/prdf/common/plat/p9/p9_dmi_regs.rule
@@ -5,7 +5,7 @@
 #
 # OpenPOWER HostBoot Project
 #
-# Contributors Listed Below - COPYRIGHT 2017
+# Contributors Listed Below - COPYRIGHT 2017,2018
 # [+] International Business Machines Corp.
 #
 #
@@ -35,4 +35,66 @@
         access      write_only;
     };
 
+    register MCICFG0
+    {
+        name        "MCI Configuration Register 0";
+        scomaddr    0x0701090A;
+        capture     group default;
+    };
+
+    register MCISTAT
+    {
+        name        "MCI Status Register";
+        scomaddr    0x0701090B;
+        capture     group default;
+    };
+
+    register MCICRCSYN
+    {
+        name        "MCI CRC Syndromes Register";
+        scomaddr    0x0701090C;
+        capture     group default;
+    };
+
+    register MCIERRINJ
+    {
+        name        "MCI Error Inject Register";
+        scomaddr    0x0701090D;
+        capture     group default;
+    };
+
+    register MCICFG1
+    {
+        name        "MCI Configuration Register 1";
+        scomaddr    0x0701090E;
+        capture     group default;
+    };
+
+    register RECR
+    {
+        name        "Read ECC Control Register";
+        scomaddr    0x07010914;
+        capture     group default;
+    };
+
+    register EICR
+    {
+        name        "Error Inject Control Register";
+        scomaddr    0x07010918;
+        capture     group default;
+    };
+
+    register CERR0
+    {
+        name        "Error detail register 0";
+        scomaddr    0x07010919;
+        capture     group default;
+    };
+
+    register CERR1
+    {
+        name        "Error detail register 1";
+        scomaddr    0x0701091A;
+        capture     group default;
+    };
 
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_mi.rule b/src/usr/diag/prdf/common/plat/p9/p9_mi.rule
index 9f6571ef0..6d9f5cd1a 100644
--- a/src/usr/diag/prdf/common/plat/p9/p9_mi.rule
+++ b/src/usr/diag/prdf/common/plat/p9/p9_mi.rule
@@ -136,62 +136,47 @@ rule rMCFIR
     MCFIR & ~MCFIR_MASK &  MCFIR_ACT0 &  MCFIR_ACT1;
 };
 
-group gMCFIR filter singlebit, cs_root_cause( 0, 8, 9 )
+group gMCFIR filter singlebit, cs_root_cause( 0 )
 {
     /** MCFIR[0]
-     *  mc internal recoverable eror
+     *  MC internal recoverable eror
      */
     (rMCFIR, bit(0)) ? self_th_1;
 
     /** MCFIR[1]
-     *  mc internal non recovervable error
+     *  MC internal non recovervable error
      */
     (rMCFIR, bit(1)) ? self_th_1;
 
     /** MCFIR[2]
-     *  powerbus protocol error
+     *  Powerbus protocol error
      */
     (rMCFIR, bit(2)) ? level2_th_1;
 
     /** MCFIR[3]
-     *  bat with with incorrect tty pe
+     *  Inband bar hit with incorrect ttype
      */
-    (rMCFIR, bit(3)) ? defaultMaskedError;
+    (rMCFIR, bit(3)) ? level2_M_self_L_th_1;
 
     /** MCFIR[4]
-     *  multiple bar
+     *  Multiple bar
      */
     (rMCFIR, bit(4)) ? level2_M_self_L_th_1;
 
-    /** MCFIR[5]
-     *  Invalid Address
-     */
-    (rMCFIR, bit(5)) ? defaultMaskedError;
-
-    /** MCFIR[6]
-     *  Illegal consumer address
-     */
-    (rMCFIR, bit(6)) ? level2_th_1;
-
-    /** MCFIR[7]
-     *  Illegal producer address
+    /** MCFIR[5:7]
+     *  reserved
      */
-    (rMCFIR, bit(7)) ? level2_th_1;
+    (rMCFIR, bit(5|6|7)) ? defaultMaskedError;
 
     /** MCFIR[8]
-     *  command list timeout
+     *  Command list timeout
      */
     (rMCFIR, bit(8)) ? threshold_and_mask_level2;
 
-    /** MCFIR[9]
-     *  channel 0 time out error
-     */
-    (rMCFIR, bit(9)) ? threshold_and_mask;
-
-    /** MCFIR[10]
-     *  channel 1 time out error
+    /** MCFIR[9:10]
+     *  reserved
      */
-    (rMCFIR, bit(10)) ? level2_th_1;
+    (rMCFIR, bit(9|10)) ? defaultMaskedError;
 
     /** MCFIR[11]
      *  mcs wat0 event
@@ -214,42 +199,32 @@ group gMCFIR filter singlebit, cs_root_cause( 0, 8, 9 )
     (rMCFIR, bit(14)) ? defaultMaskedError;
 
     /** MCFIR[15]
-     *  mirror action occurred
+     *  Mirror action occurred
      */
     (rMCFIR, bit(15)) ? defaultMaskedError;
 
     /** MCFIR[16]
-     *  centaur sync command occurred
+     *  reserved
      */
     (rMCFIR, bit(16)) ? defaultMaskedError;
 
     /** MCFIR[17]
-     *  debug config reg error
-     */
-    (rMCFIR, bit(17)) ? defaultMaskedError;
-
-    /** MCFIR[18]
-     *  reserved
+     *  WAT debug config reg error
      */
-    (rMCFIR, bit(18)) ? defaultMaskedError;
+    (rMCFIR, bit(17)) ? threshold_and_mask_self;
 
-    /** MCFIR[19]
+    /** MCFIR[18:20]
      *  reserved
      */
-    (rMCFIR, bit(19)) ? defaultMaskedError;
-
-    /** MCFIR[20]
-     *  reserved
-     */
-    (rMCFIR, bit(20)) ? defaultMaskedError;
+    (rMCFIR, bit(18|19|20)) ? defaultMaskedError;
 
     /** MCFIR[21]
-     *  reserved
+     *  HWFM event occurred
      */
     (rMCFIR, bit(21)) ? defaultMaskedError;
 
     /** MCFIR[22]
-     *  Access to secure memory facility failed
+     *  Invalid SMF access
      */
     (rMCFIR, bit(22)) ? defaultMaskedError;
 
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_mi_regs.rule b/src/usr/diag/prdf/common/plat/p9/p9_mi_regs.rule
new file mode 100644
index 000000000..595a3d1be
--- /dev/null
+++ b/src/usr/diag/prdf/common/plat/p9/p9_mi_regs.rule
@@ -0,0 +1,50 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/usr/diag/prdf/common/plat/p9/p9_mi_regs.rule $
+#
+# OpenPOWER HostBoot Project
+#
+# Contributors Listed Below - COPYRIGHT 2018
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+    ############################################################################
+    # Additional regs for P9 MI target MCFIR
+    ############################################################################
+
+    register MCERPT0
+    {
+        name        "MCERPT0";
+        scomaddr    0x0501081E;
+        capture     group default;
+    };
+
+    register MCERPT1
+    {
+        name        "MCERPT1";
+        scomaddr    0x0501081F;
+        capture     group default;
+    };
+
+    register MCERPT2
+    {
+        name        "MCERPT2";
+        scomaddr    0x0501081A;
+        capture     group default;
+    };
+