PRD: Updates from RAS XML v100

Change-Id: I9f86bb29267bd969dd89e431886ff9b5b84a1cfd
CQ: SW400169
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45412
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com>
Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45570
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>

9 files changed, 111 insertions, 106 deletions

diff --git a/src/usr/diag/prdf/common/plat/p9/p9_common_actions.rule b/src/usr/diag/prdf/common/plat/p9/p9_common_actions.rule
index afa279b0a..251e46e6d 100644
--- a/src/usr/diag/prdf/common/plat/p9/p9_common_actions.rule
+++ b/src/usr/diag/prdf/common/plat/p9/p9_common_actions.rule
@@ -99,11 +99,13 @@ actionclass threshold5pday
  */
 actionclass threshold_and_mask
 {
-    calloutSelfMed;
     threshold32pday;
     funccall("ClearServiceCallFlag");
 };
 
+actionclass threshold_and_mask_self   { calloutSelfMed;   threshold_and_mask; };
+actionclass threshold_and_mask_level2 { callout2ndLvlMed; threshold_and_mask; };
+
 ################################################################################
 #                               Special Flags                                  #
 ################################################################################
@@ -211,9 +213,10 @@ actionclass level2_M_proc_L_th_1
 #                           Callouts with flags                                #
 ################################################################################
 
-actionclass level2_th_1_SUE { level2_th_1; SueSeen;   };
-actionclass self_th_1_SUE   { self_th_1;   SueSeen;   };
-actionclass self_th_1_UERE  { self_th_1;   SueSource; };
+actionclass level2_th_1_SUE  { level2_th_1; SueSeen;   };
+actionclass level2_th_1_UERE { level2_th_1; SueSource; };
+actionclass self_th_1_SUE    { self_th_1;   SueSeen;   };
+actionclass self_th_1_UERE   { self_th_1;   SueSource; };
 
 ################################################################################
 #                               Dump Types                                     #
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_ec.rule b/src/usr/diag/prdf/common/plat/p9/p9_ec.rule
index b296f816b..34fee0983 100644
--- a/src/usr/diag/prdf/common/plat/p9/p9_ec.rule
+++ b/src/usr/diag/prdf/common/plat/p9/p9_ec.rule
@@ -644,17 +644,17 @@ group gCOREFIR filter singlebit, cs_root_cause
     /** COREFIR[33]
      *  Special recovery error, tlb multi-hit
      */
-    (rCOREFIR, bit(33)) ? threshold_and_mask;
+    (rCOREFIR, bit(33)) ? threshold_and_mask_self;
 
     /** COREFIR[34]
      *  LSU SLB multihit error
      */
-    (rCOREFIR, bit(34)) ? threshold_and_mask;
+    (rCOREFIR, bit(34)) ? threshold_and_mask_self;
 
     /** COREFIR[35]
      *  LSU ERAT multihit error
      */
-    (rCOREFIR, bit(35)) ? threshold_and_mask;
+    (rCOREFIR, bit(35)) ? threshold_and_mask_self;
 
     /** COREFIR[36]
      *  Forward Progress Error
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_ex.rule b/src/usr/diag/prdf/common/plat/p9/p9_ex.rule
index 268c5be81..4cd52900f 100644
--- a/src/usr/diag/prdf/common/plat/p9/p9_ex.rule
+++ b/src/usr/diag/prdf/common/plat/p9/p9_ex.rule
@@ -314,7 +314,7 @@ rule rL2FIR
     L2FIR & ~L2FIR_MASK & ~L2FIR_ACT0 &  L2FIR_ACT1;
 };
 
-group gL2FIR filter singlebit, cs_root_cause
+group gL2FIR filter singlebit, cs_root_cause( 1, 17, 18, 20 )
 {
     /** L2FIR[0]
      *  L2 cache read CE
@@ -324,7 +324,7 @@ group gL2FIR filter singlebit, cs_root_cause
     /** L2FIR[1]
      *  L2 cache read UE
      */
-    (rL2FIR, bit(1)) ? l2_cache_ue;
+    (rL2FIR, bit(1)) ? l2_cache_ue_UERE;
 
     /** L2FIR[2]
      *  L2 cache read SUE
@@ -404,7 +404,7 @@ group gL2FIR filter singlebit, cs_root_cause
     /** L2FIR[17]
      *  (RC) load received pb cresp addr error
      */
-    (rL2FIR, bit(17)) ? level2_th_1;
+    (rL2FIR, bit(17)) ? level2_th_1_UERE;
 
     /** L2FIR[18]
      *  (RC) store received pb cresp addr error
@@ -419,7 +419,7 @@ group gL2FIR filter singlebit, cs_root_cause
     /** L2FIR[20]
      *  RC or NCU Pb data UE error
      */
-    (rL2FIR, bit(20)) ? self_th_1;
+    (rL2FIR, bit(20)) ? self_th_1_UERE;
 
     /** L2FIR[21]
      *  RC or NCU PB data SUE detected
@@ -474,7 +474,7 @@ group gL2FIR filter singlebit, cs_root_cause
     /** L2FIR[36]
      *  Cache CE and UE in short time period
      */
-    (rL2FIR, bit(36)) ? self_th_1;
+    (rL2FIR, bit(36)) ? threshold_and_mask_self;
 
     /** L2FIR[37:38]
      *  spare
@@ -560,7 +560,7 @@ group gNCUFIR filter singlebit, cs_root_cause( 8 )
     /** NCUFIR[9]
      *  store timed out on pb
      */
-    (rNCUFIR, bit(9)) ? threshold_and_mask;
+    (rNCUFIR, bit(9)) ? threshold_and_mask_self;
 
     /** NCUFIR[10]
      *  tlbie master timeout
@@ -651,7 +651,7 @@ rule rL3FIR
     L3FIR & ~L3FIR_MASK & ~L3FIR_ACT0 &  L3FIR_ACT1;
 };
 
-group gL3FIR filter singlebit, cs_root_cause
+group gL3FIR filter singlebit, cs_root_cause( 5, 8, 11, 17, 21 )
 {
     /** L3FIR[0]
      *  L3_RDDSP_SEGR_LCO_ALL_MEM_UNAVAIL_ERR
@@ -666,7 +666,7 @@ group gL3FIR filter singlebit, cs_root_cause
     /** L3FIR[3]
      *  L3 cache CE and UE within a short period
      */
-    (rL3FIR, bit(3)) ? self_th_1;
+    (rL3FIR, bit(3)) ? threshold_and_mask_self;
 
     /** L3FIR[4]
      *  CE detected on L3 cache read
@@ -676,7 +676,7 @@ group gL3FIR filter singlebit, cs_root_cause
     /** L3FIR[5]
      *  UE detected on L3 cache read
      */
-    (rL3FIR, bit(5)) ? l3_cache_ue;
+    (rL3FIR, bit(5)) ? l3_cache_ue_UERE;
 
     /** L3FIR[6]
      *  SUE detected on L3 cache read
@@ -691,7 +691,7 @@ group gL3FIR filter singlebit, cs_root_cause
     /** L3FIR[8]
      *  L3 cache write data UE from Power Bus
      */
-    (rL3FIR, bit(8)) ? self_th_1;
+    (rL3FIR, bit(8)) ? self_th_1_UERE;
 
     /** L3FIR[9]
      *  L3 cache write data sue from Power Bus
@@ -706,7 +706,7 @@ group gL3FIR filter singlebit, cs_root_cause
     /** L3FIR[11]
      *  L3 cache write data UE from L2
      */
-    (rL3FIR, bit(11)) ? l3_cache_ue;
+    (rL3FIR, bit(11)) ? l3_cache_ue_UERE;
 
     /** L3FIR[12]
      *  L3 cache write SUE from L2
@@ -756,7 +756,7 @@ group gL3FIR filter singlebit, cs_root_cause
     /** L3FIR[21]
      *  UE detected on PowerBus read for PPE
      */
-    (rL3FIR, bit(21)) ? self_th_1;
+    (rL3FIR, bit(21)) ? self_th_1_UERE;
 
     /** L3FIR[22]
      *  L3 PPE SUE
@@ -882,12 +882,12 @@ group gCMEFIR filter singlebit, cs_root_cause
     /** CMEFIR[8]
      *  SRAM Correctable Error
      */
-    (rCMEFIR, bit(8)) ? threshold_and_mask;
+    (rCMEFIR, bit(8)) ? threshold_and_mask_self;
 
     /** CMEFIR[9]
      *  Scrub timer tick, scrub still pending
      */
-    (rCMEFIR, bit(9)) ? threshold_and_mask;
+    (rCMEFIR, bit(9)) ? threshold_and_mask_self;
 
     /** CMEFIR[10]
      *  Block Copy Engine Error
@@ -902,37 +902,37 @@ group gCMEFIR filter singlebit, cs_root_cause
     /** CMEFIR[13]
      *  Dropout detected on Core0 Chiplet iVRM
      */
-    (rCMEFIR, bit(13)) ? threshold_and_mask;
+    (rCMEFIR, bit(13)) ? threshold_and_mask_self;
 
     /** CMEFIR[14]
      *  Dropout detected on Core1 Chiplet iVRM
      */
-    (rCMEFIR, bit(14)) ? threshold_and_mask;
+    (rCMEFIR, bit(14)) ? threshold_and_mask_self;
 
     /** CMEFIR[15]
      *  CME Dropout Cache Chiplet iVRM.
      */
-    (rCMEFIR, bit(15)) ? threshold_and_mask;
+    (rCMEFIR, bit(15)) ? threshold_and_mask_self;
 
     /** CMEFIR[16]
      *  CME Extreme Droop over time exceeded
      */
-    (rCMEFIR, bit(16)) ? threshold_and_mask;
+    (rCMEFIR, bit(16)) ? threshold_and_mask_self;
 
     /** CMEFIR[17]
      *  CME Large Droop exceeded
      */
-    (rCMEFIR, bit(17)) ? threshold_and_mask;
+    (rCMEFIR, bit(17)) ? threshold_and_mask_self;
 
     /** CMEFIR[18]
      *  CME Small Droop exceeded
      */
-    (rCMEFIR, bit(18)) ? threshold_and_mask;
+    (rCMEFIR, bit(18)) ? threshold_and_mask_self;
 
     /** CMEFIR[19]
      *  Detected non-thermometer code
      */
-    (rCMEFIR, bit(19)) ? threshold_and_mask;
+    (rCMEFIR, bit(19)) ? threshold_and_mask_self;
 
     /** CMEFIR[20]
      *  scom error
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_ex_actions.rule b/src/usr/diag/prdf/common/plat/p9/p9_ex_actions.rule
index c40fcb04e..92a57dfe4 100644
--- a/src/usr/diag/prdf/common/plat/p9/p9_ex_actions.rule
+++ b/src/usr/diag/prdf/common/plat/p9/p9_ex_actions.rule
@@ -31,8 +31,9 @@ actionclass l3_cache_ce
     funccall("cacheCeWorkaround");
 };
 
-actionclass l3_cache_ue
+actionclass l3_cache_ue_UERE
 {
+    SueSource;
     self_th_1;
     funccall("L3UE");
 };
@@ -58,8 +59,9 @@ actionclass l2_cache_ce
     funccall("cacheCeWorkaround");
 };
 
-actionclass l2_cache_ue
+actionclass l2_cache_ue_UERE
 {
+    SueSource;
     self_th_1;
     funccall("L2UE");
 };
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_mca.rule b/src/usr/diag/prdf/common/plat/p9/p9_mca.rule
index 707d13aed..9a2b0dfcf 100644
--- a/src/usr/diag/prdf/common/plat/p9/p9_mca.rule
+++ b/src/usr/diag/prdf/common/plat/p9/p9_mca.rule
@@ -523,7 +523,7 @@ group gMCAECCFIR filter priority( 14, 17, 37 ), # ensure UEs handled before NCEs
     /** MCAECCFIR[41]
      *  SCOM_PARITY_CLASS_STATUS
      */
-    (rMCAECCFIR, bit(41)) ? threshold_and_mask;
+    (rMCAECCFIR, bit(41)) ? threshold_and_mask_self;
 
     /** MCAECCFIR[42]
      *  SCOM_PARITY_CLASS_RECOVERABLE
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_mcs.rule b/src/usr/diag/prdf/common/plat/p9/p9_mcs.rule
index a5d379fbd..e528dface 100644
--- a/src/usr/diag/prdf/common/plat/p9/p9_mcs.rule
+++ b/src/usr/diag/prdf/common/plat/p9/p9_mcs.rule
@@ -234,7 +234,7 @@ group gMCFIR filter singlebit, cs_root_cause( 0, 6, 8, 9 )
     /** MCFIR[8]
      *  command list timeout
      */
-    (rMCFIR, bit(8)) ? level2_th_1;
+    (rMCFIR, bit(8)) ? threshold_and_mask_level2;
 
     /** MCFIR[9]
      *  channel 0 timeout
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_nimbus.rule b/src/usr/diag/prdf/common/plat/p9/p9_nimbus.rule
index 20b64cd1c..5c556c37a 100644
--- a/src/usr/diag/prdf/common/plat/p9/p9_nimbus.rule
+++ b/src/usr/diag/prdf/common/plat/p9/p9_nimbus.rule
@@ -2549,7 +2549,7 @@ group gOCCFIR filter singlebit, cs_root_cause
     /** OCCFIR[3]
      *  STOP_RECOVERY_NOTIFY_PRD
      */
-    (rOCCFIR, bit(3)) ? threshold_and_mask;
+    (rOCCFIR, bit(3)) ? threshold_and_mask_self;
 
     /** OCCFIR[4]
      *  OCC_HB_ERROR
@@ -2579,12 +2579,12 @@ group gOCCFIR filter singlebit, cs_root_cause
     /** OCCFIR[9]
      *  GPE0 asserted an error condition
      */
-    (rOCCFIR, bit(9)) ? threshold_and_mask;
+    (rOCCFIR, bit(9)) ? threshold_and_mask_self;
 
     /** OCCFIR[10]
      *  GPE1 asserted an error condition
      */
-    (rOCCFIR, bit(10)) ? threshold_and_mask;
+    (rOCCFIR, bit(10)) ? threshold_and_mask_self;
 
     /** OCCFIR[11]
      *  GPE2 asserted an error condition
@@ -2609,37 +2609,37 @@ group gOCCFIR filter singlebit, cs_root_cause
     /** OCCFIR[15]
      *  SRAM CE
      */
-    (rOCCFIR, bit(15)) ? threshold_and_mask;
+    (rOCCFIR, bit(15)) ? threshold_and_mask_self;
 
     /** OCCFIR[16]
      *  SRAM Read Error
      */
-    (rOCCFIR, bit(16)) ? threshold_and_mask;
+    (rOCCFIR, bit(16)) ? threshold_and_mask_self;
 
     /** OCCFIR[17]
      *  SRAM Write error
      */
-    (rOCCFIR, bit(17)) ? threshold_and_mask;
+    (rOCCFIR, bit(17)) ? threshold_and_mask_self;
 
     /** OCCFIR[18]
      *  SRAM ctrl detected pe on tank read data
      */
-    (rOCCFIR, bit(18)) ? threshold_and_mask;
+    (rOCCFIR, bit(18)) ? threshold_and_mask_self;
 
     /** OCCFIR[19]
      *  SRAM cntrl  detected OCI write data pe
      */
-    (rOCCFIR, bit(19)) ? threshold_and_mask;
+    (rOCCFIR, bit(19)) ? threshold_and_mask_self;
 
     /** OCCFIR[20]
      *  SRAM cntrl detected OCI byte enable PE
      */
-    (rOCCFIR, bit(20)) ? threshold_and_mask;
+    (rOCCFIR, bit(20)) ? threshold_and_mask_self;
 
     /** OCCFIR[21]
      *  SRAM controller detected OCI address PE
      */
-    (rOCCFIR, bit(21)) ? threshold_and_mask;
+    (rOCCFIR, bit(21)) ? threshold_and_mask_self;
 
     /** OCCFIR[22]
      *  GPE0_HALTED:
@@ -2694,57 +2694,57 @@ group gOCCFIR filter singlebit, cs_root_cause
     /** OCCFIR[32]
      *  OCB_DB_OCI_TIMEOUT
      */
-    (rOCCFIR, bit(32)) ? threshold_and_mask;
+    (rOCCFIR, bit(32)) ? threshold_and_mask_self;
 
     /** OCCFIR[33]
      *  OCB_DB_OCI_READ_DATA_PARITY
      */
-    (rOCCFIR, bit(33)) ? threshold_and_mask;
+    (rOCCFIR, bit(33)) ? threshold_and_mask_self;
 
     /** OCCFIR[34]
      *  OCB_DB_OCI_SLAVE_ERROR
      */
-    (rOCCFIR, bit(34)) ? threshold_and_mask;
+    (rOCCFIR, bit(34)) ? threshold_and_mask_self;
 
     /** OCCFIR[35]
      *  OCB_PIB_ADDR_PARITY_ERR
      */
-    (rOCCFIR, bit(35)) ? threshold_and_mask;
+    (rOCCFIR, bit(35)) ? threshold_and_mask_self;
 
     /** OCCFIR[36]
      *  OCB_PIB_DATA_PARITY_ERR
      */
-    (rOCCFIR, bit(36)) ? threshold_and_mask;
+    (rOCCFIR, bit(36)) ? threshold_and_mask_self;
 
     /** OCCFIR[37]
      *  OCB_IDC0_ERROR
      */
-    (rOCCFIR, bit(37)) ? threshold_and_mask;
+    (rOCCFIR, bit(37)) ? threshold_and_mask_self;
 
     /** OCCFIR[38]
      *  OCB_IDC1_ERROR
      */
-    (rOCCFIR, bit(38)) ? threshold_and_mask;
+    (rOCCFIR, bit(38)) ? threshold_and_mask_self;
 
     /** OCCFIR[39]
      *  OCB_IDC2_ERROR
      */
-    (rOCCFIR, bit(39)) ? threshold_and_mask;
+    (rOCCFIR, bit(39)) ? threshold_and_mask_self;
 
     /** OCCFIR[40]
      *  OCB_IDC3_ERROR
      */
-    (rOCCFIR, bit(40)) ? threshold_and_mask;
+    (rOCCFIR, bit(40)) ? threshold_and_mask_self;
 
     /** OCCFIR[41]
      *  SRT_FSM_ERR
      */
-    (rOCCFIR, bit(41)) ? threshold_and_mask;
+    (rOCCFIR, bit(41)) ? threshold_and_mask_self;
 
     /** OCCFIR[42]
      *  JTAGACC_ERR
      */
-    (rOCCFIR, bit(42)) ? threshold_and_mask;
+    (rOCCFIR, bit(42)) ? threshold_and_mask_self;
 
     /** OCCFIR[43]
      *  spare
@@ -2754,7 +2754,7 @@ group gOCCFIR filter singlebit, cs_root_cause
     /** OCCFIR[44]
      *  C405_ECC_UE
      */
-    (rOCCFIR, bit(44)) ? threshold_and_mask;
+    (rOCCFIR, bit(44)) ? threshold_and_mask_self;
 
     /** OCCFIR[45]
      *  C405_ECC_CE
@@ -2764,67 +2764,67 @@ group gOCCFIR filter singlebit, cs_root_cause
     /** OCCFIR[46]
      *  C405_OCI_MACHINECHECK
      */
-    (rOCCFIR, bit(46)) ? threshold_and_mask;
+    (rOCCFIR, bit(46)) ? threshold_and_mask_self;
 
     /** OCCFIR[47]
      *  SRAM_SPARE_DIRECT_ERROR0
      */
-    (rOCCFIR, bit(47)) ? threshold_and_mask;
+    (rOCCFIR, bit(47)) ? threshold_and_mask_self;
 
     /** OCCFIR[48]
      *  SRAM_SPARE_DIRECT_ERROR1
      */
-    (rOCCFIR, bit(48)) ? threshold_and_mask;
+    (rOCCFIR, bit(48)) ? threshold_and_mask_self;
 
     /** OCCFIR[49]
      *  SRAM_SPARE_DIRECT_ERROR2
      */
-    (rOCCFIR, bit(49)) ? threshold_and_mask;
+    (rOCCFIR, bit(49)) ? threshold_and_mask_self;
 
     /** OCCFIR[50]
      *  SRAM_SPARE_DIRECT_ERROR3
      */
-    (rOCCFIR, bit(50)) ? threshold_and_mask;
+    (rOCCFIR, bit(50)) ? threshold_and_mask_self;
 
     /** OCCFIR[51]
      *  GPE0_OCISLV_ERR
      */
-    (rOCCFIR, bit(51)) ? threshold_and_mask;
+    (rOCCFIR, bit(51)) ? threshold_and_mask_self;
 
     /** OCCFIR[52]
      *  GPE1_OCISLV_ERR
      */
-    (rOCCFIR, bit(52)) ? threshold_and_mask;
+    (rOCCFIR, bit(52)) ? threshold_and_mask_self;
 
     /** OCCFIR[53]
      *  GPE2_OCISLV_ERR
      */
-    (rOCCFIR, bit(53)) ? threshold_and_mask;
+    (rOCCFIR, bit(53)) ? threshold_and_mask_self;
 
     /** OCCFIR[54]
      *  GPE3_OCISLV_ERR
      */
-    (rOCCFIR, bit(54)) ? threshold_and_mask;
+    (rOCCFIR, bit(54)) ? threshold_and_mask_self;
 
     /** OCCFIR[55]
      *  C405ICU_M_TIMEOUT
      */
-    (rOCCFIR, bit(55)) ? threshold_and_mask;
+    (rOCCFIR, bit(55)) ? defaultMaskedError;
 
     /** OCCFIR[56]
      *  C405DCU_M_TIMEOUT
      */
-    (rOCCFIR, bit(56)) ? threshold_and_mask;
+    (rOCCFIR, bit(56)) ? threshold_and_mask_self;
 
     /** OCCFIR[57]
      *  OCC_COMPLEX_FAULT
      */
-    (rOCCFIR, bit(57)) ? threshold_and_mask;
+    (rOCCFIR, bit(57)) ? threshold_and_mask_self;
 
     /** OCCFIR[58]
      *  OCC_COMPLEX_NOTIFY
      */
-    (rOCCFIR, bit(58)) ? threshold_and_mask;
+    (rOCCFIR, bit(58)) ? threshold_and_mask_self;
 
     /** OCCFIR[59:61]
      *  spare
@@ -5381,7 +5381,7 @@ group gPBCENTFIR filter singlebit, cs_root_cause
     /** PBCENTFIR[5]
      *  pb cresp addr error
      */
-    (rPBCENTFIR, bit(5)) ? threshold_and_mask;
+    (rPBCENTFIR, bit(5)) ? threshold_and_mask_self;
 
     /** PBCENTFIR[6]
      *  pb cresp error
@@ -5538,22 +5538,22 @@ group gPBPPEFIR filter singlebit, cs_root_cause
     /** PBPPEFIR[0]
      *  PPE asserted an internally detected err
      */
-    (rPBPPEFIR, bit(0)) ? threshold_and_mask;
+    (rPBPPEFIR, bit(0)) ? threshold_and_mask_self;
 
     /** PBPPEFIR[1]
      *  PPE err on ext interface to the Mem
      */
-    (rPBPPEFIR, bit(1)) ? threshold_and_mask;
+    (rPBPPEFIR, bit(1)) ? threshold_and_mask_self;
 
     /** PBPPEFIR[2]
      *  PPE halted due to lack of progress.
      */
-    (rPBPPEFIR, bit(2)) ? threshold_and_mask;
+    (rPBPPEFIR, bit(2)) ? threshold_and_mask_self;
 
     /** PBPPEFIR[3]
      *  PPE halted on breakpoint event.
      */
-    (rPBPPEFIR, bit(3)) ? threshold_and_mask;
+    (rPBPPEFIR, bit(3)) ? threshold_and_mask_self;
 
     /** PBPPEFIR[4]
      *  PPE watchdog expired
@@ -5573,17 +5573,17 @@ group gPBPPEFIR filter singlebit, cs_root_cause
     /** PBPPEFIR[7]
      *  SRAM uncorrectable error
      */
-    (rPBPPEFIR, bit(7)) ? threshold_and_mask;
+    (rPBPPEFIR, bit(7)) ? threshold_and_mask_self;
 
     /** PBPPEFIR[8]
      *  SRM correctable error
      */
-    (rPBPPEFIR, bit(8)) ? threshold_and_mask;
+    (rPBPPEFIR, bit(8)) ? threshold_and_mask_self;
 
     /** PBPPEFIR[9]
      *  Scrub timer tick while scrub pending
      */
-    (rPBPPEFIR, bit(9)) ? threshold_and_mask;
+    (rPBPPEFIR, bit(9)) ? threshold_and_mask_self;
 
     /** PBPPEFIR[10]
      *  reserved
@@ -5784,7 +5784,7 @@ group gPBAFIR filter singlebit, cs_root_cause
     /** PBAFIR[32]
      *  PBAXRCV Low data before High Data
      */
-    (rPBAFIR, bit(32)) ? self_th_1;
+    (rPBAFIR, bit(32)) ? defaultMaskedError;
 
     /** PBAFIR[33]
      *  PBAXRCV low data timeout
@@ -5799,7 +5799,7 @@ group gPBAFIR filter singlebit, cs_root_cause
     /** PBAFIR[35]
      *  Illegal PBAX Flow.
      */
-    (rPBAFIR, bit(35)) ? self_th_1;
+    (rPBAFIR, bit(35)) ? defaultMaskedError;
 
     /** PBAFIR[36]
      *  PBA engine retry threshold reached
@@ -6403,7 +6403,7 @@ group gNMMUFIR filter singlebit, cs_root_cause
     /** NMMUFIR[11]
      *  SLB multi-hit error detected.
      */
-    (rNMMUFIR, bit(11)) ? level2_th_1;
+    (rNMMUFIR, bit(11)) ? threshold_and_mask_self;
 
     /** NMMUFIR[12]
      *  TLB directory parity error detected.
@@ -6423,7 +6423,7 @@ group gNMMUFIR filter singlebit, cs_root_cause
     /** NMMUFIR[15]
      *  TLB multi-hit error detected.
      */
-    (rNMMUFIR, bit(15)) ? level2_th_1;
+    (rNMMUFIR, bit(15)) ? threshold_and_mask_self;
 
     /** NMMUFIR[16]
      *  Segment fault detected .
@@ -6839,7 +6839,7 @@ group gINTCQFIR filter singlebit, cs_root_cause
     /** INTCQFIR[47]
      *  INT_CQ_FIR_PGM_DBG_ACCESS:
      */
-    (rINTCQFIR, bit(47)) ? threshold_and_mask;
+    (rINTCQFIR, bit(47)) ? threshold_and_mask_self;
 
     /** INTCQFIR[48]
      *  spare
@@ -8464,22 +8464,22 @@ group gXBPPEFIR filter singlebit, cs_root_cause
     /** XBPPEFIR[0]
      *  PPE general error.
      */
-    (rXBPPEFIR, bit(0)) ? threshold_and_mask;
+    (rXBPPEFIR, bit(0)) ? threshold_and_mask_self;
 
     /** XBPPEFIR[1]
      *  PPE general error.
      */
-    (rXBPPEFIR, bit(1)) ? threshold_and_mask;
+    (rXBPPEFIR, bit(1)) ? threshold_and_mask_self;
 
     /** XBPPEFIR[2]
      *  PPE general error.
      */
-    (rXBPPEFIR, bit(2)) ? threshold_and_mask;
+    (rXBPPEFIR, bit(2)) ? threshold_and_mask_self;
 
     /** XBPPEFIR[3]
      *  PPE general error.
      */
-    (rXBPPEFIR, bit(3)) ? threshold_and_mask;
+    (rXBPPEFIR, bit(3)) ? threshold_and_mask_self;
 
     /** XBPPEFIR[4]
      *  PPE halted.
@@ -8499,7 +8499,7 @@ group gXBPPEFIR filter singlebit, cs_root_cause
     /** XBPPEFIR[7]
      *  Arb missed scrub tick.
      */
-    (rXBPPEFIR, bit(7)) ? threshold_and_mask;
+    (rXBPPEFIR, bit(7)) ? threshold_and_mask_self;
 
     /** XBPPEFIR[8]
      *  Arb ary ue error.
@@ -8509,7 +8509,7 @@ group gXBPPEFIR filter singlebit, cs_root_cause
     /** XBPPEFIR[9]
      *  Arb ary ce error.
      */
-    (rXBPPEFIR, bit(9)) ? threshold_and_mask;
+    (rXBPPEFIR, bit(9)) ? threshold_and_mask_self;
 
     /** XBPPEFIR[10]
      *  spare
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_obus.rule b/src/usr/diag/prdf/common/plat/p9/p9_obus.rule
index d6767c995..86669fd77 100644
--- a/src/usr/diag/prdf/common/plat/p9/p9_obus.rule
+++ b/src/usr/diag/prdf/common/plat/p9/p9_obus.rule
@@ -466,12 +466,12 @@ group gIOOLFIR filter singlebit, cs_root_cause
     /** IOOLFIR[6]
      *  link0 crc error
      */
-    (rIOOLFIR, bit(6)) ? threshold_and_mask;
+    (rIOOLFIR, bit(6)) ? threshold_and_mask_self;
 
     /** IOOLFIR[7]
      *  link1 crc error
      */
-    (rIOOLFIR, bit(7)) ? threshold_and_mask;
+    (rIOOLFIR, bit(7)) ? threshold_and_mask_self;
 
     /** IOOLFIR[8]
      *  link0 nak received
@@ -506,22 +506,22 @@ group gIOOLFIR filter singlebit, cs_root_cause
     /** IOOLFIR[14]
      *  link0 sl ecc correctable
      */
-    (rIOOLFIR, bit(14)) ? threshold_and_mask;
+    (rIOOLFIR, bit(14)) ? threshold_and_mask_self;
 
     /** IOOLFIR[15]
      *  link1 sl ecc correctable
      */
-    (rIOOLFIR, bit(15)) ? threshold_and_mask;
+    (rIOOLFIR, bit(15)) ? threshold_and_mask_self;
 
     /** IOOLFIR[16]
      *  link0 sl ecc ue
      */
-    (rIOOLFIR, bit(16)) ? threshold_and_mask;
+    (rIOOLFIR, bit(16)) ? threshold_and_mask_self;
 
     /** IOOLFIR[17]
      *  link1 sl ecc ue
      */
-    (rIOOLFIR, bit(17)) ? threshold_and_mask;
+    (rIOOLFIR, bit(17)) ? threshold_and_mask_self;
 
     /** IOOLFIR[18]
      *  link0 retrain threshold
@@ -626,12 +626,12 @@ group gIOOLFIR filter singlebit, cs_root_cause
     /** IOOLFIR[38]
      *  link0 prbs select error
      */
-    (rIOOLFIR, bit(38)) ? threshold_and_mask;
+    (rIOOLFIR, bit(38)) ? threshold_and_mask_self;
 
     /** IOOLFIR[39]
      *  link1 prbs select error
      */
-    (rIOOLFIR, bit(39)) ? threshold_and_mask;
+    (rIOOLFIR, bit(39)) ? threshold_and_mask_self;
 
     /** IOOLFIR[40]
      *  link0 tcomplete bad
@@ -671,22 +671,22 @@ group gIOOLFIR filter singlebit, cs_root_cause
     /** IOOLFIR[48]
      *  link0 npu error
      */
-    (rIOOLFIR, bit(48)) ? threshold_and_mask;
+    (rIOOLFIR, bit(48)) ? threshold_and_mask_self;
 
     /** IOOLFIR[49]
      *  link1 npu error
      */
-    (rIOOLFIR, bit(49)) ? threshold_and_mask;
+    (rIOOLFIR, bit(49)) ? threshold_and_mask_self;
 
     /** IOOLFIR[50]
      *  linkx npu error
      */
-    (rIOOLFIR, bit(50)) ? threshold_and_mask;
+    (rIOOLFIR, bit(50)) ? threshold_and_mask_self;
 
     /** IOOLFIR[51]
      *  osc switch
      */
-    (rIOOLFIR, bit(51)) ? threshold_and_mask;
+    (rIOOLFIR, bit(51)) ? threshold_and_mask_self;
 
     /** IOOLFIR[52]
      *  link0 correctable array error
@@ -837,7 +837,7 @@ group gOBPPEFIR filter singlebit, cs_root_cause
     /** OBPPEFIR[7]
      *  PPE Arb missed scrub tick.
      */
-    (rOBPPEFIR, bit(7)) ? threshold_and_mask;
+    (rOBPPEFIR, bit(7)) ? threshold_and_mask_self;
 
     /** OBPPEFIR[8]
      *  PPE  Arb ary ue error.
@@ -847,7 +847,7 @@ group gOBPPEFIR filter singlebit, cs_root_cause
     /** OBPPEFIR[9]
      *  PPE Arb ary ce error.
      */
-    (rOBPPEFIR, bit(9)) ? threshold_and_mask;
+    (rOBPPEFIR, bit(9)) ? threshold_and_mask_self;
 
     /** OBPPEFIR[10]
      *  spare
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_xbus.rule b/src/usr/diag/prdf/common/plat/p9/p9_xbus.rule
index 1272d7f57..450e40ed4 100644
--- a/src/usr/diag/prdf/common/plat/p9/p9_xbus.rule
+++ b/src/usr/diag/prdf/common/plat/p9/p9_xbus.rule
@@ -417,12 +417,12 @@ group gIOELFIR filter singlebit, cs_root_cause
     /** IOELFIR[6]
      *  link0 crc error
      */
-    (rIOELFIR, bit(6)) ? threshold_and_mask;
+    (rIOELFIR, bit(6)) ? threshold_and_mask_self;
 
     /** IOELFIR[7]
      *  link1 crc error
      */
-    (rIOELFIR, bit(7)) ? threshold_and_mask;
+    (rIOELFIR, bit(7)) ? threshold_and_mask_self;
 
     /** IOELFIR[8]
      *  link0 nak received
@@ -457,22 +457,22 @@ group gIOELFIR filter singlebit, cs_root_cause
     /** IOELFIR[14]
      *  link0 sl ecc correctable
      */
-    (rIOELFIR, bit(14)) ? threshold_and_mask;
+    (rIOELFIR, bit(14)) ? threshold_and_mask_self;
 
     /** IOELFIR[15]
      *  link1 sl ecc correctable
      */
-    (rIOELFIR, bit(15)) ? threshold_and_mask;
+    (rIOELFIR, bit(15)) ? threshold_and_mask_self;
 
     /** IOELFIR[16]
      *  link0 sl ecc ue
      */
-    (rIOELFIR, bit(16)) ? threshold_and_mask;
+    (rIOELFIR, bit(16)) ? threshold_and_mask_self;
 
     /** IOELFIR[17]
      *  link1 sl ecc ue
      */
-    (rIOELFIR, bit(17)) ? threshold_and_mask;
+    (rIOELFIR, bit(17)) ? threshold_and_mask_self;
 
     /** IOELFIR[18:39]
      *  spare