PRD:Masked NXAS FIR

Accelerator switchboard shall not be supported. FIR is masked.

Change-Id: Iab9360125eb502cfd8c6910808a39e2e40f39c5e
RTC:92896
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/7557
Reviewed-by: Zane Shelley <zshelle@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7710
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

2 files changed, 3 insertions, 259 deletions

diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PB.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PB.rule
index cd1818e39..7fd30335b 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PB.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PB.rule
@@ -88,7 +88,7 @@ group gPbChipletFir filter singlebit
     /** PB_CHIPLET_FIR[15]
      *  Attention from NXASFIR
      */
-    (PbChipletFir, bit(15)) ? analyze(gNxAsFir);
+    (PbChipletFir, bit(15)) ? defaultMaskedError;
 
     /** PB_CHIPLET_FIR[16]
      *  Attention from ENHCAFIR
@@ -539,236 +539,6 @@ group gNxCqFir filter singlebit
 };
 
 ################################################################################
-# PB Chiplet NXASFIR
-################################################################################
-# based on p8dd1_mss_FFDC_60.xls
-################################################################################
-
-rule NxAsFir
-{
-    CHECK_STOP:  NXASFIR & ~NXASFIR_MASK & ~NXASFIR_ACT0 & ~NXASFIR_ACT1;
-    RECOVERABLE: NXASFIR & ~NXASFIR_MASK & ~NXASFIR_ACT0 &  NXASFIR_ACT1;
-};
-
-group gNxAsFir filter singlebit
-{
-    /** NXASFIR[0]
-     *  SND_ARY_UE
-     */
-    (NxAsFir, bit(0)) ? calloutNxASThr1;
-
-    /** NXASFIR[1]
-     *  MMIO_DAT_UE
-     */
-    (NxAsFir, bit(1)) ? defaultMaskedError;
-
-    /** NXASFIR[2]
-     *  COPREQ_DAT_UE
-     */
-    (NxAsFir, bit(2)) ? defaultMaskedError;
-
-    /** NXASFIR[3]
-     *  PBCQ_Q_INFO_PE
-     */
-    (NxAsFir, bit(3)) ? defaultMaskedError;
-
-    /** NXASFIR[4]
-     *  RCMD0_ADDR_PE
-     */
-    (NxAsFir, bit(4)) ? calloutNxASThr1;
-
-    /** NXASFIR[5]
-     *  RCMD0_TTAG_PE
-     */
-    (NxAsFir, bit(5)) ? calloutNxASThr1;
-
-    /** NXASFIR[6]
-     *  RCMD1_ADDR_PE
-     */
-    (NxAsFir, bit(6)) ? calloutNxASThr1;
-
-    /** NXASFIR[7]
-     *  RCMD1_TTAG_PE
-     */
-    (NxAsFir, bit(7)) ? calloutNxASThr1;
-
-    /** NXASFIR[8]
-     *  MAL_FMD_MMIO_ST
-     */
-    (NxAsFir, bit(8)) ? defaultMaskedError;
-
-    /** NXASFIR[9]
-     *  DATA_HANG
-     */
-    (NxAsFir, bit(9)) ? calloutNxASThr1;
-
-    /** NXASFIR[10]
-     *  CANNOT_RTY_ERR
-     */
-    (NxAsFir, bit(10)) ? defaultMaskedError;
-
-    /** NXASFIR[11]
-     *  CMPL_CNT_ERR
-     */
-    (NxAsFir, bit(11)) ? defaultMaskedError;
-
-    /** NXASFIR[12]
-     *  MULT_CAM_HIT_ERR
-     */
-    (NxAsFir, bit(12)) ? defaultMaskedError;
-
-    /** NXASFIR[13]
-     *  FUTURE_ERR_1
-     */
-    (NxAsFir, bit(13)) ? defaultMaskedError;
-
-    /** NXASFIR[14]
-     *  FL_FIFO_OVFLW
-     */
-    (NxAsFir, bit(14)) ? calloutNxASThr1;
-
-    /** NXASFIR[15]
-     *  CMD_TO_INVALID_RW
-     */
-    (NxAsFir, bit(15)) ? defaultMaskedError;
-
-    /** NXASFIR[16]
-     *  DMA_WL_UE
-     */
-    (NxAsFir, bit(16)) ? calloutNxASThr1;
-
-    /** NXASFIR[17]
-     *  CREDWT_RTY_ERR
-     */
-    (NxAsFir, bit(17)) ? defaultMaskedError;
-
-    /** NXASFIR[18]
-     *  NOTIFY_RTY_ERR
-     */
-    (NxAsFir, bit(18)) ? defaultMaskedError;
-
-    /** NXASFIR[19]
-     *  RCV_TAB_UE
-     */
-    (NxAsFir, bit(19)) ? calloutNxASThr1;
-
-    /** NXASFIR[20]
-     *  FIFO_ADR_TAB_UE
-     */
-    (NxAsFir, bit(20)) ? calloutNxASThr1;
-
-    /** NXASFIR[21]
-     *  MMIO_CR_DARY_UE
-     */
-    (NxAsFir, bit(21)) ? calloutNxASThr1;
-
-    /** NXASFIR[22]
-     *  NOTIF_ARY_UE
-     */
-    (NxAsFir, bit(22)) ? calloutNxASThr1;
-
-    /** NXASFIR[23]
-     *  INTR_ARY_UE
-     */
-    (NxAsFir, bit(23)) ? calloutNxASThr1;
-
-    /** NXASFIR[24]
-     *  CR0_ATAG_PE
-     */
-    (NxAsFir, bit(24)) ? calloutNxASThr1;
-
-    /** NXASFIR[25]
-     *  CR0_TTAG_PE
-     */
-    (NxAsFir, bit(25)) ? calloutNxASThr1;
-
-    /** NXASFIR[26]
-     *  CR1_ATAG_PE
-     */
-    (NxAsFir, bit(26)) ? calloutNxASThr1;
-
-    /** NXASFIR[27]
-     *  CR1_TTAG_PE
-     */
-    (NxAsFir, bit(27)) ? calloutNxASThr1;
-
-    /** NXASFIR[28]
-     *  CW_ADR_ERR
-     */
-    (NxAsFir, bit(28)) ? defaultMaskedError;
-
-    /** NXASFIR[29]
-     *  INTR_RTY_CNT_EXP
-     */
-    (NxAsFir, bit(29)) ? defaultMaskedError;
-
-    /** NXASFIR[30]
-     *  EG_OVFLW
-     */
-    (NxAsFir, bit(30)) ? calloutNxASThr1;
-
-    /** NXASFIR[31]
-     *  MULT_PM_HIT
-     */
-    (NxAsFir, bit(31)) ? defaultMaskedError;
-
-    /** NXASFIR[32]
-     *  EG_SCOM_ERR
-     */
-    (NxAsFir, bit(32)) ? defaultMaskedError;
-
-    /** NXASFIR[33]
-     *  UNUSUAL_EG_SCENARIO
-     */
-    (NxAsFir, bit(33)) ? defaultMaskedError;
-
-    /** NXASFIR[34]
-     *  DSLC_INTF_PE
-     */
-    (NxAsFir, bit(34)) ? defaultMaskedError;
-
-    /** NXASFIR[35]
-     *  AS_IN_CE
-     */
-    (NxAsFir, bit(35)) ? calloutNxASThr32;
-
-    /** NXASFIR[36]
-     *  AS_IN_UNSUP_CFG
-     */
-    (NxAsFir, bit(36)) ? defaultMaskedError;
-
-    /** NXASFIR[37]
-     * COPREQ_CRESP_ERR
-     */
-    (NxAsFir, bit(37)) ? defaultMaskedError;
-
-    /** NXASFIR[38]
-     *  CREDWT_CRESP_ERR
-     */
-    (NxAsFir, bit(38)) ? defaultMaskedError;
-
-    /** NXASFIR[39]
-     *  AS_IN_SP_FIR
-     */
-    (NxAsFir, bit(39)) ? defaultMaskedError;
-
-    /** NXASFIR[40]
-     *  AS_EG_CE
-     */
-    (NxAsFir, bit(40)) ? calloutNxASThr32;
-
-    /** NXASFIR[41]
-     *  SCOM_ERR
-     */
-    (NxAsFir, bit(41)) ? defaultMaskedError;
-
-    /** NXASFIR[42]
-     *  SCOM_ERR_DUP
-     */
-    (NxAsFir, bit(42)) ? defaultMaskedError;
-};
-
-################################################################################
 # PB Chiplet NXCXAFIR
 ################################################################################
 
@@ -3333,14 +3103,6 @@ actionclass calloutNx
     callout(connected(TYPE_NX, 0), MRU_MED);
 };
 
-/** callout Nx-AS connected to Proc*/
-#RTC 86494 we may not support NX-AS. In that case we may endup masking
-#the relevant bits.
-actionclass calloutNxASThr1
-{
-    TBDDefaultCallout;
-};
-
 actionclass calloutNxASThr32
 {
     TBDDefaultCallout;
diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PB.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PB.rule
index 8ac9987ad..c87e9163b 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PB.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PB.rule
@@ -178,12 +178,12 @@
     # PB Chiplet NXASFIR
     ############################################################################
 
+    # NXASFIR has been modeled merely to collect FFDC. No attentions are
+    # expected from it.
     register NXASFIR
     {
         name        "EN.NX.AS.FIR_REG";
         scomaddr    0x020130c0;
-        reset       (&, 0x020130c1);
-        mask        (|, 0x020130c5);
         capture     group default;
     };
 
@@ -194,24 +194,6 @@
         capture     group default;
     };
 
-    register NXASFIR_ACT0
-    {
-        name        "EN.NX.AS.FIR_ACTION0_REG";
-        scomaddr    0x020130c6;
-        capture     type secondary;
-        capture     group default;
-        capture     req nonzero("NXASFIR");
-    };
-
-    register NXASFIR_ACT1
-    {
-        name        "EN.NX.AS.FIR_ACTION1_REG";
-        scomaddr    0x020130c7;
-        capture     type secondary;
-        capture     group default;
-        capture     req nonzero("NXASFIR");
-    };
-
     ############################################################################
     # PB Chiplet NXCXAFIR
     ############################################################################