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| author | Zane Shelley <zshelle@us.ibm.com> | 2018-11-01 11:51:15 -0500 |
|---|---|---|
| committer | Zane C. Shelley <zshelle@us.ibm.com> | 2018-11-08 10:40:28 -0600 |
| commit | 7f716fe1404d8eea1e2d6fe16ad9f3e2f7337feb (patch) | |
| tree | 57c47665f40570b77b6aceb0b722439c2facd084 /src/usr/diag/prdf/common/plat | |
| parent | e8825169c84ca4185894ec34c5022ddc2cd6a9f0 (diff) | |
| download | talos-hostboot-7f716fe1404d8eea1e2d6fe16ad9f3e2f7337feb.tar.gz talos-hostboot-7f716fe1404d8eea1e2d6fe16ad9f3e2f7337feb.zip | |
PRD: Remove remaining P8 code
Change-Id: Icb74c251a718091071c909b1832b58615345dc5d
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68279
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68511
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/usr/diag/prdf/common/plat')
34 files changed, 0 insertions, 16885 deletions
diff --git a/src/usr/diag/prdf/common/plat/pegasus/Ex.rule b/src/usr/diag/prdf/common/plat/pegasus/Ex.rule deleted file mode 100755 index cfc81481c..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Ex.rule +++ /dev/null @@ -1,2107 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Ex.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -################################################################################ -# -# Scope: -# Registers and actions for the following chiplets: -# Note that only addresses for EX0 will be used. -# -# Chiplet Register Addresses Description -# ======= ======================= ============================================ -# EX0 0x10000000 - 0x10FFFFFF EX0 pervasive logic -# EX1 0x11000000 - 0x11FFFFFF EX1 pervasive logic -# EX2 0x12000000 - 0x12FFFFFF EX2 pervasive logic -# EX3 0x13000000 - 0x13FFFFFF EX3 pervasive logic -# EX4 0x14000000 - 0x14FFFFFF EX4 pervasive logic -# EX5 0x15000000 - 0x15FFFFFF EX5 pervasive logic -# EX6 0x16000000 - 0x16FFFFFF EX6 pervasive logic -# EX7 0x17000000 - 0x17FFFFFF EX7 pervasive logic -# EX8 0x18000000 - 0x18FFFFFF EX8 pervasive logic -# EX9 0x19000000 - 0x19FFFFFF EX9 pervasive logic -# EX10 0x1A000000 - 0x1AFFFFFF EX10 pervasive logic -# EX11 0x1B000000 - 0x1BFFFFFF EX11 pervasive logic -# EX12 0x1C000000 - 0x1CFFFFFF EX12 pervasive logic -# EX13 0x1D000000 - 0x1DFFFFFF EX13 pervasive logic -# EX14 0x1E000000 - 0x1EFFFFFF EX14 pervasive logic -# EX15 0x1F000000 - 0x1FFFFFFF EX15 pervasive logic -# -################################################################################ - -chip Ex -{ - name "Power8 EX Chiplet"; - targettype TYPE_EX; - sigoff 0x8000; - dump DUMP_CONTENT_HW; - scomlen 64; - -.include "prdfP8ExExtraSig.H"; - - ############################################################################# - # # - # ###### # - # # # ###### #### ### #### ##### ###### ##### #### # - # # # # # # # # # # # # # # - # ###### ##### # # #### # ##### # # #### # - # # # # # ### # # # # ##### # # - # # # # # # # # # # # # # # # # - # # # ###### #### ### #### # ###### # # #### # - # # - ############################################################################# - - ############################################################################ - # EX Chiplet Registers - ############################################################################ - - register EX_CHIPLET_CS_FIR - { - name "EX00.TP.ECO_DOM.XFIR"; - scomaddr 0x10040000; - capture group default; - }; - - register EX_CHIPLET_RE_FIR - { - name "EX00.TP.ECO_DOM.RFIR"; - scomaddr 0x10040001; - capture group default; - }; - - register EX_CHIPLET_FIR_MASK - { - name "EX00.TP.ECO_DOM.FIR_MASK"; - scomaddr 0x10040002; - capture group default; - }; - - # EX special attention registers - Used for FFDC only - # Currently, all analysis of these registers is done by ATTN. - - register EX_CHIPLET_SPA - { - name "EX00.TP.ECO_DOM.EPS.FIR.SPATTN"; - scomaddr 0x10040004; - capture group default; - }; - - ############################################################################ - # EX Chiplet LFIR - ############################################################################ - - register EX_LFIR - { - name "EX00.TP.ECO_DOM.LOCAL_FIR"; - scomaddr 0x1004000a; - reset (&, 0x1004000b); - mask (|, 0x1004000f); - capture group default; - }; - - register EX_LFIR_MASK - { - name "EX00.TP.ECO_DOM.EPS.FIR.LOCAL_FIR_MASK"; - scomaddr 0x1004000d; - capture group default; - }; - - register EX_LFIR_ACT0 - { - name "EX00.TP.ECO_DOM.EPS.FIR.LOCAL_FIR_ACTION0"; - scomaddr 0x10040010; - capture type secondary; - capture group default; - capture req nonzero("EX_LFIR"); - }; - - register EX_LFIR_ACT1 - { - name "EX00.TP.ECO_DOM.EPS.FIR.LOCAL_FIR_ACTION1"; - scomaddr 0x10040011; - capture type secondary; - capture group default; - capture req nonzero("EX_LFIR"); - }; - - ############################################################################ - # EX Chiplet COREFIR - ############################################################################ - - register COREFIR - { - name "EX00.EC.PC.PC_NE.FIR.CORE_FIR"; - scomaddr 0x10013100; - mask (|, 0x10013105); - capture group default; - }; - - register COREFIR_MASK - { - name "EX00.EC.PC.PC_NE.FIR.CORE_FIRMASK"; - scomaddr 0x10013103; - capture group default; - }; - - register COREFIR_ACT0 - { - name "EX00.EC.PC.PC_NE.FIR.CORE_ACTION0"; - scomaddr 0x10013106; - capture type secondary; - capture group default; -# As a P6 workaround that was never fixed in P7 or P8, recoverable attentions -# are reported via the WOF register. Therefore, we cannot add this line -# otherwise we could end up not capturing the required FFDC. -# capture req nonzero("COREFIR"); - }; - - register COREFIR_ACT1 - { - name "EX00.EC.PC.PC_NE.FIR.CORE_ACTION1"; - scomaddr 0x10013107; - capture type secondary; - capture group default; -# As a P6 workaround that was never fixed in P7 or P8, recoverable attentions -# are reported via the WOF register. Therefore, we cannot add this line -# otherwise we could end up not capturing the required FFDC. -# capture req nonzero("COREFIR"); - }; - - register COREFIRWOF - { - name "Core FIR WOF"; - scomaddr 0x10013108; - reset (|, 0x10013108); - capture group default; - }; - - ########################################################################### - # EX Chiplet COREFIR Error Report Registers - ########################################################################### - - register PCNE_REG0_HOLD_OUT - { - name "EXP.EC.PC.PC_NE.PCNE_REG0_HOLD_OUT"; - scomaddr 0x1001300D; - capture group default; - capture group CerrRegs; - }; - - register PCNE_REG1_HOLD_OUT - { - name "EXP.EC.PC.PC_NE.PCNE_REG1_HOLD_OUT"; - scomaddr 0x1001301D; - capture group default; - capture group CerrRegs; - }; - - register PCNE_REG2_HOLD_OUT - { - name "EXP.EC.PC.PC_NE.PCNE_REG2_HOLD_OUT"; - scomaddr 0x1001302D; - capture group default; - capture group CerrRegs; - }; - - register PCNE_REG3_HOLD_OUT - { - name "EXP.EC.PC.PC_NE.PCNE_REG3_HOLD_OUT"; - scomaddr 0x1001303D; - capture group default; - capture group CerrRegs; - }; - - register PCNE_REG4_HOLD_OUT - { - name "EXP.EC.PC.PC_NE.PCNE_REG4_HOLD_OUT"; - scomaddr 0x1001304D; - capture group default; - capture group CerrRegs; - }; - - register PCNE_REG5_HOLD_OUT - { - name "EXP.EC.PC.PC_NE.PCNE_REG5_HOLD_OUT"; - scomaddr 0x1001305D; - capture group default; - capture group CerrRegs; - }; - - register PCNE_REG6_HOLD_OUT - { - name "EXP.EC.PC.PC_NE.PCNE_REG6_HOLD_OUT"; - scomaddr 0x1001306D; - capture group default; - capture group CerrRegs; - }; - - register PCNE_REG7_HOLD_OUT - { - name "EXP.EC.PC.PC_NE.PCNE_REG7_HOLD_OUT"; - scomaddr 0x1001307D; - capture group default; - capture group CerrRegs; - }; - - register PCNW_REG0_HOLD_OUT - { - name "EXP.EC.PC.PC_NW.PCNW_REG0_HOLD_OUT"; - scomaddr 0x100132A9; - capture group default; - capture group CerrRegs; - }; - - register PCNW_REG1_HOLD_OUT - { - name "EXP.EC.PC.PC_NW.PCNW_REG1_HOLD_OUT"; - scomaddr 0x100132AA; - capture group default; - capture group CerrRegs; - }; - - register PCS_REG0_HOLD_OUT - { - name "EXP.EC.PC.PC_S.PCS_REG0_HOLD_OUT"; - scomaddr 0x100132CB; - capture group default; - capture group CerrRegs; - }; - - register PCS_REG1_HOLD_OUT - { - name "EXP.EC.PC.PC_S.PCS_REG1_HOLD_OUT"; - scomaddr 0x100132D5; - capture req funccall("isMuranoVeniceNotDD1"); - capture group default; - capture group CerrRegs; - }; - - register FXU_REG0_HOLD_OUT - { - name "EXP.EC.FX.FXU_REG0_HOLD_OUT"; - scomaddr 0x10013300; - capture group default; - capture group CerrRegs; - }; - - register FXU_REG1_HOLD_OUT - { - name "EXP.EC.FX.FXU_REG1_HOLD_OUT"; - scomaddr 0x10013301; - capture group default; - capture group CerrRegs; - }; - - register FXU_REG2_HOLD_OUT - { - name "EXP.EC.FX.FXU_REG2_HOLD_OUT"; - scomaddr 0x10013302; - capture group default; - capture group CerrRegs; - }; - - register FXU_REG3_HOLD_OUT - { - name "EXP.EC.FX.FXU_REG3_HOLD_OUT"; - scomaddr 0x10013303; - capture group default; - capture group CerrRegs; - }; - - register FXU_REG4_HOLD_OUT - { - name "EXP.EC.FX.FXU_REG4_HOLD_OUT"; - scomaddr 0x10013304; - capture group default; - capture group CerrRegs; - }; - - register ISU_REG0_ISU_HOLD_OUT - { - name "EXP.EC.SD.ISU_REG0_HOLD_OUT"; - scomaddr 0x10013340; - capture group default; - capture group CerrRegs; - }; - - register ISU_REG1_ISU_HOLD_OUT - { - name "EXP.EC.SD.ISU_REG1_HOLD_OUT"; - scomaddr 0x10013341; - capture group default; - capture group CerrRegs; - }; - - register ISU_REG2_ISU_HOLD_OUT - { - name "EXP.EC.SD.ISU_REG2_HOLD_OUT"; - scomaddr 0x10013342; - capture group default; - capture group CerrRegs; - }; - - register ISU_REG3_ISU_HOLD_OUT - { - name "EXP.EC.SD.ISU_REG3_HOLD_OUT"; - scomaddr 0x10013343; - capture group default; - capture group CerrRegs; - }; - - register ISU_REG4_ISU_HOLD_OUT - { - name "EXP.EC.SD.ISU_REG4_HOLD_OUT"; - scomaddr 0x10013344; - capture group default; - capture group CerrRegs; - }; - - register ISU_REG5_ISU_HOLD_OUT - { - name "EXP.EC.SD.ISU_REG5_HOLD_OUT"; - scomaddr 0x10013345; - capture group default; - capture group CerrRegs; - }; - - register ISU_REG6_ISU_HOLD_OUT - { - name "EXP.EC.SD.ISU_REG6_HOLD_OUT"; - scomaddr 0x10013346; - capture group default; - capture group CerrRegs; - }; - - register ISU_REG7_ISU_HOLD_OUT - { - name "EXP.EC.SD.ISU_REG7_HOLD_OUT"; - scomaddr 0x10013347; - capture group default; - capture group CerrRegs; - }; - - register ISU_REG8_ISU_HOLD_OUT_ERRPT - { - name "EXP.EC.SD.ISU_REG8_HOLD_OUT"; - scomaddr 0x10013348; - capture group default; - capture group CerrRegs; - }; - - register ISU_REG9_ISU_HOLD_OUT - { - name "EXP.EC.SD.ISU_REG9_HOLD_OUT"; - scomaddr 0x10013349; - capture group default; - capture group CerrRegs; - }; - - register IFU_REG0_HOLD_OUT - { - name "EXP.EC.IFU.IFU_REG0_HOLD_OUT"; - scomaddr 0x10013381; - capture group default; - capture group CerrRegs; - }; - - register IFU_REG1_HOLD_OUT - { - name "EXP.EC.IFU.IFU_REG1_HOLD_OUT"; - scomaddr 0x10013382; - capture group default; - capture group CerrRegs; - }; - - register IFU_REG2_HOLD_OUT - { - name "EXP.EC.IFU.IFU_REG2_HOLD_OUT"; - scomaddr 0x10013383; - capture group default; - capture group CerrRegs; - }; - - register IFU_REG3_HOLD_OUT - { - name "EXP.EC.IFU.IFU_REG3_HOLD_OUT"; - scomaddr 0x10013384; - capture group default; - capture group CerrRegs; - }; - - register IFU_REG4_HOLD_OUT - { - name "EXP.EC.IFU.IFU_REG4_HOLD_OUT"; - scomaddr 0x10013385; - capture group default; - capture group CerrRegs; - }; - - register LSU_REG0_HOLD_OUT - { - name "EXP.EC.LS.LSU_REG0_HOLD_OUT"; - scomaddr 0x100133C0; - capture group default; - capture group CerrRegs; - }; - - register LSU_REG1_HOLD_OUT - { - name "EXP.EC.LS.LSU_REG1_HOLD_OUT"; - scomaddr 0x100133C1; - capture group default; - capture group CerrRegs; - }; - - register LSU_REG2_HOLD_OUT - { - name "EXP.EC.LS.LSU_REG2_HOLD_OUT"; - scomaddr 0x100133C2; - capture group default; - capture group CerrRegs; - }; - - register LSU_REG3_HOLD_OUT - { - name "EXP.EC.LS.LSU_REG3_HOLD_OUT"; - scomaddr 0x100133C3; - capture group default; - capture group CerrRegs; - }; - - register LSU_REG4_HOLD_OUT - { - name "EXP.EC.LS.LSU_REG4_HOLD_OUT"; - scomaddr 0x100133C4; - capture group default; - capture group CerrRegs; - }; - - register LSU_REG5_HOLD_OUT - { - name "EXP.EC.LS.LSU_REG5_HOLD_OUT"; - scomaddr 0x100133C5; - capture group default; - capture group CerrRegs; - }; - - register LSU_REG6_HOLD_OUT - { - name "EXP.EC.LS.LSU_REG6_HOLD_OUT"; - scomaddr 0x100133C6; - capture group default; - capture group CerrRegs; - }; - - register LSU_REG7_HOLD_OUT - { - name "EXP.EC.LS.LSU_REG7_HOLD_OUT"; - scomaddr 0x100133C7; - capture group default; - capture group CerrRegs; - }; - - register LSU_REG8_HOLD_OUT - { - name "EXP.EC.LS.LSU_REG8_HOLD_OUT"; - scomaddr 0x100133C8; - capture group default; - capture group CerrRegs; - }; - - register LSU_REG9_HOLD_OUT - { - name "EXP.EC.LS.LSU_REG9_HOLD_OUT"; - scomaddr 0x100133C9; - capture group default; - capture group CerrRegs; - }; - - register LSU_REG10_HOLD_OUT - { - name "EXP.EC.LS.LSU_REG10_HOLD_OUT"; - scomaddr 0x100133CA; - capture group default; - capture group CerrRegs; - }; - - register LSU_REG11_HOLD_OUT - { - name "EXP.EC.LS.LSU_REG11_HOLD_OUT"; - scomaddr 0x100133CB; - capture group default; - capture group CerrRegs; - }; - - register LSU_REG12_HOLD_OUT - { - name "EXP.EC.LS.LSU_REG12_HOLD_OUT"; - scomaddr 0x100133CC; - capture group default; - capture group CerrRegs; - }; - - register LSU_REG13_HOLD_OUT - { - name "EXP.EC.LS.LSU_REG13_HOLD_OUT"; - scomaddr 0x100133CD; - capture group default; - capture group CerrRegs; - }; - - register LSU_REG14_HOLD_OUT - { - name "EXP.EC.LS.LSU_REG14_HOLD_OUT"; - scomaddr 0x100133CE; - capture group default; - capture group CerrRegs; - }; - - register LSU_REG15_HOLD_OUT - { - name "EXP.EC.LS.LSU_REG15_HOLD_OUT"; - scomaddr 0x100133CF; - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # EX Chiplet L2FIR - ############################################################################ - - register L2FIR - { - name "EX00.L2.L2MISC.L2CERRS.FIR_REG"; - scomaddr 0x10012800; - reset (&, 0x10012801); - mask (|, 0x10012805); - capture group default; - }; - - register L2FIR_MASK - { - name "EX00.L2.L2MISC.L2CERRS.FIR_MASK_REG"; - scomaddr 0x10012803; - capture group default; - }; - - register L2FIR_ACT0 - { - name "EX00.L2.L2MISC.L2CERRS.FIR_ACTION0_REG"; - scomaddr 0x10012806; - capture type secondary; - capture group default; - capture req nonzero("L2FIR"); - }; - - register L2FIR_ACT1 - { - name "EX00.L2.L2MISC.L2CERRS.FIR_ACTION1_REG"; - scomaddr 0x10012807; - capture type secondary; - capture group default; - capture req nonzero("L2FIR"); - }; - - register L2FIR_ERROR_REPORT_0 - { - name "EXP.L2.L2MISC.L2CERRS.ERR_RPT0"; - scomaddr 0x10012815; - capture group default; - capture group CerrRegs; - }; - - register L2FIR_ERROR_REPORT_1 - { - name "EXP.L2.L2MISC.L2CERRS.ERR_RPT1"; - scomaddr 0x10012816; - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # EX Chiplet L3FIR - ############################################################################ - - register L3FIR - { - name "EX00.L3.L3_MISC.L3CERRS.FIR_REG"; - scomaddr 0x10010800; - reset (&, 0x10010801); - mask (|, 0x10010805); - capture group default; - }; - - register L3FIR_MASK - { - name "EX00.L3.L3_MISC.L3CERRS.FIR_MASK_REG"; - scomaddr 0x10010803; - capture group default; - }; - - register L3FIR_ACT0 - { - name "EX00.L3.L3_MISC.L3CERRS.FIR_ACTION0_REG"; - scomaddr 0x10010806; - capture type secondary; - capture group default; - capture req nonzero("L3FIR"); - }; - - register L3FIR_ACT1 - { - name "EX00.L3.L3_MISC.L3CERRS.FIR_ACTION1_REG"; - scomaddr 0x10010807; - capture type secondary; - capture group default; - capture req nonzero("L3FIR"); - }; - - register L3FIR_RD0_ERROR_REPORT - { - name "EXP.L3.L3_MISC.L3CERRS.L3_CTL_CHECK_RD0_REG"; - scomaddr 0x10010810; - capture group default; - capture group CerrRegs; - }; - - register L3FIR_RD1_ERROR_REPORT - { - name "EXP.L3.L3_MISC.L3CERRS.L3_CTL_CHECK_RD1_REG"; - scomaddr 0x10010817; - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # EX Chiplet NCUFIR - ############################################################################ - - register NCUFIR - { - name "EX00.NC.NCMISC.NCSCOMS.FIR_REG"; - scomaddr 0x10010c00; - reset (&, 0x10010c01); - mask (|, 0x10010c05); - capture group default; - }; - - register NCUFIR_MASK - { - name "EX00.NC.NCMISC.NCSCOMS.FIR_MASK_REG"; - scomaddr 0x10010c03; - capture group default; - }; - - register NCUFIR_ACT0 - { - name "EX00.NC.NCMISC.NCSCOMS.FIR_ACTION0_REG"; - scomaddr 0x10010c06; - capture type secondary; - capture group default; - capture req nonzero("NCUFIR"); - }; - - register NCUFIR_ACT1 - { - name "EX00.NC.NCMISC.NCSCOMS.FIR_ACTION1_REG"; - scomaddr 0x10010c07; - capture type secondary; - capture group default; - capture req nonzero("NCUFIR"); - }; - - register NCUFIR_ERROR_REPORT - { - name "EXP.NC.NCMISC.NCSCOMS.ERR_RPT_REG"; - scomaddr 0x10010C0C; - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # EX Chiplet SPATTNs - ############################################################################ - - # EX special attention registers - Used for FFDC only - # Currently, all analysis of these registers is done by ATTN. - - register SPATTN_0 - { - name "EX00.EC.PC.PC_NE.TCTL0.SPATTN"; - scomaddr 0x10013007; - capture group default; - capture group CerrRegs; - }; - - register SPATTN_1 - { - name "EX00.EC.PC.PC_NE.TCTL1.SPATTN"; - scomaddr 0x10013017; - capture group default; - capture group CerrRegs; - }; - - register SPATTN_2 - { - name "EX00.EC.PC.PC_NE.TCTL2.SPATTN"; - scomaddr 0x10013027; - capture group default; - capture group CerrRegs; - }; - register SPATTN_3 - { - name "EX00.EC.PC.PC_NE.TCTL3.SPATTN"; - scomaddr 0x10013037; - capture group default; - capture group CerrRegs; - }; - - register SPATTN_4 - { - name "EX00.EC.PC.PC_NE.TCTL4.SPATTN"; - scomaddr 0x10013047; - capture group default; - capture group CerrRegs; - }; - - register SPATTN_5 - { - name "EX00.EC.PC.PC_NE.TCTL5.SPATTN"; - scomaddr 0x10013057; - capture group default; - capture group CerrRegs; - }; - - register SPATTN_6 - { - name "EX00.EC.PC.PC_NE.TCTL6.SPATTN"; - scomaddr 0x10013067; - capture group default; - capture group CerrRegs; - }; - - register SPATTN_7 - { - name "EX00.EC.PC.PC_NE.TCTL7.SPATTN"; - scomaddr 0x10013077; - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # EX Chiplet Other Registers - ############################################################################ - - register COREHMEER - { - name "Core HMEER"; - scomaddr 0x1001329B; - capture type secondary; - capture group default; - }; - - ############################################################################ - # EX non-existent registers for capture - ############################################################################ - register L2TRACE_ARRAY - { - name "Capture Data for L2 Trace Array"; - capture group never; - }; - - register L3TRACE_ARRAY - { - name "Capture Data for L3 Trace Array"; - capture group never; - }; - - ############################################################################ - # EX Chiplet PLL Registers - ############################################################################ - - register EX_ERROR_REG - { - name "EH.TPCHIP.NET.PCBSLEX.TP_PCB_SLAVE_INST.ERROR_REG"; - scomaddr 0x100F001F; - capture group PllFIRs; - }; - - register EX_CONFIG_REG - { - name "EH.TPCHIP.NET.PCBSLEX.TP_PCB_SLAVE_INST.SLAVE_CONFIG_REG"; - scomaddr 0x100F001E; - capture group PllFIRs; - }; - - ############################################################################ - # Core registers for FFDC - ############################################################################ - - register EX_FREQ_CTRL_REG - { - name "EX.TP_PCB_SLAVE_PM_INST.FREQ_CTRL_REG"; - scomaddr 0x100F0151; - capture group default; - access read_only; - }; - - register EX_DPLL_STATUS_REG - { - name "EX.TP_PCB_SLAVE_PM_INST.PCBS_DPLL_STAT_REG"; - scomaddr 0x100F0161; - capture group default; - access read_only; - }; - - register EX_POWER_MGMT_STATUS_REG - { - name "EX.TP_PCB_SLAVE_PM_INST.PCBS_PWR_MGMT_STAT_REG"; - scomaddr 0x100F0153; - capture group default; - access read_only; - }; - - register EX_POWER_MGMT_CTRL_REG - { - name "EX.TP_PCB_SLAVE_PM_INST.PCBS_PWR_MGMT_CTRL_REG"; - scomaddr 0x100F0159; - capture group default; - access read_only; - }; - -}; - - ############################################################################## - # # - # #### # # - # # # # # # ##### ### # # # ## ##### ### ### # # ### # - # # # # # # # # # # # # # # # # # ## # # # - # #### # # # #### ### # ####### # # # # # # # # ### # - # # # # # # # # # # # # # # # # # # ## # # - # # # ### #### ##### ### # # # ## # ### ### # # ### # - # # - ############################################################################## - -################################################################################ -# EX Chiplet Registers -################################################################################ - -rule ExChipletFir -{ - CHECK_STOP: - EX_CHIPLET_CS_FIR & `1F00000000000000`; - RECOVERABLE: - (EX_CHIPLET_RE_FIR >> 2) & `3F00000000000000`; -}; - -group gExChipletFir attntype CHECK_STOP, RECOVERABLE filter priority(3,5,6,7,4,2) -{ - /** EX_CHIPLET_FIR[2] - * Unit Checkstop from Core Local FIR (bit0 in RER) - */ - (ExChipletFir, bit(2))? analyzeCoreUnitCheckstop; - - /** EX_CHIPLET_FIR[3] - * Attention from LFIR - */ - (ExChipletFir, bit(3))? analyzeExLFir; - - /** EX_CHIPLET_FIR[4] - * Attention from COREFIR - */ - (ExChipletFir, bit(4)) ? analyzeCore; - - /** EX_CHIPLET_FIR[5] - * Attention from L2FIR - */ - (ExChipletFir, bit(5)) ? analyzeL2Fir; - - /** EX_CHIPLET_FIR[6] - * Attention from L3FIR - */ - (ExChipletFir, bit(6)) ? analyzeL3Fir; - - /** EX_CHIPLET_FIR[7] - * Attention from NCUFIR - */ - (ExChipletFir, bit(7)) ? analyzeNcuFir; -}; - -################################################################################ -# EX Chiplet LFIR -################################################################################ - -rule ExLFir -{ - CHECK_STOP: EX_LFIR & ~EX_LFIR_MASK & ~EX_LFIR_ACT0 & ~EX_LFIR_ACT1; - RECOVERABLE: EX_LFIR & ~EX_LFIR_MASK & ~EX_LFIR_ACT0 & EX_LFIR_ACT1; -}; - -group gExLFir filter singlebit -{ - /** EX_LFIR[0] - * CFIR internal parity error - */ - (ExLFir, bit(0)) ? calloutParentChipHighThr32; - - /** EX_LFIR[1] - * Local errors from GPIO (PCB error) - */ - (ExLFir, bit(1)) ? defaultMaskedError; - - /** EX_LFIR[2] - * Local errors from CC (PCB error) - */ - (ExLFir, bit(2)) ? defaultMaskedError; - - /** EX_LFIR[3] - * Local errors from CC (OPCG, parity, scan collision, ...) - */ - (ExLFir, bit(3)) ? defaultMaskedError; - - /** EX_LFIR[4] - * Local errors from PSC (PCB error) - */ - (ExLFir, bit(4)) ? defaultMaskedError; - - /** EX_LFIR[5] - * Local errors from PSC (parity error) - */ - (ExLFir, bit(5)) ? defaultMaskedError; - - /** EX_LFIR[6] - * Local errors from Thermal (parity error) - */ - (ExLFir, bit(6)) ? defaultMaskedError; - - /** EX_LFIR[7] - * Local errors from Thermal (PCB error) - */ - (ExLFir, bit(7)) ? defaultMaskedError; - - /** EX_LFIR[8|9] - * Local errors from Thermal (Trip error) - */ - (ExLFir, bit(8|9)) ? defaultMaskedError; - - /** EX_LFIR[10] - * Local errors from trace array - error - */ - (ExLFir, bit(10)) ? calloutParentChipHighThr32; - - /** EX_LFIR[11] - * Local errors from Trace Array ( error) - */ - (ExLFir, bit(11)) ? defaultMaskedError; - - /** EX_LFIR[12|13] - * Local errors from trial - */ - (ExLFir, bit(12|13)) ? defaultMaskedError; - - /** EX_LFIR[14] - * Local errors from OHA - recov error - */ - (ExLFir, bit(14)) ? defaultMaskedError; - - /** EX_LFIR[15] - * Local errors from OHA - checkstop - */ - (ExLFir, bit(15)) ? defaultMaskedError; - - /** EX_LFIR[16] - * Local errors from skewadj - */ - (ExLFir, bit(16)) ? calloutParentChipHighThr32; - - /** EX_LFIR[17] - * local errors from dcadj - */ - (ExLFir, bit(17)) ? calloutParentChipHighThr32; - - /** EX_LFIR[18:39] - * Unused local errors - */ - (ExLFir, bit( 18|19|20|21|22|23|24|25|26|27|28|29| - 30|31|32|33|34|35|36|37|38|39 )) ? defaultMaskedError; - - /** EX_LFIR[40] - * Malfunction alert - local checkstop in another chiplet - */ - (ExLFir, bit(40)) ? defaultMaskedError; -}; - -################################################################################ -# EX Chiplet COREFIR -################################################################################ - -rule CoreFir -{ - CHECK_STOP: COREFIR & ~COREFIR_MASK & COREFIR_ACT0 & ~COREFIR_ACT1; - PROC_CS: COREFIR & ~COREFIR_MASK & COREFIR_ACT0 & COREFIR_ACT1; - RECOVERABLE: COREFIRWOF & ~COREFIR_MASK & ~COREFIR_ACT0 & COREFIR_ACT1; -}; - -group gCoreFir filter singlebit, - secondarybits( 33, 34, 35 ) -{ - /** COREFIR[0] - * IFU_SRAM_PARITY_ERR: SRAM recoverable error (ICACHE parity error, etc.) - */ - (CoreFir, bit(0)) ? calloutExThr5pHr; - - /** COREFIR[1] - * IF_SETDELETE_ERR: set deleted - */ - (CoreFir, bit(1)) ? SelfHighThr1; - - /** COREFIR[2] - * IF_RFILE_REC_ERR: RegFile recoverable error - */ - (CoreFir, bit(2)) ? calloutExThr5pHr; - - /** COREFIR[3] - * IF_RFILE_CHKSTOP_ERR: RegFile core check stop - */ - (CoreFir, bit(3)) ? SelfHighThr1; - - /** COREFIR[4] - * IF_LOG_REC_ERR: logic recoverable error - */ - (CoreFir, bit(4)) ? calloutExThr5pHr; - - /** COREFIR[5] - * IF_LOG_CHKSTOP_ERR: logic core check stop - */ - (CoreFir, bit(5)) ? SelfHighThr1; - - /** COREFIR[6] - * IF_NOT_MT_REC_ERR: recoverable if not in MT window - */ - (CoreFir, bit(6)) ? calloutExThr32pDay; - - /** COREFIR[7] - * IF_CHKSTOP_ERR: system check stop - */ - (CoreFir, bit(7)) ? SelfHighThr1; - - /** COREFIR[8] - * RECOV_FIR_CHKSTOP_ERR: recovery core check stop - */ - (CoreFir, bit(8)) ? SelfHighThr1; - - /** COREFIR[9] - * SD_RFILE_REC_ERR: RegFile recoverable error - */ - (CoreFir, bit(9)) ? calloutExThr5pHr; - - /** COREFIR[10] - * SD_RFILE_CHKSTOP_ERR: RegFile core check stop (mapper error) - */ - (CoreFir, bit(10)) ? SelfHighThr1; - - /** COREFIR[11] - * SD_LOG_REC_ERR: logic recoverable error - */ - (CoreFir, bit(11)) ? calloutExThr5pHr; - - /** COREFIR[12] - * SD_LOG_CHKSTOP_ERR: logic core check stop - */ - (CoreFir, bit(12)) ? SelfHighThr1; - - /** COREFIR[13] - * SD_NOT_MT_REC_ERR: recoverable if not in MT window - */ - (CoreFir, bit(13)) ? calloutExThr32pDay; - - /** COREFIR[14] - * SD_MCHK_AND_ME_EQ_0: MCHK received while ME=0 non recoverable - */ - # FIXME: RTC 85697: Make sure this is SUE-CS bit - (CoreFir, bit(14)) ? calloutSelfHighSUE; - - /** COREFIR[15] - * SD_PC_L2_UE_ERR: UE from L2 - */ - (CoreFir, bit(15)) ? defaultMaskedError; - - /** COREFIR[16] - * ISU_L2_UE_OVER_TH_ERR: Number of UEs from L2 above threshold - */ - (CoreFir, bit(16)) ? defaultMaskedError; - - /** COREFIR[17] - * SD_PC_CI_UE: UE on CI load - */ - (CoreFir, bit(17)) ? defaultMaskedError; - - /** COREFIR[18] - * UNUSED_2 - */ - (CoreFir, bit(18)) ? defaultMaskedError; - - /** COREFIR[19] - * FX_GPR_REC_ERR: GPR recoverable error - */ - (CoreFir, bit(19)) ? calloutExThr5pHr; - - /** COREFIR[20] - * HV Corruption - */ - (CoreFir, bit(20)) ? SelfHighThr1; - - /** COREFIR[21] - * FX_LOG_CHKSTOP_ERR: logic core check stop - */ - (CoreFir, bit(21)) ? SelfHighThr1; - - /** COREFIR[22] - * FX_NOT_MT_REC_ERR: recoverable if not in MT window - */ - (CoreFir, bit(22)) ? calloutExThr32pDay; - - /** COREFIR[23] - * VS_VRF_REC_ERR: VRF recoverable error - */ - (CoreFir, bit(23)) ? calloutExThr5pHr; - - /** COREFIR[24] - * VS_LOG_REC_ERR: logic recoverable error - */ - (CoreFir, bit(24)) ? calloutExThr5pHr; - - /** COREFIR[25] - * VS_LOG_CHKSTOP_ERR: logic core check stop - */ - (CoreFir, bit(25)) ? SelfHighThr1; - - /** COREFIR[26] - * RECOV_IN_MAINT_ERR: 26 = recov_in_maint - */ - (CoreFir, bit(26)) ? callout2ndLvlMedThr1; - - /** COREFIR[27] - * DU_LOG_REC_ERR: logic recoverable error - */ - (CoreFir, bit(27)) ? calloutExThr5pHr; - - /** COREFIR[28] - * DU_LOG_CHKSTOP_ERR: logic core check stop - */ - (CoreFir, bit(28)) ? SelfHighThr1; - - /** COREFIR[29] - * LSU_SRAM_PARITY_ERR: SRAM recoverable error (DCACHE parity error, etc.) - */ - (CoreFir, bit(29)) ? calloutExThr5pHr; - - /** COREFIR[30] - * LS_SETDELETE_ERR: set deleted - */ - (CoreFir, bit(30)) ? SelfHighThr1; - - /** COREFIR[31] - * LS_RFILE_REC_ERR: RegFile recoverable error - */ - (CoreFir, bit(31)) ? calloutExThr5pHr; - - /** COREFIR[32] - * LS_RFILE_CHKSTOP_ERR: RegFile core check stop - */ - (CoreFir, bit(32)) ? SelfHighThr1; - - /** COREFIR[33] - * LS_TLB_MULTIHIT_ERR: special recovery error TLB multi hit error occurred - */ - (CoreFir, bit(33)) ? thresholdAndMask_self; - - /** COREFIR[34] - * LS_SLB_MULTIHIT_ERR: special recovery error SLBFEE multi hit - * error occurred - */ - (CoreFir, bit(34)) ? thresholdAndMask_self; - - /** COREFIR[35] - * LS_DERAT_MULTIHIT_ERR: special recovery error ERAT multi hit error - * occurred - */ - (CoreFir, bit(35)) ? thresholdAndMask_self; - - /** COREFIR[36] - * FORWARD_PROGRESS_ERR: forward progress error - */ - (CoreFir, bit(36)) ? SelfHighThr1; - - /** COREFIR[37] - * LS_LOG_REC_ERR: logic recoverable error - */ - (CoreFir, bit(37)) ? calloutExThr5pHr; - - /** COREFIR[38] - * LS_LOG_CHKSTOP_ERR: logic core check stop - */ - (CoreFir, bit(38)) ? SelfHighThr1; - - /** COREFIR[39] - * LS_NOT_MT_REC_ERR: recoverable if not in MT window - */ - (CoreFir, bit(39)) ? calloutExThr32pDay; - - /** COREFIR[40] - * LS_NOT_CI_REC_ERR: recoverable if not in CI window - */ - (CoreFir, bit(40)) ? calloutExThr32pDay; - - /** COREFIR[41] - * LS_CHKSTOP_ERR: system check stop - */ - (CoreFir, bit(41)) ? SelfHighThr1; - - /** COREFIR[42] - * LS_GPR_RCV_CHKSTOP_ERR: UE from GPR/VRF recovery process - */ - (CoreFir, bit(42)) ? defaultMaskedError; - - /** COREFIR[43] - * THREAD_HANG_REC_ERR: thread hang recoverable error - */ - (CoreFir, bit(43)) ? SelfAndLevel2MedThr5PerHrNoGard; - - /** COREFIR[44] - * FIR_LOG_RECOV_ERR: logic recoverable error - */ - (CoreFir, bit(44)) ? calloutExThr5pHr; - - /** COREFIR[45] - * PC_LOG_CHKSTOP_ERR: PC logic core check stop - */ - (CoreFir, bit(45)) ? SelfHighThr1; - - /** COREFIR[46] - * RESERVED - */ - (CoreFir, bit(46)) ? defaultMaskedError; - - /** COREFIR[47] - * TFC_FIR_TFMR_P_ERR: TFMR Parity Error (timing facility may be corrupt) - */ - (CoreFir, bit(47)) ? defaultMaskedError; - - /** COREFIR[48] - * SPRD_FIR_HYP_RES_P_ERR: Hypervisor Resource error - core check stop - */ - (CoreFir, bit(48)) ? SelfHighThr1; - - /** COREFIR[49] - * TFC_FIR_P_ERR: TFAC parity error - */ - (CoreFir, bit(49)) ? defaultMaskedError; - - /** COREFIR[50] - * TFC_FIR_CONTROL_ERR: TFAC control error - */ - (CoreFir, bit(50)) ? defaultMaskedError; - - /** COREFIR[51] - * PC_FIRM_AND_SEL_ERR: TFAC firmware error and select error - */ - (CoreFir, bit(51)) ? defaultMaskedError; - - /** COREFIR[52] - * CORE_HUNG: Hang recovery failed (core check stop) - */ - (CoreFir, bit(52)) ? SelfHighThr1; - - /** COREFIR[53] - * CORE_HANG_DETECT: Internal hang detected (core hang) - */ - (CoreFir, bit(53)) ? defaultMaskedError; - - /** COREFIR[54] - * AMBI_HANG_DETECT: Hang detected unknown source - */ - (CoreFir, bit(54)) ? calloutLevel2MedExLowThr1; - - /** COREFIR[55] - * NEST_HANG_DETECT: External Hang detected - */ - (CoreFir, bit(55)) ? nestHangDetect; - - /** COREFIR[56|57|58] - * RESERVED - */ - (CoreFir, bit(56|57|58)) ? defaultMaskedError; - - /** COREFIR[59] - * PC_SOM_ERR: SCOM satellite error detected - */ - (CoreFir, bit(59)) ? defaultMaskedError; - - /** COREFIR[60] - * Debug trigger error inject - */ - (CoreFir, bit(60)) ? SelfMedThr32PerDay; - - /** COREFIR[61] - * SP_INJ_REC_ERR: SCOM or Firmware recoverable Error Inject - */ - (CoreFir, bit(61)) ? defaultMaskedError; - - /** COREFIR[62] - * SP_INJ_XSTOP_ERR: Firmware Xstop Error Inject - */ - (CoreFir, bit(62)) ? defaultMaskedError; - - /** COREFIR[63] - * SPRD_PHYP_ERR_INJ: Phyp Xstop via SPRC / SPRD - */ - (CoreFir, bit(63)) ? calloutProcLow2ndLvlMedThr1; -}; - -################################################################################ -# EX Chiplet L2FIR -################################################################################ - -rule L2Fir -{ - CHECK_STOP: L2FIR & ~L2FIR_MASK & ~L2FIR_ACT0 & ~L2FIR_ACT1; - RECOVERABLE: L2FIR & ~L2FIR_MASK & ~L2FIR_ACT0 & L2FIR_ACT1; -}; - -group gL2Fir filter singlebit, - secondarybits( 0, 6 ) -{ - /** L2FIR[0] - * CACHE_RD_CE - */ - (L2Fir, bit(0)) ? L2CE; - - /** L2FIR[1] - * CACHE_RD_UE - */ - (L2Fir, bit(1)) ? L2UE; - - /** L2FIR[2] - * CACHE_RD_SUE - */ - (L2Fir, bit(2)) ? defaultMaskedError; - - /** L2FIR[3] - * HW_DIR_INTIATED_LINE_DELETE_OCCURRED - */ - (L2Fir, bit(3)) ? defaultMaskedError; - - /** L2FIR[4] - * CACHE_UE_SUE_DETECTED_ON_MODIFIED_LINE_BY_CO - */ - (L2Fir, bit(4)) ? defaultMaskedError; - - /** L2FIR[5] - * CACHE_UE_SUE_DETECTED_ON_NON_MODIFIED_LINE_BY_CO - */ - (L2Fir, bit(5)) ? defaultMaskedError; - - /** L2FIR[6] - * DIR_CE_DETECTED - */ - (L2Fir, bit(6)) ? L2DirCE; - - /** L2FIR[7] - * DIR_UE_DETECTED - */ - (L2Fir, bit(7)) ? SelfHighThr1; - - /** L2FIR[8] - * DIR_STUCK_BIT_CE - */ - (L2Fir, bit(8)) ? SelfHighThr1; - - /** L2FIR[9] - * DIR_SBCE_REPAIR_FAILED - */ - (L2Fir, bit(9)) ? SelfHighThr1; - - /** L2FIR[10] - * MULTIPLE_DIR_ERRORS_DETECTED - */ - (L2Fir, bit(10)) ? defaultMaskedError; - - /** L2FIR[11] - * LRU_READ_ERROR_DETECTED - */ - (L2Fir, bit(11)) ? SelfHighThr32PerDay; - - /** L2FIR[12] - * RC_POWERBUS_DATA_TIMEOUT - */ - (L2Fir, bit(12)) ? callout2ndLvlMedThr1; - - /** L2FIR[13] - * NCU_POWERBUS_DATA_TIMEOUT - */ - (L2Fir, bit(13)) ? callout2ndLvlMedThr1; - - /** L2FIR[14] - * HW_CONTROL_ERROR - */ - (L2Fir, bit(14)) ? L2ChipLevel2; - - /** L2FIR[15] - * LRU_ALL_MEMBERS_IN_CGC_ARE_LINE_DELETED - */ - (L2Fir, bit(15)) ? SelfHighThr1; - - /** L2FIR[16] - * CACHE_INHIBITED_HIT_CACHEABLE_ERROR - */ - (L2Fir, bit(16)) ? SelfHighThr1; - - /** L2FIR[17] - * RC_LOAD_RECIVED_PB_CRESP_ADR_ERR - */ - (L2Fir, bit(17)) ? SelfHighThr1UE; - - /** L2FIR[18] - * RC_STORE_RECIVED_PB_CRESP_ADR_ERR - */ - (L2Fir, bit(18)) ? SelfHighThr1; - - /** L2FIR[19] - * RC_POWBUS_DATA_CE_ERR_FROM_F2CHK - */ - (L2Fir, bit(19)) ? SelfHighThr32PerDay; - - /** L2FIR[20] - * RC_POWBUS_DATA_UE_ERR_FROM_F2CHK - */ - (L2Fir, bit(20)) ? SelfHighThr1UE; - - /** L2FIR[21] - * RC_POWBUS_DATA_SUE_ERR_FROM_F2CHK - */ - (L2Fir, bit(21)) ? defaultMaskedError; - - /** L2FIR[22] - * CO_ICSW_UE_SUE_DATA_ERR_FROM_F2CHK - */ - (L2Fir, bit(22)) ? SelfHighThr1; - - /** L2FIR[23] - * RC_LOAD_RECIVED_PB_CRESP_ADR_ERR_FOR_HYP - */ - (L2Fir, bit(23)) ? defaultMaskedError; - - /** L2FIR[24] - * RCDAT_RD_PARITY_ERR - */ - (L2Fir, bit(24)) ? SelfHighThr1UE; - - /** L2FIR[25] - * CO_ICSW_RTY_BUSY_ABT_ERR - */ - (L2Fir, bit(25)) ? defaultMaskedError; - - /** L2FIR[26] - * HA_LOG_STOP_SW_ERR - */ - (L2Fir, bit(26)) ? defaultMaskedError; - - /** L2FIR[27] - * RC_LOAD_RECEIVED_PB_ACK_DEAD_FROM_FOREIGN0 - */ - (L2Fir, bit(27)) ? defaultMaskedError; - - /** L2FIR[28] - * RC_LOAD_RECEIVED_PB_ACK_DEAD_FROM_FOREIGN1 - */ - (L2Fir, bit(28)) ? defaultMaskedError; - - /** L2FIR[29] - * RC_STORE_RECEIVED_PB_ACK_DEAD_FROM_FOREIGN0 - */ - (L2Fir, bit(29)) ? defaultMaskedError; - - /** L2FIR[30] - * RC_STORE_RECEIVED_PB_ACK_DEAD_FROM_FOREIGN1 - */ - (L2Fir, bit(30)) ? defaultMaskedError; - - /** L2FIR[31] - * ILLEGAL_MPALOG_TPID_SW_ERR - */ - (L2Fir, bit(31)) ? defaultMaskedError; - - /** L2FIR[32] - * UNEXP_HA_ST_ERR - */ - (L2Fir, bit(32)) ? defaultMaskedError; - - /** L2FIR[33] - * HA_LINE_IN_CONS_CACHE_ERR - */ - (L2Fir, bit(33)) ? defaultMaskedError; - - /** L2FIR[34] - * HA_TABLE_IN_PROD_CACHE_ERR - */ - (L2Fir, bit(34)) ? defaultMaskedError; - - /** L2FIR[35] - * ILLEGAL_LOG_STOP_SW_ERR - */ - (L2Fir, bit(35)) ? defaultMaskedError; - - /** L2FIR[48] - * SCOM_ERR1: scom error - */ - (L2Fir, bit(48)) ? defaultMaskedError; - - /** L2FIR[49] - * SCOM_ERR2: scom error - */ - (L2Fir, bit(49)) ? defaultMaskedError; -}; - -################################################################################ -# EX Chiplet L3FIR -################################################################################ - -rule L3Fir -{ - CHECK_STOP: L3FIR & ~L3FIR_MASK & ~L3FIR_ACT0 & ~L3FIR_ACT1; - RECOVERABLE: L3FIR & ~L3FIR_MASK & ~L3FIR_ACT0 & L3FIR_ACT1; -}; - -group gL3Fir filter singlebit, - secondarybits( 4, 13 ) -{ - /** L3FIR[0] - * PowerBus Command Error - Overrun condition. - */ - (L3Fir, bit(0)) ? calloutExLowSecLvlThr1MedDumpSh; - - /** L3FIR[1] - * PowerBus Data Error - Overrun condition. - */ - (L3Fir, bit(1)) ? calloutExLowSecLvlThr1MedDumpSh; - - /** L3FIR[2] - * Spare - */ - (L3Fir, bit(2)) ? defaultMaskedError; - - /** L3FIR[3] - * Spare - */ - (L3Fir, bit(3)) ? defaultMaskedError; - - /** L3FIR[4] - * L3 Cache CE - */ - (L3Fir, bit(4)) ? L3CE; - - /** L3FIR[5] - * L3 Cache UE. - */ - (L3Fir, bit(5)) ? L3UE; - - /** L3FIR[4,5] - * L3 Cache UE with CE. - */ - (L3Fir, bit(4,5)) ? L3UE; - - /** L3FIR[6] - * L3 Cache SUE. - */ - (L3Fir, bit(6)) ? defaultMaskedError; - - /** L3FIR[7] - * L3 Cache Write CE from PowerBus - */ - (L3Fir, bit(7)) ? SelfMedThr32PerDay; - - /** L3FIR[8] - * L3 Cache Write UE from PowerBus - */ - (L3Fir, bit(8)) ? SelfHighThr1UE; - - /** L3FIR[9] - * L3 Cache Write SUE from PowerBus - */ - (L3Fir, bit(9)) ? defaultMaskedError; - - /** L3FIR[10] - * L3 Cache Write CE from L2 - */ - (L3Fir, bit(10)) ? SelfHighThr32PerDay; - - /** L3FIR[11] - * L3 Cache Write UE from L2 - */ - (L3Fir, bit(11)) ? L3UE; - - /** L3FIR[12] - * L3 Cache Write SUE from L2 - */ - (L3Fir, bit(12)) ? defaultMaskedError; - - /** L3FIR[13] - * L3 Dir Read CE - */ - (L3Fir, bit(13)) ? L3DirCE; - - /** L3FIR[14] - * L3 Dir Read UE - */ - (L3Fir, bit(14)) ? SelfHighThr1UE; - - /** L3FIR[15] - * L3 Dir Read \"Phantom Error\" - */ - (L3Fir, bit(15)) ? defaultMaskedError; - - /** L3FIR[16] - * L3 Store Address Error - */ - (L3Fir, bit(16)) ? calloutExLowSecLvlThr1MedDumpSh; - - /** L3FIR[17] - * L3 Load Address Error (from Prefetch Machine) - */ - (L3Fir, bit(17)) ? SelfHighThr1; - - /** L3FIR[18] - * L3 Address Hang - */ - (L3Fir, bit(18)) ? defaultMaskedError; - - /** L3FIR[19] - * Reserved field (Access type is l3_flink_0_load_ack_dead) - */ - (L3Fir, bit(19)) ? defaultMaskedError; - - /** L3FIR[20] - * Reserved field (Access type is l3_flink_0_store_ack_dead) - */ - (L3Fir, bit(20)) ? defaultMaskedError; - - /** L3FIR[21] - * Reserved field (Access type is l3_flink_1_load_ack_dead) - */ - (L3Fir, bit(21)) ? defaultMaskedError; - - /** L3FIR[22] - * Reserved field (Access type is l3_flink_1_store_ack_dead) - */ - (L3Fir, bit(22)) ? defaultMaskedError; - - /** L3FIR[23] - * L3 Machine Hang - */ - (L3Fir, bit(23)) ? calloutExLowSecLvlThr1MedDumpSh; - - /** L3FIR[24] - * L3 Hw Control Error - */ - (L3Fir, bit(24)) ? SelfHighThr1; - - /** L3FIR[25] - * L3 Snoop Sw error detected - */ - (L3Fir, bit(25)) ? calloutExLowSecLvlThr1MedDumpSh; - - /** L3FIR[26] - * L3 Line Delete CE done - */ - (L3Fir, bit(26)) ? defaultMaskedError; - - /** L3FIR[27] - * L3 DRAM Logic Error - */ - (L3Fir, bit(27)) ? SelfHighThr1; - - /** L3FIR[28] - * L3 LRU SRAM Logic Recoverable Error - */ - (L3Fir, bit(28)) ? SelfHighThr32PerDay; - - /** L3FIR[29] - * L3 Cache Congruence Class Deleted - */ - (L3Fir, bit(29)) ? SelfHighThr1; - - /** L3FIR[30] - * L3 Cache Timer Refresh Error - */ - (L3Fir, bit(30)) ? SelfHighThr1; - - /** L3FIR[31] - * L3 HA Consumer SW Access Error - */ - (L3Fir, bit(31)) ? defaultMaskedError; - - /** L3FIR[32] - * L3 HA Producer SW Access Error - */ - (L3Fir, bit(32)) ? defaultMaskedError; - - /** L3FIR[33] - * L3 HA Line In Consumer Cache Error - */ - (L3Fir, bit(33)) ? defaultMaskedError; - - /** L3FIR[34] - * L3 HA Table In Producer Cache Error - */ - (L3Fir, bit(34)) ? defaultMaskedError; - - /** L3FIR[35] - * L3 HA Log Overflow - */ - (L3Fir, bit(35)) ? defaultMaskedError; - - /** L3FIR[36] - * SCOM_ERR: scom error - */ - (L3Fir, bit(36)) ? defaultMaskedError; - - /** L3FIR[37] - * SCOM_ERR: scom error - */ - (L3Fir, bit(37)) ? defaultMaskedError; -}; - -################################################################################ -# EX Chiplet NCUFIR -################################################################################ -# Based on p8dd1_mss_FFDC_37_reviewed -############################################################################### -rule NcuFir -{ - CHECK_STOP: NCUFIR & ~NCUFIR_MASK & ~NCUFIR_ACT0 & ~NCUFIR_ACT1; - RECOVERABLE: NCUFIR & ~NCUFIR_MASK & ~NCUFIR_ACT0 & NCUFIR_ACT1; -}; - -group gNcuFir filter singlebit -{ - /** NCUFIR[0] - * CONTROL_ERR: H/W control error. - */ - (NcuFir, bit(0)) ? SelfHighThr1; - - /** NCUFIR[1] - * TLBIE_SW_ERR: TLBIE received illegal AP/LP field from core. - */ - (NcuFir, bit(1)) ? calloutExLowSecLvlThr1MedDumpSh; - - /** NCUFIR[2] - * ST_ADDR_ERR: Store address machine or TLBIE/sync machine received - * addr_err cresp. - */ - (NcuFir, bit(2)) ? calloutExLowSecLvlThr1MedDumpSh; - - /** NCUFIR[3] - * LD_ADDR_ERR: Load address machine received addr_err cresp. - */ - (NcuFir, bit(3)) ? calloutExLowSecLvlThr1MedDumpSh; - - /** NCUFIR[4] - * ST_FOREIGN0_ACK_DEAD: Store received ack_dead on foreign link0. - */ - (NcuFir, bit(4)) ? defaultMaskedError; - - /** NCUFIR[5] - * ST_FOREIGN1_ACK_DEAD: Store received ack_dead on foreign link1. - */ - (NcuFir, bit(5)) ? defaultMaskedError; - - /** NCUFIR[6] - * LD_FOREIGN0_ACK_DEAD: Load received ack_dead on foreign link0. - */ - (NcuFir, bit(6)) ? defaultMaskedError; - - /** NCUFIR[7] - * LD_FOREIGN1_ACK_DEAD: Load received ack_dead on foreign link1. - */ - (NcuFir, bit(7)) ? defaultMaskedError; - - /** NCUFIR[8] - * STQ_DATA_PARITY_ERR: Store data parity error from regfile detected. - */ - (NcuFir, bit(8)) ? SelfHighThr1UE; - - /** NCUFIR[9] - * STORE_TIMEOUT: Store timed out on PB. - */ - (NcuFir, bit(9)) ? callout2ndLvlMedThr1; - - /** NCUFIR[10] - * TLBIE_MASTER_TIMEOUT: TLBIE master timed out on PB. - */ - (NcuFir, bit(10)) ? calloutExLowSecLvlThr1MedDumpSh; - - /** NCUFIR[11] - * TLBIE_SNOOP_TIMEOUT: TLBIE snooper timed out waiting for core. - */ - (NcuFir, bit(11)) ? SelfHighThr1; - - /** NCUFIR[12] - * HTM_IMA_TIMEOUT: HTM/IMA address machine timed out on PB. - */ - (NcuFir, bit(12)) ? calloutExLowSecLvlThr1MedDumpSh; - - /** NCUFIR[13] - * IMA_CRESP_ADDR_ERR: IMA received addr_err cresp. - */ - (NcuFir, bit(13)) ? calloutExLowSecLvlThr1MedDumpSh; - - /** NCUFIR[14] - * IMA_FOREIGN0_ACK_DEAD: IMA received ack_dead on foreign link0. - */ - (NcuFir, bit(14)) ? defaultMaskedError; - - /** NCUFIR[15] - * IMA_FOREIGN1_ACK_DEAD: IMA received ack_dead on foreign link1. - */ - (NcuFir, bit(15)) ? defaultMaskedError; - - /** NCUFIR[16] - * HTM_GOT_ACK_DEAD: HTM received ack_dead on any foreign link. - */ - (NcuFir, bit(16)) ? defaultMaskedError; - - /** NCUFIR[17] - * PMISC_CRESP_ADDR_ERR: PMISC received address error cresp. - */ - - (NcuFir, bit(17)) ? calloutParentProcHighThr1; - - /** NCUFIR[18] - * TLBIE_CONTROL_ERR: TLBIE control error. - */ - (NcuFir, bit(18)) ? calloutExLowSecLvlThr1MedDumpSh; - - /** NCUFIR[19|20|21|22|23] - * SPARE - */ - (NcuFir, bit(19|20|21|22|23)) ? defaultMaskedError; - - /** NCUFIR[24] - * SCOM_ERR1: scom error - */ - (NcuFir, bit(24)) ? defaultMaskedError; - - /** NCUFIR[25] - * SCOM_ERR2: scom error - */ - (NcuFir, bit(25)) ? defaultMaskedError; -}; - - ############################################################################## - # # - # # ### # - # # # ## ##### ### ### # # # # # # ### ### ### ### # - # # # # # # # # # ## # # # # # # # # # # - # ####### # # # # # # # # # # ##### ### ### ## ### # - # # # # # # # # # # ## # # # # # # # # # # - # # # ## # ### ### # # ### ### # # ### ### ### ### # - # # - ############################################################################## - -# Include the common action set. -.include "CommonActions.rule" - -# When analyzing CoreFir, check for/handle core checkstop -actionclass analyzeCore -{ - funccall("CheckCoreCheckstop"); - # if core recoverable is not set in COREWOF and - # Core CS is on, analyze core checkstop - try(funccall("CoreRePresent"), funccall("SetCoreCheckstopCause")); - analyze(gCoreFir); - funccall("MaskIfCoreCheckstop"); - funccall("RestartTraceArray"); -}; - -# Chiplet recoverable FIR indicated Core checkstop, so take actions for -# handling core checkstop. Analyze CoreFir. -actionclass analyzeCoreUnitCheckstop -{ - funccall("CheckCoreCheckstop"); - funccall("SetCoreCheckstopCause"); - analyze(gCoreFir); - funccall("MaskIfCoreCheckstop"); -}; - -actionclass analyzeExLFir -{ - analyze(gExLFir); - funccall("RestartTraceArray"); -}; - -actionclass analyzeL2Fir -{ - analyze(gL2Fir); - funccall("RestartTraceArray"); -}; - -actionclass analyzeL3Fir -{ - analyze(gL3Fir); - funccall("RestartTraceArray"); -}; - -actionclass analyzeNcuFir -{ - analyze(gNcuFir); - funccall("RestartTraceArray"); -}; - -actionclass L3DirCE -{ - calloutSelfHigh; - threshold( field(32 / day), mfg_file(ATTR_MNFG_TH_P8EX_L3_DIR_CES) ); -}; - -actionclass L3UE -{ - SelfHighThr1UE; - funccall("L3UE"); -}; - -# Thresholding and runtime handling (line deletes and column repairs) -# for cache CEs - -actionclass L3CE -{ - calloutSelfHigh; - threshold( field(32 / day), mfg_file(ATTR_MNFG_TH_P8EX_L3_CACHE_CES) ); - funccall("L3CE"); # This is no-operation for Hostboot -}; - -actionclass L2CE -{ - calloutSelfHigh; - threshold( field(32 / day), mfg_file(ATTR_MNFG_TH_P8EX_L2_CACHE_CES) ); - funccall("L2CE"); # This is no-operation for Hostboot -}; - -actionclass L2UE -{ - SelfHighThr1UE; - funccall("L2UE"); -}; - -actionclass L2DirCE -{ - calloutSelfHigh; - threshold( field(32 / day), mfg_file(ATTR_MNFG_TH_P8EX_L2_DIR_CES) ); -}; - -actionclass L2ChipLevel2 -{ - calloutParentProcLow; - callout2ndLvlMed; - threshold1; -}; - -actionclass calloutSelfHighSUE -{ - SelfHighThr1; - flag(SUE); -}; - -actionclass calloutParentProcLow -{ - callout(connected(TYPE_PROC),MRU_LOW); -}; - -/** calls out Ex if threshold exceeds. Calls for second level support as well, - * garding not required */ -actionclass SelfAndLevel2MedThr5PerHrNoGard -{ - calloutSelfMedNoGard; - callout2ndLvlMed; - threshold5phour; -}; - -/** callouts Proc on first instance. Calls for second level support as well */ -actionclass calloutProcLow2ndLvlMedThr1 -{ - calloutParentProcLow; - callout2ndLvlMed; - threshold1; - -}; - -/** Calls out and gards the parent PROC on first instance. Also, calls for - * second level support just in case replacing the processor did not resolve - * the issue. This bit is also a possible checkstop SUE. */ -actionclass nestHangDetect -{ - callout(connected(TYPE_PROC),MRU_MED); - callout2ndLvlLow; - threshold1; - flag(SUE); -}; - -/** callout connected parent proc with high priority.*/ -actionclass calloutParentProcHigh -{ - callout(connected(TYPE_PROC),MRU_HIGH); -}; - -/** callout parent proc. Threshold is 32 events per day */ -actionclass calloutParentChipHighThr32 -{ - calloutParentProcHigh; - threshold32pday; -}; - -/** callout core, threshold 5 per day */ -actionclass calloutExThr5pHr -{ - SelfHighThr5PerHour; -}; - -/** callout core, threshold 32per day and initiate hw dump*/ -actionclass calloutExThr32pDay -{ - SelfMedThr32PerDay; -}; - -actionclass calloutExLowSecLvlThr1MedDumpSh -{ - SelfLowLevel2MedThr1; - dumpSH; -}; - -/** callout 2nd level med priority, core low priority */ -actionclass calloutLevel2MedExLowThr1 -{ - callout2ndLvlMed; - calloutSelfLow; - threshold1; -}; diff --git a/src/usr/diag/prdf/common/plat/pegasus/MuranoVeniceProc.rule b/src/usr/diag/prdf/common/plat/pegasus/MuranoVeniceProc.rule deleted file mode 100644 index 5c0a74155..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/MuranoVeniceProc.rule +++ /dev/null @@ -1,170 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/MuranoVeniceProc.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2015 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -chip Proc -{ - name "Power8 Murano or Venice Chip"; - targettype TYPE_PROC; - sigoff 0x8000; - dump DUMP_CONTENT_HW; - scomlen 64; - -#Import signatures -.include "prdfP8ProcExtraSig.H"; -.include "prdfP8ProcMbCommonExtraSig.H"; - -#Import Common Proc Registers -.include "Proc_regs_common.rule" - -# Import all of the chiplet registers -.include "Proc_regs_TP.rule" -.include "Proc_regs_PB.rule" -.include "Proc_regs_XBUS.rule" -.include "Proc_regs_ABUS.rule" -.include "Proc_regs_PCIE.rule" - -}; - -################################################################################ -# Global Broadcast Registers -################################################################################ - -rule GlobalFir -{ - CHECK_STOP: GLOBAL_CS_FIR; - RECOVERABLE: GLOBAL_RE_FIR; -}; - -group gGlobalFir attntype CHECK_STOP, RECOVERABLE filter singlebit -{ - /** GLOBAL_FIR[1] - * Attention from TP chiplet - */ - (GlobalFir, bit(1)) ? analyze(gTpChipletFir); - - /** GLOBAL_FIR[2] - * Attention from PB chiplet - */ - (GlobalFir, bit(2)) ? analyze(gPbChipletFir); - - /** GLOBAL_FIR[4] - * Attention from XBUS chiplet - */ - (GlobalFir, bit(4)) ? analyze(gXbusChipletFir); - - /** GLOBAL_FIR[8] - * Attention from ABUS - */ - (GlobalFir, bit(8)) ? analyze(gAbusChipletFir); - - /** GLOBAL_FIR[9] - * Attention from PCIE - */ - (GlobalFir, bit(9)) ? analyze(gPcieChipletFir); - - /** GLOBAL_FIR[17] - * Attention from EX1 (Venice only) - */ - (GlobalFir, bit(17)) ? analyzeEx1; - - /** GLOBAL_FIR[18] - * Attention from EX2 (Venice only) - */ - (GlobalFir, bit(18)) ? analyzeEx2; - - /** GLOBAL_FIR[19] - * Attention from EX3 (Venice only) - */ - (GlobalFir, bit(19)) ? analyzeEx3; - - /** GLOBAL_FIR[20] - * Attention from EX4 - */ - (GlobalFir, bit(20)) ? analyzeEx4; - - /** GLOBAL_FIR[21] - * Attention from EX5 - */ - (GlobalFir, bit(21)) ? analyzeEx5; - - /** GLOBAL_FIR[22] - * Attention from EX6 - */ - (GlobalFir, bit(22)) ? analyzeEx6; - - /** GLOBAL_FIR[25] - * Attention from EX9 (Venice only) - */ - (GlobalFir, bit(25)) ? analyzeEx9; - - /** GLOBAL_FIR[26] - * Attention from EX10 (Venice only) - */ - (GlobalFir, bit(26)) ? analyzeEx10; - - /** GLOBAL_FIR[27] - * Attention from EX11 (Venice only) - */ - (GlobalFir, bit(27)) ? analyzeEx11; - - /** GLOBAL_FIR[28] - * Attention from EX12 - */ - (GlobalFir, bit(28)) ? analyzeEx12; - - /** GLOBAL_FIR[29] - * Attention from EX13 - */ - (GlobalFir, bit(29)) ? analyzeEx13; - - /** GLOBAL_FIR[30] - * Attention from EX14 - */ - (GlobalFir, bit(30)) ? analyzeEx14; -}; - -# Import all of the chiplet rules and actions -# NOTE: Some of PB local FIRs are handled through the TP chiplet FIRs -.include "Proc_acts_TP.rule" -.include "Proc_acts_PB.rule" -.include "Proc_acts_XBUS.rule" -.include "Proc_acts_ABUS.rule" -.include "Proc_acts_PCIE.rule" - - ############################################################################## - # # - # # ### # - # # # ## ##### ### ### # # # # # # ### ### ### ### # - # # # # # # # # # ## # # # # # # # # # # - # ####### # # # # # # # # # # ##### ### ### ## ### # - # # # # # # # # # # ## # # # # # # # # # # - # # # ## # ### ### # # ### ### # # ### ### ### ### # - # # - ############################################################################## - -# Include the common action set. -.include "CommonActions.rule" - -#import common Proc actions -.include "Proc_acts_common.rule" diff --git a/src/usr/diag/prdf/common/plat/pegasus/NaplesProc.rule b/src/usr/diag/prdf/common/plat/pegasus/NaplesProc.rule deleted file mode 100644 index d0b1da33d..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/NaplesProc.rule +++ /dev/null @@ -1,170 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/NaplesProc.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2015 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -chip Proc -{ - name "Power8 Naples Chip"; - targettype TYPE_PROC; - sigoff 0x4000; - dump DUMP_CONTENT_HW; - scomlen 64; - -#Import signatures -.include "prdfP8ProcExtraSig.H"; -.include "prdfP8ProcMbCommonExtraSig.H"; - -#Import Common Proc rule file -.include "Proc_regs_common.rule" - -# Import all of the chiplet registers -.include "Proc_regs_TP.rule" -.include "Proc_regs_PB.rule" -.include "Proc_regs_XBUS.rule" -.include "Proc_regs_NV.rule" -.include "Proc_regs_PCIE.rule" - -}; - -################################################################################ -# Global Broadcast Registers -################################################################################ - -rule GlobalFir -{ - CHECK_STOP: GLOBAL_CS_FIR; - RECOVERABLE: GLOBAL_RE_FIR; -}; - -group gGlobalFir attntype CHECK_STOP, RECOVERABLE filter singlebit -{ - /** GLOBAL_FIR[1] - * Attention from TP chiplet - */ - (GlobalFir, bit(1)) ? analyze(gTpChipletFir); - - /** GLOBAL_FIR[2] - * Attention from PB chiplet - */ - (GlobalFir, bit(2)) ? analyze(gPbChipletFir); - - /** GLOBAL_FIR[4] - * Attention from XBUS chiplet - */ - (GlobalFir, bit(4)) ? analyze(gXbusChipletFir); - - /** GLOBAL_FIR[8] - * Attention from NV - */ - (GlobalFir, bit(8)) ? analyze(gNvChipletFir); - - /** GLOBAL_FIR[9] - * Attention from PCIE - */ - (GlobalFir, bit(9)) ? analyze(gPcieChipletFir); - - /** GLOBAL_FIR[17] - * Attention from EX1 (Venice only) - */ - (GlobalFir, bit(17)) ? analyzeEx1; - - /** GLOBAL_FIR[18] - * Attention from EX2 (Venice only) - */ - (GlobalFir, bit(18)) ? analyzeEx2; - - /** GLOBAL_FIR[19] - * Attention from EX3 (Venice only) - */ - (GlobalFir, bit(19)) ? analyzeEx3; - - /** GLOBAL_FIR[20] - * Attention from EX4 - */ - (GlobalFir, bit(20)) ? analyzeEx4; - - /** GLOBAL_FIR[21] - * Attention from EX5 - */ - (GlobalFir, bit(21)) ? analyzeEx5; - - /** GLOBAL_FIR[22] - * Attention from EX6 - */ - (GlobalFir, bit(22)) ? analyzeEx6; - - /** GLOBAL_FIR[25] - * Attention from EX9 (Venice only) - */ - (GlobalFir, bit(25)) ? analyzeEx9; - - /** GLOBAL_FIR[26] - * Attention from EX10 (Venice only) - */ - (GlobalFir, bit(26)) ? analyzeEx10; - - /** GLOBAL_FIR[27] - * Attention from EX11 (Venice only) - */ - (GlobalFir, bit(27)) ? analyzeEx11; - - /** GLOBAL_FIR[28] - * Attention from EX12 - */ - (GlobalFir, bit(28)) ? analyzeEx12; - - /** GLOBAL_FIR[29] - * Attention from EX13 - */ - (GlobalFir, bit(29)) ? analyzeEx13; - - /** GLOBAL_FIR[30] - * Attention from EX14 - */ - (GlobalFir, bit(30)) ? analyzeEx14; -}; - -# Import all of the chiplet rules and actions -# NOTE: Some of PB local FIRs are handled through the TP chiplet FIRs -.include "Proc_acts_TP.rule" -.include "Proc_acts_PB.rule" -.include "Proc_acts_XBUS.rule" -.include "Proc_acts_NV.rule" -.include "Proc_acts_PCIE.rule" - - ############################################################################## - # # - # # ### # - # # # ## ##### ### ### # # # # # # ### ### ### ### # - # # # # # # # # # ## # # # # # # # # # # - # ####### # # # # # # # # # # ##### ### ### ## ### # - # # # # # # # # # # ## # # # # # # # # # # - # # # ## # ### ### # # ### ### # # ### ### ### ### # - # # - ############################################################################## - -# Include the common action set. -.include "CommonActions.rule" - -#import common Proc actions -.include "Proc_acts_common.rule" diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_ABUS.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_ABUS.rule deleted file mode 100755 index 6c1d41ca6..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_ABUS.rule +++ /dev/null @@ -1,616 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc_acts_ABUS.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2017 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -################################################################################ -# ABUS Chiplet Registers -################################################################################ - -rule AbusChipletFir -{ - CHECK_STOP: - (ABUS_CHIPLET_CS_FIR & `1C00000000000000`) & ~ABUS_CHIPLET_FIR_MASK; - RECOVERABLE: - ((ABUS_CHIPLET_RE_FIR >> 2) & `1C00000000000000`) & ~ABUS_CHIPLET_FIR_MASK; -}; - -group gAbusChipletFir filter singlebit -{ - /** ABUS_CHIPLET_FIR[3] - * Attention from LFIR - */ - (AbusChipletFir, bit(3)) ? analyze(gAbusLFir); - - /** ABUS_CHIPLET_FIR[4] - * Attention from PBESFIR - */ - (AbusChipletFir, bit(4)) ? analyze(gPbesFir); - - /** ABUS_CHIPLET_FIR[5] - * Attention from IOAFIR - */ - (AbusChipletFir, bit(5)) ? analyze(gIoaFir); -}; - -################################################################################ -# ABUS Chiplet LFIR -################################################################################ - -rule AbusLFir -{ - CHECK_STOP: ABUS_LFIR & ~ABUS_LFIR_MASK & ~ABUS_LFIR_ACT0 & ~ABUS_LFIR_ACT1; - RECOVERABLE: ABUS_LFIR & ~ABUS_LFIR_MASK & ~ABUS_LFIR_ACT0 & ABUS_LFIR_ACT1; -}; - -group gAbusLFir filter singlebit -{ - /** ABUS_LFIR[0] - * CFIR internal parity error - */ - (AbusLFir, bit(0)) ? SelfHighThr32PerDay; - - /** ABUS_LFIR[1] - * Local errors from GPIO (PCB error) - */ - (AbusLFir, bit(1)) ? defaultMaskedError; - - /** ABUS_LFIR[2] - * Local errors from CC (PCB error) - */ - (AbusLFir, bit(2)) ? SelfHighThr32PerDay; - - /** ABUS_LFIR[3] - * Local errors from CC (OPCG, parity, scan collision, ...) - */ - (AbusLFir, bit(3)) ? callout2ndLvlMedThr32; - - /** ABUS_LFIR[4] - * Local errors from PSC (PCB error) - */ - (AbusLFir, bit(4)) ? defaultMaskedError; - - /** ABUS_LFIR[5] - * Local errors from PSC (parity error) - */ - (AbusLFir, bit(5)) ? defaultMaskedError; - - /** ABUS_LFIR[6] - * Local errors from Thermal (parity error) - */ - (AbusLFir, bit(6)) ? defaultMaskedError; - - /** ABUS_LFIR[7] - * Local errors from Thermal (PCB error) - */ - (AbusLFir, bit(7)) ? defaultMaskedError; - - /** ABUS_LFIR[8|9] - * Local errors from Thermal (Trip error) - */ - (AbusLFir, bit(8|9)) ? defaultMaskedError; - - /** ABUS_LFIR[10|11] - * Local errors from Trace Array ( error) - */ - (AbusLFir, bit(10|11)) ? defaultMaskedError; - - /** ABUS_LFIR[12:20] - * FIR_IN12: unused local errors - */ - (AbusLFir, bit(12|13|14|15|16|17|18|19|20)) ? defaultMaskedError; - - /** ABUS_LFIR[21:30] - * FIR_IN12: unused local errors - */ - (AbusLFir, bit(21|22|23|24|25|26|27|28|29|30)) ? defaultMaskedError; - - /** ABUS_LFIR[31:39] - * FIR_IN12: unused local errors - */ - (AbusLFir, bit(31|32|33|34|35|36|37|38|39)) ? defaultMaskedError; - - /** ABUS_LFIR[40] - * Malfunction alert - */ - (AbusLFir, bit(40)) ? defaultMaskedError; -}; - -################################################################################ -# ABUS Chiplet PBESFIR -################################################################################ -# based on p8dd1_mss_FFDC_37_ reviewd.xls -################################################################################ - -rule PbesFir -{ - CHECK_STOP: - PBESFIR & ~PBESFIR_MASK & ~PBESFIR_ACT0 & ~PBESFIR_ACT1; - RECOVERABLE: - PBESFIR & ~PBESFIR_MASK & ~PBESFIR_ACT0 & PBESFIR_ACT1; -}; - - -group gPbesFir filter singlebit, - secondarybits( 6, 9, 12 ) -{ - /** PBESFIR[0] - * A0LINK_FMR_ERROR: a0link_fmr_error - */ - (PbesFir, bit(0)) ? SelfHighThr1; - - /** PBESFIR[1] - * A1LINK_FMR_ERROR: a1link_fmr_error - */ - (PbesFir, bit(1)) ? SelfHighThr1; - - /** PBESFIR[2] - * A2LINK_FMR_ERROR: a2link_fmr_error - */ - (PbesFir, bit(2)) ? SelfHighThr1; - - /** PBESFIR[3] - * A0LINK_PSR_ERR: a0link_psr_err - */ - (PbesFir, bit(3)) ? SelfHighThr1; - - /** PBESFIR[4] - * A1LINK_PSR_ERR: a1link_psr_err - */ - (PbesFir, bit(4)) ? SelfHighThr1; - - /** PBESFIR[5] - * A2LINK_PSR_ERR: a2link_psr_err - */ - (PbesFir, bit(5)) ? SelfHighThr1; - - /** PBESFIR[6] - * A0LINK_PSR_COR_ERR - */ - (PbesFir, bit(6)) ? calloutAbus0InterfaceTh5; - - /** PBESFIR[7] - * A0LINK_PSR_DERR_ERR - */ - (PbesFir, bit(7)) ? defaultMaskedError; - - /** PBESFIR[8] - * A0LINK_PSR_UNC_ERR - */ - (PbesFir, bit(8)) ? calloutAbus0InterfaceTh1; - - /** PBESFIR[9] - * A1LINK_PSR_COR_ERR - */ - (PbesFir, bit(9)) ? calloutAbus1InterfaceTh5; - - /** PBESFIR[10] - * A1LINK_PSR_DERR_ERR - */ - (PbesFir, bit(10)) ? defaultMaskedError; - - /** PBESFIR[11] - * A1LINK_PSR_UNC_ERR - */ - (PbesFir, bit(11)) ? calloutAbus1InterfaceTh1; - - /** PBESFIR[12] - * A2LINK_PSR_COR_ERR - */ - (PbesFir, bit(12)) ? calloutAbus2InterfaceTh5; - - /** PBESFIR[13] - * A2LINK_PSR_DERR_ERR - */ - (PbesFir, bit(13)) ? defaultMaskedError; - - /** PBESFIR[14] - * A2LINK_PSR_UNC_ERR - */ - (PbesFir, bit(14)) ? calloutAbus2InterfaceTh1; - - /** PBESFIR[15] - * A0LINK_FMR_COR_ERR_HI - */ - (PbesFir, bit(15)) ? SelfHighThr32PerDay; - - /** PBESFIR[16] - * A0LINK_FMR_COR_ERR_LO - */ - (PbesFir, bit(16)) ? SelfHighThr32PerDay; - - /** PBESFIR[17] - * A0LINK_FMR_SUE_ERR_HI - */ - (PbesFir, bit(17)) ? defaultMaskedError; - - /** PBESFIR[18] - * A0LINK_FMR_SUE_ERR_LO - */ - (PbesFir, bit(18)) ? defaultMaskedError; - - /** PBESFIR[19] - * A0LINK_FMR_UNC_ERR_HI - */ - (PbesFir, bit(19)) ? calloutProcHighThr1SUE; - - /** PBESFIR[20] - * A0LINK_FMR_UNC_ERR_LO - */ - (PbesFir, bit(20)) ? calloutProcHighThr1SUE; - - /** PBESFIR[21] - * A1LINK_FMR_COR_ERR_HI - */ - (PbesFir, bit(21)) ? SelfHighThr32PerDay; - - /** PBESFIR[22] - * A1LINK_FMR_COR_ERR_LO - */ - (PbesFir, bit(22)) ? SelfHighThr32PerDay; - - /** PBESFIR[23] - * A1LINK_FMR_SUE_ERR_HI - */ - (PbesFir, bit(23)) ? defaultMaskedError; - - /** PBESFIR[24] - * A1LINK_FMR_SUE_ERR_LO - */ - (PbesFir, bit(24)) ? defaultMaskedError; - - /** PBESFIR[25] - * A1LINK_FMR_UNC_ERR_HI - */ - (PbesFir, bit(25)) ? calloutProcHighThr1SUE; - - /** PBESFIR[26] - * A1LINK_FMR_UNC_ERR_LO - */ - (PbesFir, bit(26)) ? calloutProcHighThr1SUE; - - /** PBESFIR[27] - * A2LINK_FMR_COR_ERR_HI - */ - (PbesFir, bit(27)) ? SelfHighThr32PerDay; - - /** PBESFIR[28] - * A2LINK_FMR_COR_ERR_LO - */ - (PbesFir, bit(28)) ? SelfHighThr32PerDay; - - /** PBESFIR[29] - * A2LINK_FMR_SUE_ERR_HI - */ - (PbesFir, bit(29)) ? defaultMaskedError; - - /** PBESFIR[30] - * A2LINK_FMR_SUE_ERR_LO - */ - (PbesFir, bit(30)) ? defaultMaskedError; - - /** PBESFIR[31] - * A2LINK_FMR_UNC_ERR_HI - */ - (PbesFir, bit(31)) ? calloutProcHighThr1SUE; - - /** PBESFIR[32] - * A2LINK_FMR_UNC_ERR_LO - */ - (PbesFir, bit(32)) ? calloutProcHighThr1SUE; - - /** PBESFIR[33] - * A0_OBS_CR_OVERFLOW_FIR_ERR - */ - (PbesFir, bit(33)) ? SelfHighThr1; - - /** PBESFIR[34] - * A1_OBS_CR_OVERFLOW_FIR_ERR - */ - (PbesFir, bit(34)) ? SelfHighThr1; - - /** PBESFIR[35] - * A2_OBS_CR_OVERFLOW_FIR_ERR - */ - (PbesFir, bit(35)) ? SelfHighThr1; - - /** PBESFIR[36] - * FIR_SCOM_ERR_DUP - */ - (PbesFir, bit(36)) ? defaultMaskedError; - - /** PBESFIR[37] - * FIR_SCOM_ERR - */ - (PbesFir, bit(37)) ? defaultMaskedError; - - # If bit 3 and 8 turn on simultaneously, action should be same as - # in case of bit 8. - - /** PBESFIR[3,8] - * A0LINK_PSR_UNC_ERR - */ - (PbesFir, bit(3,8)) ? calloutAbus0InterfaceTh1; - - # If bit 4 and 11 turn on simultaneously, action should be same as - # in case of bit 11. - - /** PBESFIR[4,11] - * A1LINK_PSR_UNC_ERR - */ - (PbesFir, bit(4,11)) ? calloutAbus1InterfaceTh1; - - # If bit 5 and 14 turn on simultaneously, action should be same as - # in case of bit 14. - - /** PBESFIR[5,14] - * A2LINK_PSR_UNC_ERR - */ - (PbesFir, bit(5,14)) ? calloutAbus2InterfaceTh1; -}; - -################################################################################ -# ABUS Chiplet IOAFIR -################################################################################ - -rule IoaFir -{ - CHECK_STOP: IOAFIR & ~IOAFIR_MASK & ~IOAFIR_ACT0 & ~IOAFIR_ACT1; - RECOVERABLE: IOAFIR & ~IOAFIR_MASK & ~IOAFIR_ACT0 & IOAFIR_ACT1; -}; - -group gIoaFir filter singlebit, - secondarybits( 17, 25, 33 ) -{ - /** IOAFIR[0] - * FIR_RX_INVALID_STATE_OR_PARITY_ERROR - */ - (IoaFir, bit(0)) ? defaultMaskedError; - - /** IOAFIR[1] - * FIR_TX_INVALID_STATE_OR_PARITY_ERROR - */ - (IoaFir, bit(1)) ? defaultMaskedError; - - /** IOAFIR[2] - * FIR_GCR_HANG_ERROR - */ - (IoaFir, bit(2)) ? SelfHighThr1; - - /** IOAFIR[3:7] - * Reserved - */ - (IoaFir, bit(3|4|5|6|7)) ? defaultMaskedError; - - /** IOAFIR[8:15] - * FIR_RX_BUS0 unused - */ - (IoaFir, bit(8|9|10|11|12|13|14|15)) ? defaultMaskedError; - - /** IOAFIR[16] - * ABUS0 Training Error - */ - (IoaFir, bit(16)) ? defaultMaskedError; - - /** IOAFIR[17] - * ABUS0 Spare Deployed - */ - (IoaFir, bit(17)) ? spareDeployed_abus0; - - /** IOAFIR[18] - * ABUS0 Max Spares Exceeded - */ - (IoaFir, bit(18)) ? maxSparesExceeded_abus0; - - /** IOAFIR[19] - * ABUS0 Recalibration or Dynamic Repair Error - */ - (IoaFir, bit(19)) ? calloutAbus0InterfaceTh1; - - /** IOAFIR[20] - * ABUS0 Too Many Bus Errors - */ - (IoaFir, bit(20)) ? tooManyBusErrors_abus0; - - /** IOAFIR[21:23] - * Reserved - */ - (IoaFir, bit(21|22|23)) ? defaultMaskedError; - - /** IOAFIR[24] - * ABUS1 Training Error - */ - (IoaFir, bit(24)) ? defaultMaskedError; - - /** IOAFIR[25] - * ABUS1 Spare Deployed - */ - (IoaFir, bit(25)) ? spareDeployed_abus1; - - /** IOAFIR[26] - * ABUS1 Max Spares Exceeded - */ - (IoaFir, bit(26)) ? maxSparesExceeded_abus1; - - /** IOAFIR[27] - * ABUS1 Recalibration or Dynamic Repair Error - */ - (IoaFir, bit(27)) ? calloutAbus1InterfaceTh1; - - /** IOAFIR[28] - * ABUS1 Too Many Bus Errors - */ - (IoaFir, bit(28)) ? tooManyBusErrors_abus1; - - /** IOAFIR[29:31] - * Reserved - */ - (IoaFir, bit(29|30|31)) ? defaultMaskedError; - - /** IOAFIR[32] - * ABUS2 Training Error - */ - (IoaFir, bit(32)) ? defaultMaskedError; - - /** IOAFIR[33] - * ABUS2 Spare Deployed - */ - (IoaFir, bit(33)) ? spareDeployed_abus2; - - /** IOAFIR[34] - * ABUS2 Max Spares Exceeded - */ - (IoaFir, bit(34)) ? maxSparesExceeded_abus2; - - /** IOAFIR[35] - * ABUS2 Recalibration or Dynamic Repair Error - */ - (IoaFir, bit(35)) ? calloutAbus2InterfaceTh1; - - /** IOAFIR[36] - * ABUS2 Too Many Bus Errors - */ - (IoaFir, bit(36)) ? tooManyBusErrors_abus2; - - /** IOAFIR[37:39] - * Reserved - */ - (IoaFir, bit(37|38|39)) ? defaultMaskedError; - - /** IOAFIR[40:47] - * FIR_RX_BUS4 unused - */ - (IoaFir, bit(40|41|42|43|44|45|46|47)) ? defaultMaskedError; - - /** IOAFIR[48] - * FIR_SCOMFIR_ERROR - */ - (IoaFir, bit(48)) ? defaultMaskedError; - - /** IOAFIR[49] - * FIR_SCOMFIR_ERROR_CLONE - */ - (IoaFir, bit(49)) ? defaultMaskedError; -}; - -################################################################################ -# Actions specific to ABUS chiplet -################################################################################ - - -/** Callout the ABUS 0 interface */ -actionclass calloutAbus0Interface -{ - callout(procedure(FAB_BUS_OFF_NODE), MRU_MED); - callout(connected(TYPE_ABUS, 0), MRU_MEDA); - callout(connected_peer(TYPE_ABUS, 0), MRU_MEDA); - funccall("calloutInterface_abus0"); -}; - -/** Callout the ABUS 1 interface */ -actionclass calloutAbus1Interface -{ - callout(procedure(FAB_BUS_OFF_NODE), MRU_MED); - callout(connected(TYPE_ABUS, 1), MRU_MEDA); - callout(connected_peer(TYPE_ABUS, 1), MRU_MEDA); - funccall("calloutInterface_abus1"); -}; - -/** Callout the ABUS 2 interface */ -actionclass calloutAbus2Interface -{ - callout(procedure(FAB_BUS_OFF_NODE), MRU_MED); - callout(connected(TYPE_ABUS, 2), MRU_MEDA); - callout(connected_peer(TYPE_ABUS, 2), MRU_MEDA); - funccall("calloutInterface_abus2"); -}; - -/** Callout the ABUS 0 interface, threshold 1 */ -actionclass calloutAbus0InterfaceTh1 { calloutAbus0Interface; threshold1; }; - -/** Callout the ABUS 1 interface, threshold 1 */ -actionclass calloutAbus1InterfaceTh1 { calloutAbus1Interface; threshold1; }; - -/** Callout the ABUS 2 interface, threshold 1 */ -actionclass calloutAbus2InterfaceTh1 { calloutAbus2Interface; threshold1; }; - -/** Threshold 5 per day, mask but do not predictively callout ABUS 0 */ -actionclass calloutAbus0InterfaceTh5 -{ - calloutAbus0Interface; - threshold5pday; - funccall("ClearServiceCallFlag"); -}; - -/** Threshold 5 per day, mask but do not predictively callout ABUS 1 */ -actionclass calloutAbus1InterfaceTh5 -{ - calloutAbus1Interface; - threshold5pday; - funccall("ClearServiceCallFlag"); -}; - -/** Threshold 5 per day, mask but do not predictively callout ABUS 2 */ -actionclass calloutAbus2InterfaceTh5 -{ - calloutAbus2Interface; - threshold5pday; - funccall("ClearServiceCallFlag"); -}; - -/** Lane Repair: spare deployed - ABUS 0 */ -actionclass spareDeployed_abus0 -{ calloutAbus0Interface; funccall("spareDeployed_abus0"); }; - -/** Lane Repair: spare deployed - ABUS 1 */ -actionclass spareDeployed_abus1 -{ calloutAbus1Interface; funccall("spareDeployed_abus1"); }; - -/** Lane Repair: spare deployed - ABUS 2 */ -actionclass spareDeployed_abus2 -{ calloutAbus2Interface; funccall("spareDeployed_abus2"); }; - -/** Lane Repair: max spares exceeded - ABUS 0 */ -actionclass maxSparesExceeded_abus0 -{ calloutAbus0InterfaceTh1; funccall("maxSparesExceeded_abus0"); }; - -/** Lane Repair: max spares exceeded - ABUS 1 */ -actionclass maxSparesExceeded_abus1 -{ calloutAbus1InterfaceTh1; funccall("maxSparesExceeded_abus1"); }; - -/** Lane Repair: max spares exceeded - ABUS 1 */ -actionclass maxSparesExceeded_abus2 -{ calloutAbus2InterfaceTh1; funccall("maxSparesExceeded_abus2"); }; - -/** Lane Repair: too many bus errors - ABUS 0 */ -actionclass tooManyBusErrors_abus0 -{ calloutAbus0InterfaceTh1; funccall("tooManyBusErrors_abus0"); }; - -/** Lane Repair: too many bus errors - ABUS 1 */ -actionclass tooManyBusErrors_abus1 -{ calloutAbus1InterfaceTh1; funccall("tooManyBusErrors_abus1"); }; - -/** Lane Repair: too many bus errors - ABUS 2 */ -actionclass tooManyBusErrors_abus2 -{ calloutAbus2InterfaceTh1; funccall("tooManyBusErrors_abus2"); }; - diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_NV.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_NV.rule deleted file mode 100755 index 408f3d938..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_NV.rule +++ /dev/null @@ -1,583 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc_acts_NV.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2015,2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -################################################################################ -# NV Chiplet Registers -################################################################################ - -rule NvChipletFir -{ - CHECK_STOP: - (NV_CHIPLET_CS_FIR & `1700000000000000`) & ~NV_CHIPLET_FIR_MASK; - RECOVERABLE: - ((NV_CHIPLET_RE_FIR >> 2) & `1700000000000000`) & ~NV_CHIPLET_FIR_MASK; -}; - -group gNvChipletFir filter singlebit -{ - /** NV_CHIPLET_FIR[3] - * Attention from LFIR - */ - (NvChipletFir, bit(3)) ? analyze(gNVLFir); - - /** NV_CHIPLET_FIR[5] - * Attention from IONVFIR_0 - */ - (NvChipletFir, bit(5)) ? analyze(gIoNvFir_0); - - /** NV_CHIPLET_FIR[6] - * Attention from NPU - */ - (NvChipletFir, bit(6)) ? analyze(gNpuFir); - - /** NV_CHIPLET_FIR[7] - * Attention from IONVFIR_1 - */ - (NvChipletFir, bit(7)) ? analyze(gIoNvFir_1); -}; - -################################################################################ -# NV Chiplet LFIR -################################################################################ - -rule NVLFir -{ - CHECK_STOP: NV_LFIR & ~NV_LFIR_MASK & ~NV_LFIR_ACT0 & ~NV_LFIR_ACT1; - RECOVERABLE: NV_LFIR & ~NV_LFIR_MASK & ~NV_LFIR_ACT0 & NV_LFIR_ACT1; -}; - -group gNVLFir filter singlebit -{ - /** NV_LFIR[0] - * CFIR internal parity error - */ - (NVLFir, bit(0)) ? SelfHighThr32PerDay; - - /** NV_LFIR[1] - * Local errors from GPIO (PCB error) - */ - (NVLFir, bit(1)) ? defaultMaskedError; - - /** NV_LFIR[2] - * Local errors from CC (PCB error) - */ - (NVLFir, bit(2)) ? SelfHighThr32PerDay; - - /** NV_LFIR[3] - * Local errors from CC (OPCG, parity, scan collision, ...) - */ - (NVLFir, bit(3)) ? callout2ndLvlMedThr32; - - /** NV_LFIR[4] - * Local errors from PSC (PCB error) - */ - (NVLFir, bit(4)) ? defaultMaskedError; - - /** NV_LFIR[5] - * Local errors from PSC (parity error) - */ - (NVLFir, bit(5)) ? defaultMaskedError; - - /** NV_LFIR[6] - * Local errors from Thermal (parity error) - */ - (NVLFir, bit(6)) ? defaultMaskedError; - - /** NV_LFIR[7] - * Local errors from Thermal (PCB error) - */ - (NVLFir, bit(7)) ? defaultMaskedError; - - /** NV_LFIR[8|9] - * Local errors from Thermal (Trip error) - */ - (NVLFir, bit(8|9)) ? defaultMaskedError; - - /** NV_LFIR[10|11] - * Local errors from Trace Array ( error) - */ - (NVLFir, bit(10|11)) ? defaultMaskedError; - - /** NV_LFIR[12:20] - * FIR_IN12: unused local errors - */ - (NVLFir, bit(12|13|14|15|16|17|18|19|20)) ? defaultMaskedError; - - /** NV_LFIR[21:30] - * FIR_IN12: unused local errors - */ - (NVLFir, bit(21|22|23|24|25|26|27|28|29|30)) ? defaultMaskedError; - - /** NV_LFIR[31:39] - * FIR_IN12: unused local errors - */ - (NVLFir, bit(31|32|33|34|35|36|37|38|39)) ? defaultMaskedError; - - /** NV_LFIR[40] - * Malfunction alert - */ - (NVLFir, bit(40)) ? defaultMaskedError; -}; - -################################################################################ -# NV Chiplet IONVFIR_0s -################################################################################ - -rule IoNvFir_0 -{ - CHECK_STOP: - IONVFIR_0 & ~IONVFIR_0_MASK & ~IONVFIR_0_ACT0 & ~IONVFIR_0_ACT1; - RECOVERABLE: - IONVFIR_0 & ~IONVFIR_0_MASK & ~IONVFIR_0_ACT0 & IONVFIR_0_ACT1; -}; - -group gIoNvFir_0 filter singlebit -{ - /** IONVFIR_0[0] - * FIR_RX_INVALID_STATE_OR_PARITY_ERROR - */ - (IoNvFir_0, bit(0)) ? SelfMedThr32PerDay; - - /** IONVFIR_0[1] - * FIR_TX_INVALID_STATE_OR_PARITY_ERROR - */ - (IoNvFir_0, bit(1)) ? SelfMedThr32PerDay; - - /** IONVFIR_0[2] - * FIR_GCR_HANG_ERROR - */ - (IoNvFir_0, bit(2)) ? SelfMedThr32PerDay; - - /** IONVFIR_0[3:12] - * RESERVED - */ - (IoNvFir_0, bit(3|4|5|6|7|8|9|10|11|12)) ? defaultMaskedError; - - /** IONVFIR_0[13:22] - * RESERVED - */ - (IoNvFir_0, bit(13|14|15|16|17|18|19|20|21|22)) ? defaultMaskedError; - - /** IONVFIR_0[23:32] - * RESERVED - */ - (IoNvFir_0, bit(23|24|25|26|27|28|29|30|31|32)) ? defaultMaskedError; - - /** IONVFIR_0[33:42] - * RESERVED - */ - (IoNvFir_0, bit(33|34|35|36|37|38|39|40|41|42)) ? defaultMaskedError; - - /** IONVFIR_0[43:47] - * RESERVED - */ - (IoNvFir_0, bit(43|44|45|46|47)) ? defaultMaskedError; - - /** IONVFIR_0[48] - * FIR_SCOMFIR_ERROR - */ - (IoNvFir_0, bit(48)) ? defaultMaskedError; - - /** IONVFIR_0[49] - * FIR_SCOMFIR_ERROR_CLONE - */ - (IoNvFir_0, bit(49)) ? defaultMaskedError; -}; - -rule IoNvFir_1 -{ - CHECK_STOP: - IONVFIR_1 & ~IONVFIR_1_MASK & ~IONVFIR_1_ACT0 & ~IONVFIR_1_ACT1; - RECOVERABLE: - IONVFIR_1 & ~IONVFIR_1_MASK & ~IONVFIR_1_ACT0 & IONVFIR_1_ACT1; -}; - -group gIoNvFir_1 filter singlebit -{ - /** IONVFIR_1[0] - * FIR_RX_INVALID_STATE_OR_PARITY_ERROR - */ - (IoNvFir_1, bit(0)) ? SelfMedThr32PerDay; - - /** IONVFIR_1[1] - * FIR_TX_INVALID_STATE_OR_PARITY_ERROR - */ - (IoNvFir_1, bit(1)) ? SelfMedThr32PerDay; - - /** IONVFIR_1[2] - * FIR_GCR_HANG_ERROR - */ - (IoNvFir_1, bit(2)) ? SelfMedThr32PerDay; - - /** IONVFIR_1[3:12] - * RESERVED - */ - (IoNvFir_1, bit(3|4|5|6|7|8|9|10|11|12)) ? defaultMaskedError; - - /** IONVFIR_1[13:22] - * RESERVED - */ - (IoNvFir_1, bit(13|14|15|16|17|18|19|20|21|22)) ? defaultMaskedError; - - /** IONVFIR_1[23:32] - * RESERVED - */ - (IoNvFir_1, bit(23|24|25|26|27|28|29|30|31|32)) ? defaultMaskedError; - - /** IONVFIR_1[33:42] - * RESERVED - */ - (IoNvFir_1, bit(33|34|35|36|37|38|39|40|41|42)) ? defaultMaskedError; - - /** IONVFIR_1[43:47] - * RESERVED - */ - (IoNvFir_1, bit(43|44|45|46|47)) ? defaultMaskedError; - - /** IONVFIR_1[48] - * FIR_SCOMFIR_ERROR - */ - (IoNvFir_1, bit(48)) ? defaultMaskedError; - - /** IONVFIR_1[49] - * FIR_SCOMFIR_ERROR_CLONE - */ - (IoNvFir_1, bit(49)) ? defaultMaskedError; -}; - -rule NpuFir -{ - CHECK_STOP: NPUFIR & ~NPUFIR_MASK & ~NPUFIR_ACT0 & ~NPUFIR_ACT1; - RECOVERABLE: NPUFIR & ~NPUFIR_MASK & ~NPUFIR_ACT0 & NPUFIR_ACT1; -}; - -group gNpuFir filter singlebit -{ - /** NPUFIR[0] - * TVT Entry Invalid Single PE - */ - (NpuFir, bit(0)) ? defaultMaskedError; - - /** NPUFIR[1] - * TVT Address Range Error Single PE - */ - (NpuFir, bit(1)) ? defaultMaskedError; - - /** NPUFIR[2] - * TCE Page Access Error Single PE - */ - (NpuFir, bit(2)) ? defaultMaskedError; - - /** NPUFIR[3] - * TCE Cache Multiple Hit Error Fatal Error - */ - (NpuFir, bit(3)) ? defaultMaskedError; - - /** NPUFIR[4] - * TCE Request Timeout Error Fatal Error - */ - (NpuFir, bit(4)) ? defaultMaskedError; - - /** NPUFIR[5] - * TCE Fetch Data Error Fatal Error - */ - (NpuFir, bit(5)) ? defaultMaskedError; - - /** NPUFIR[6] - * TCE Directory Parity Error Informational - */ - (NpuFir, bit(6)) ? calloutSelfMedTh32NoGard; - - /** NPUFIR[7] - * TCE Cache Data Array Parity Error Informational - */ - (NpuFir, bit(7)) ? calloutSelfMedTh32NoGard; - - /** NPUFIR[8] - * Addr Translation Effective Address Array UE Fatal Error - */ - (NpuFir, bit(8)) ? defaultMaskedError; - - /** NPUFIR[9] - * Addr Translation Effective Address Array CE Informational - */ - (NpuFir, bit(9)) ? calloutSelfMedTh32NoGard; - - /** NPUFIR[10] - * TVT Parity Error Fatal Error - */ - (NpuFir, bit(10)) ? defaultMaskedError; - - /** NPUFIR[11] - * LSI Source ID Register Parity Error Fatal Error - */ - (NpuFir, bit(11)) ? defaultMaskedError; - - /** NPUFIR[12] - * Interrupt Represent Timer Register Parity Error Fatal Error - */ - (NpuFir, bit(12)) ? defaultMaskedError; - - /** NPUFIR[13] - * IODA Address Register Parity Error Fatal Error - */ - (NpuFir, bit(13)) ? defaultMaskedError; - - /** NPUFIR[14] - * NPU Control Register Parity Error Fatal Error - */ - (NpuFir, bit(14)) ? defaultMaskedError; - - /** NPUFIR[15] - * NPU Timeout Control Register Parity Error Fatal Error - */ - (NpuFir, bit(15)) ? defaultMaskedError; - - /** NPUFIR[16] - * Invalid IODA Table Select Error Fatal Error - */ - (NpuFir, bit(16)) ? defaultMaskedError; - - /** NPUFIR[17] - * Invalid MMIO Address Decode Fatal Error - */ - (NpuFir, bit(17)) ? defaultMaskedError; - - /** NPUFIR[18] - * TCE Fetch Address Error Single PE - */ - (NpuFir, bit(18)) ? defaultMaskedError; - - /** NPUFIR[19] - * TCE tree walk CE error Informational - */ - (NpuFir, bit(19)) ? calloutSelfMedTh32NoGard; - - /** NPUFIR[20] - * Spare FIR Unused - */ - (NpuFir, bit(20)) ? defaultMaskedError; - - /** NPUFIR[21] - * MMIO/scom register error - */ - (NpuFir, bit(21)) ? defaultMaskedError; - - /** NPUFIR[22] - * NTL Array CE Informational - */ - (NpuFir, bit(22)) ? calloutSelfMedTh32NoGard; - - /** NPUFIR[23] - * NTL Array UE Fatal Error - */ - (NpuFir, bit(23)) ? defaultMaskedError; - - /** NPUFIR[24] - * DMA Timeout Fatal Error - */ - (NpuFir, bit(24)) ? defaultMaskedError; - - /** NPUFIR[25] - * NTL Control Error Fatal Error - */ - (NpuFir, bit(25)) ? defaultMaskedError; - - /** NPUFIR[26] - * Invalid FLIT Received Fatal Error - */ - (NpuFir, bit(26)) ? defaultMaskedError; - - /** NPUFIR[27] - * DL/TL Interface Parity Error - */ - (NpuFir, bit(27)) ? defaultMaskedError; - - /** NPUFIR[28] - * TL Credit Error Fatal Error - */ - (NpuFir, bit(28)) ? defaultMaskedError; - - /** NPUFIR[29] - * TL Packet Overflow Fatal Error - */ - (NpuFir, bit(29)) ? defaultMaskedError; - - /** NPUFIR[30] - * LMD Poison Single PE - */ - (NpuFir, bit(30)) ? defaultMaskedError; - - /** NPUFIR[31] - * LMD Stomp/CRC Error - */ - (NpuFir, bit(31)) ? thresholdAndMask_self; - - /** NPUFIR[32] - * CQ Parity Error Fatal Error - */ - (NpuFir, bit(32)) ? defaultMaskedError; - - /** NPUFIR[33] - * PowerBus Data Array CE Informational - */ - (NpuFir, bit(33)) ? calloutSelfMedTh32NoGard; - - /** NPUFIR[34] - * PowerBus Data Array UE Fatal Error - */ - (NpuFir, bit(34)) ? defaultMaskedError; - - /** NPUFIR[35] - * PowerBus Data Array SUE Fatal Error - */ - (NpuFir, bit(35)) ? defaultMaskedError; - - /** NPUFIR[36] - * CQ ECC CE Informational - */ - (NpuFir, bit(36)) ? calloutSelfMedTh32NoGard; - - /** NPUFIR[37] - * CQ ECC UE Fatal Error - */ - (NpuFir, bit(37)) ? defaultMaskedError; - - /** NPUFIR[38] - * PowerBus Data Hang Fatal Error - */ - (NpuFir, bit(38)) ? defaultMaskedError; - - /** NPUFIR[39] - * PowerBus Command Hang Fatal Error - */ - (NpuFir, bit(39)) ? defaultMaskedError; - - /** NPUFIR[40] - * Address Error on Read - */ - (NpuFir, bit(40)) ? defaultMaskedError; - - /** NPUFIR[41] - * PB Address Error non-Read Fatal Error - */ - (NpuFir, bit(41)) ? defaultMaskedError; - - /** NPUFIR[42] - * PowerBus Protocol Error Fatal Error - */ - (NpuFir, bit(42)) ? defaultMaskedError; - - /** NPUFIR[43] - * Register Parity Error Fatal Error - */ - (NpuFir, bit(43)) ? defaultMaskedError; - - /** NPUFIR[44] - * Unused ECC Error Unused - */ - (NpuFir, bit(44)) ? defaultMaskedError; - - /** NPUFIR[45] - * Unused Link Error Unused - */ - (NpuFir, bit(45)) ? defaultMaskedError; - - /** NPUFIR[46] - * Unused Link Error Unused - */ - (NpuFir, bit(46)) ? defaultMaskedError; - - /** NPUFIR[47] - * Unused Link Abort Unused - */ - (NpuFir, bit(47)) ? defaultMaskedError; - - /** NPUFIR[48] - * CQ/NTL Interface Hang Fatal Error - */ - (NpuFir, bit(48)) ? defaultMaskedError; - - /** NPUFIR[49] - * Unused Secure Access Error Unused - */ - (NpuFir, bit(49)) ? defaultMaskedError; - - /** NPUFIR[50] - * Scom Error Fatal Error - */ - (NpuFir, bit(50)) ? defaultMaskedError; - - /** NPUFIR[51] - * CQ spare Unused - */ - (NpuFir, bit(51)) ? defaultMaskedError; - - /** NPUFIR[52] - * Spare FIR Unused - */ - (NpuFir, bit(52)) ? defaultMaskedError; - - /** NPUFIR[53] - * Spare FIR Unused - */ - (NpuFir, bit(53)) ? defaultMaskedError; - - /** NPUFIR[54] - * NDL FIR 0 Single PE - */ - (NpuFir, bit(54)) ? defaultMaskedError; - - /** NPUFIR[55] - * NDL FIR 1 Single PE - */ - (NpuFir, bit(55)) ? defaultMaskedError; - - /** NPUFIR[56] - * Scom Fir Error Fatal Error - */ - (NpuFir, bit(56)) ? defaultMaskedError; - - /** NPUFIR[57] - * Scom Fir Error 2 Fatal Error - */ - (NpuFir, bit(57)) ? defaultMaskedError; - - /** NPUFIR[58:63] - * Reserved Unused - */ - (NpuFir, bit(58|59|60|61|62|63)) ? defaultMaskedError; -}; - -################################################################################ -# Actions specific to NV chiplet -################################################################################ - -/** Callout Self, threshold 32 per day, no garding. */ -actionclass calloutSelfMedTh32NoGard -{ - calloutSelfMedNoGard; - threshold32pday; -}; diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PB.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PB.rule deleted file mode 100755 index 51ef371bc..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PB.rule +++ /dev/null @@ -1,3776 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PB.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -################################################################################ -# PB Chiplet Registers -################################################################################ - -rule PbChipletFir -{ - CHECK_STOP: - (PB_CHIPLET_CS_FIR & `1FDFFE0000000000`) & ~PB_CHIPLET_FIR_MASK; - RECOVERABLE: - ((PB_CHIPLET_RE_FIR >> 2 ) & `1FDFFE0000000000`) & ~PB_CHIPLET_FIR_MASK; -}; - -group gPbChipletFir filter singlebit -{ - /** PB_CHIPLET_FIR[3] - * Attention from LFIR - */ - (PbChipletFir, bit(3)) ? analyze(gPbLFir); - - /** PB_CHIPLET_FIR[4] - * Attention from NXDMAENGFIR - */ - (PbChipletFir, bit(4)) ? analyze(gNxDmaEngFir); - - /** PB_CHIPLET_FIR[5] - * Attention from NXCQFIR - */ - (PbChipletFir, bit(5)) ? analyze(gNxCqFir); - - /** PB_CHIPLET_FIR[6] - * Attention from MCDFIR - */ - (PbChipletFir, bit(6)) ? analyze(gMcdFir); - - /** PB_CHIPLET_FIR[7|9] - * Attention from PBWESTFIR or PBEASTFIR - */ - (PbChipletFir, bit(7|9)) ? analyze(gPbWestEastFir); - - /** PB_CHIPLET_FIR[8] - * Attention from PBCENTFIR - */ - (PbChipletFir, bit(8)) ? analyze(gPbCentFir); - - /** PB_CHIPLET_FIR[11] - * Attention from PSIHBFIR - */ - (PbChipletFir, bit(11)) ? analyze(gPsiHbFir); - - /** PB_CHIPLET_FIR[12] - * Attention from ICPFIR - */ - (PbChipletFir, bit(12)) ? analyze(gIcpFir); - - /** PB_CHIPLET_FIR[13] - * Attention from PBAFIR - */ - (PbChipletFir, bit(13)) ? analyze(gPbaFir); - - /** PB_CHIPLET_FIR[14] - * Attention from EHHCAFIR - */ - (PbChipletFir, bit(14)) ? analyze(gEhHcaFir); - - /** PB_CHIPLET_FIR[15] - * Attention from NXASFIR - */ - (PbChipletFir, bit(15)) ? defaultMaskedError; - - /** PB_CHIPLET_FIR[16] - * Attention from ENHCAFIR - */ - (PbChipletFir, bit(16)) ? analyze(gEnHcaFir); - - /** PB_CHIPLET_FIR[17|18|19] - * Attention from PCINESTFIRs - */ - (PbChipletFir, bit(17|18|19)) ? analyze(gPciNestFir); - - /** PB_CHIPLET_FIR[20] - * Attention from NXCXAFIR_0 - */ - (PbChipletFir, bit(20)) ? analyze(gNxCxaFir_0); - - # It would be nice to include this in the above PCINESTFIRs, however since - # this bit only exists on naples, an attention from bits 17-19 would cause - # us to also try to read PciNestFir3 which would fail on non-naples chips. - /** PB_CHIPLET_FIR[21] - * Attention from PCINESTFIR3 - */ - (PbChipletFir, bit(21)) ? analyze(gPciNestFir3); - - /** PB_CHIPLET_FIR[22] - * Attention from NXCXAFIR_1 - */ - (PbChipletFir, bit(22)) ? analyze(gNxCxaFir_1); -}; - -rule PbChipletSpa -{ - SPECIAL: PB_CHIPLET_SPA & ~PB_CHIPLET_SPA_MASK; -}; - -group gPbChipletSpa filter singlebit -{ - /** PB_CHIPLET_SPA[0] - * Attention from PBCENTFIR - */ - (PbChipletSpa, bit(0)) ? analyze(gPbCentFir); -}; - -################################################################################ -# PB Chiplet LFIR -################################################################################ - -rule PbLFir -{ - CHECK_STOP: PB_LFIR & ~PB_LFIR_MASK & ~PB_LFIR_ACT0 & ~PB_LFIR_ACT1; - RECOVERABLE: PB_LFIR & ~PB_LFIR_MASK & ~PB_LFIR_ACT0 & PB_LFIR_ACT1; -}; - -group gPbLFir filter singlebit -{ - /** PB_LFIR[0] - * CFIR internal parity error - */ - (PbLFir, bit(0)) ? SelfHighThr32PerDay; - - /** PB_LFIR[1] - * Local errors from GPIO (PCB error) - */ - (PbLFir, bit(1)) ? defaultMaskedError; - - /** PB_LFIR[2] - * Local errors from CC (PCB error) - */ - (PbLFir, bit(2)) ? defaultMaskedError; - - /** PB_LFIR[3] - * Local errors from CC (OPCG, parity, scan collision, ...) - */ - (PbLFir, bit(3)) ? SelfHighThr32PerDay; - - /** PB_LFIR[4] - * Local errors from PSC (PCB error) - */ - (PbLFir, bit(4)) ? defaultMaskedError; - - /** PB_LFIR[5] - * Local errors from PSC (parity error) - */ - (PbLFir, bit(5)) ? defaultMaskedError; - - /** PB_LFIR[6] - * Local errors from Thermal (parity error) - */ - (PbLFir, bit(6)) ? defaultMaskedError; - - /** PB_LFIR[7] - * Local errors from Thermal (PCB error) - */ - (PbLFir, bit(7)) ? defaultMaskedError; - - /** PB_LFIR[8|9] - * Local errors from Thermal (Trip error) - */ - (PbLFir, bit(8|9)) ? defaultMaskedError; - - /** PB_LFIR[10] - * Local errors from Trace Array ( error) - */ - (PbLFir, bit(10)) ? SelfHighThr32PerDay; - - /** PB_LFIR[11] - * Local errors from Trace Array ( error) - */ - (PbLFir, bit(11)) ? defaultMaskedError; - - /** PB_LFIR[12:15] - * Local errors from io sense - */ - (PbLFir, bit(12|13|14|15)) ? defaultMaskedError; - - /** PB_LFIR[16] - * Fast check stop fir - */ - (PbLFir, bit(16)) ? defaultMaskedError; - - /** PB_LFIR[17:20] - * Unused local errors - */ - (PbLFir, bit(17|18|19|20)) ? defaultMaskedError; - - /** PB_LFIR[21:30] - * Unused local errors - */ - (PbLFir, bit(21|22|23|24|25|26|27|28|29|30)) ? defaultMaskedError; - - /** PB_LFIR[31:39] - * Unused local errors - */ - (PbLFir, bit(31|32|33|34|35|36|37|38|39)) ? defaultMaskedError; - - /** PB_LFIR[40] - * Malfunction alert - local checkstop in another chiplet - */ - (PbLFir, bit(40)) ? defaultMaskedError; - -}; - -################################################################################ -# PB Chiplet NXDMAENGFIR -################################################################################ - -# p8dd1_mss_FFDC_73_final.xls - -rule NxDmaEngFir -{ - CHECK_STOP: - NXDMAENGFIR & ~NXDMAENGFIR_MASK & ~NXDMAENGFIR_ACT0 & ~NXDMAENGFIR_ACT1; - RECOVERABLE: - NXDMAENGFIR & ~NXDMAENGFIR_MASK & ~NXDMAENGFIR_ACT0 & NXDMAENGFIR_ACT1; -}; - -group gNxDmaEngFir filter singlebit -{ - /** NXDMAENGFIR[0] - * Reserved - */ - (NxDmaEngFir, bit(0)) ? defaultMaskedError; - - /** NXDMAENGFIR[1] - * ICS invalid state error FIR bit - */ - (NxDmaEngFir, bit(1)) ? calloutNxThr1; - - /** NXDMAENGFIR[2|3] - * Reserved - */ - (NxDmaEngFir, bit(2|3)) ? defaultMaskedError; - - /** NXDMAENGFIR[4] - * Channel 0 842 array corrected ECC error - */ - (NxDmaEngFir, bit(4)) ? calloutNxThr32; - - /** NXDMAENGFIR[5] - * Channel 0 842 array uncorrectable ECC error - */ - (NxDmaEngFir, bit(5)) ? calloutNxThr1; - - /** NXDMAENGFIR[6] - * Channel 1 842 array corrected ECC error - */ - (NxDmaEngFir, bit(6)) ? calloutNxThr32; - - /** NXDMAENGFIR[7] - * Channel 1 842 array uncorrectable ECC error - */ - (NxDmaEngFir, bit(7)) ? calloutNxThr1; - - /** NXDMAENGFIR[8] - * DMA non-zero CSB CC detected - */ - (NxDmaEngFir, bit(8)) ? defaultMaskedError; - - /** NXDMAENGFIR[9] - * DMA array correctable ECC error - */ - (NxDmaEngFir, bit(9)) ? calloutNxThr32; - - /** NXDMAENGFIR[10] - * DMA outbound write/inbound read correctable ECC error - */ - (NxDmaEngFir, bit(10)) ? calloutNxThr32; - - /** NXDMAENGFIR[11] - * Channel 5 AMF array corrected ECC error - */ - (NxDmaEngFir, bit(11)) ? calloutNxThr32; # masked in Naples - - /** NXDMAENGFIR[12] - * Channel 6 AMF array corrected ECC error - */ - (NxDmaEngFir, bit(12)) ? calloutNxThr32; # masked in Naples - - /** NXDMAENGFIR[13] - * Channel 7 AMF array corrected ECC error - */ - (NxDmaEngFir, bit(13)) ? calloutNxThr32; # masked in Naples - - /** NXDMAENGFIR[14] - * Error from other SCOM satellites - */ - (NxDmaEngFir, bit(14)) ? defaultMaskedError; - - /** NXDMAENGFIR[15] - * DMA invalid state error - */ - (NxDmaEngFir, bit(15)) ? calloutNxThr1; - - /** NXDMAENGFIR[16] - * DMA invalid state error - */ - (NxDmaEngFir, bit(16)) ? calloutNxThr1; - - /** NXDMAENGFIR[17] - * DMA array uncorrectable ECC error - */ - (NxDmaEngFir, bit(17)) ? calloutNxThr1; - - /** NXDMAENGFIR[18] - * DMA outbound write/inbound read uncorrectable ECC error - */ - (NxDmaEngFir, bit(18)) ? calloutNxThr1; - - /** NXDMAENGFIR[19] - * DMA inbound read error - */ - (NxDmaEngFir, bit(19)) ? calloutNxThr1; - - /** NXDMAENGFIR[20] - * Channel 0 invalid state error - */ - (NxDmaEngFir, bit(20)) ? calloutNxThr1; - - /** NXDMAENGFIR[21] - * Channel 1 invalid state error - */ - (NxDmaEngFir, bit(21)) ? calloutNxThr1; - - /** NXDMAENGFIR[22] - * Channel 2 invalid state error - */ - (NxDmaEngFir, bit(22)) ? calloutNxThr1; - - /** NXDMAENGFIR[23] - * Channel 3 invalid state error - */ - (NxDmaEngFir, bit(23)) ? calloutNxThr1; - - /** NXDMAENGFIR[24] - * Channel 4 invalid state error - */ - (NxDmaEngFir, bit(24)) ? calloutNxThr1; # masked in Naples - - /** NXDMAENGFIR[25] - * Channel 5 invalid state error - */ - (NxDmaEngFir, bit(25)) ? calloutNxThr1; # masked in Naples - - /** NXDMAENGFIR[26] - * Channel 6 invalid state error - */ - (NxDmaEngFir, bit(26)) ? calloutNxThr1; # masked in Naples - - /** NXDMAENGFIR[27] - * Channel 7 invalid state error - */ - (NxDmaEngFir, bit(27)) ? calloutNxThr1; # masked in Naples - - /** NXDMAENGFIR[28] - * Channel 5 AMF array uncorrectable ECC error - */ - (NxDmaEngFir, bit(28)) ? calloutNxThr1; # masked in Naples - - /** NXDMAENGFIR[29] - * Channel 6 AMF array uncorrectable ECC error - */ - (NxDmaEngFir, bit(29)) ? calloutNxThr1; # masked in Naples - - /** NXDMAENGFIR[30] - * Channel 7 AMF array uncorrectable ECC error - */ - (NxDmaEngFir, bit(30)) ? calloutNxThr1; # masked in Naples - - /** NXDMAENGFIR[31] - * UE error on CRB(CSB address, CCB) - */ - (NxDmaEngFir, bit(31)) ? calloutNxThr1; - - /** NXDMAENGFIR[32] - * SUE error on CRB(CSB address, CCB) - */ - (NxDmaEngFir, bit(32)) ? calloutNxThr1; - - /** NXDMAENGFIR[33] - * SUE error on something other than CRB(CSB address, CCB) - */ - (NxDmaEngFir, bit(33)) ? defaultMaskedError; - - /** NXDMAENGFIR[34|35] - * Reserved - */ - (NxDmaEngFir, bit(34|35)) ? defaultMaskedError; - - /** NXDMAENGFIR[36] - * Channel 4 AMF array corrected ECC error - */ - (NxDmaEngFir, bit(36)) ? calloutNxThr32; # masked in Naples - - /** NXDMAENGFIR[37] - * Channel 4 AMF array uncorrectable ECC error - */ - (NxDmaEngFir, bit(37)) ? calloutNxThr1; # masked in Naples - - /** NXDMAENGFIR[38] - * NX Unit Checkstop - */ - # This is not a hardware attention. Instead, this bit is set manually by the - # hypervisor to communicate to PRD that it handled an NX freeze. - (NxDmaEngFir, bit(38)) ? nxUnitCheckstop; - - /** NXDMAENGFIR[39|40|41|42|43|44|45|46|47] - * Reserved - */ - (NxDmaEngFir, bit(39|40|41|42|43|44|45|46|47)) ? defaultMaskedError; - - /** NXDMAENGFIR[48] - * FIR/SCOM satellite parity error - */ - (NxDmaEngFir, bit(48)) ? defaultMaskedError; - - /** NXDMAENGFIR[49] - * FIR/SCOM satellite parity error FIR bit duplicate - */ - (NxDmaEngFir, bit(49)) ? defaultMaskedError; -}; - -################################################################################ -# PB Chiplet NXCQFIR -################################################################################ - -# p8dd1_mss_FFDC_73_final.xls - -rule NxCqFir -{ - CHECK_STOP: NXCQFIR & ~NXCQFIR_MASK & ~NXCQFIR_ACT0 & ~NXCQFIR_ACT1; - RECOVERABLE: NXCQFIR & ~NXCQFIR_MASK & ~NXCQFIR_ACT0 & NXCQFIR_ACT1; -}; - -group gNxCqFir filter singlebit -{ - /** NXCQFIR[0] - * PBI internal parity error - */ - (NxCqFir, bit(0)) ? calloutNxThr1; - - /** NXCQFIR[1] - * PowerBus CE error - */ - (NxCqFir, bit(1)) ? calloutNxThr5pHr; - - /** NXCQFIR[2] - * PowerBus UE error - */ - (NxCqFir, bit(2)) ? calloutNxThr1; - - /** NXCQFIR[3] - * PowerBus SUE error - */ - (NxCqFir, bit(3)) ? defaultMaskedError; - - /** NXCQFIR[4] - * Inbound array CE error - */ - (NxCqFir, bit(4)) ? calloutNxThr5pHr; - - /** NXCQFIR[5] - * Inbound array UE error - */ - (NxCqFir, bit(5)) ? calloutNxThr1; - - /** NXCQFIR[6] - * PowerBus data hang error - */ - (NxCqFir, bit(6)) ? callout2ndLvlMedThr1; - - /** NXCQFIR[7] - * PowerBus command hang error - */ - (NxCqFir, bit(7)) ? defaultMaskedError; - - /** NXCQFIR[8] - * PowerBus read address error - */ - (NxCqFir, bit(8)) ? calloutNxThr1; - - /** NXCQFIR[9] - * PowerBus write address error - */ - (NxCqFir, bit(9)) ? calloutNxThr1; - - /** NXCQFIR[10] - * PowerBus miscellaneous error - */ - (NxCqFir, bit(10)) ? callout2ndLvlMedThr1; - - /** NXCQFIR[11] - * MMIO BAR parity error - */ - (NxCqFir, bit(11)) ? calloutNxThr1; - - /** NXCQFIR[12] - * CRB kill ISN received while holding ISN with UE error - */ - (NxCqFir, bit(12)) ? calloutNxThr1; - - /** NXCQFIR[13] - * ACK_DEAD cresp received by read command - */ - (NxCqFir, bit(13)) ? calloutNxThr1; - - /** NXCQFIR[14] - * ACK_DEAD cresp received by write command - */ - (NxCqFir, bit(14)) ? calloutNxThr1; - - /** NXCQFIR[15] - * Link check aborted while waiting on data - */ - (NxCqFir, bit(15)) ? calloutNxThr1; - - /** NXCQFIR[16] - * Hang poll time expired on internal transfer - */ - (NxCqFir, bit(16)) ? calloutNxThr1; - - /** NXCQFIR[17] - * A write occurred to a secure register when it wasn't enabled - */ - (NxCqFir, bit(17)) ? defaultMaskedError; - - /** NXCQFIR[18] - * FIR/SCOM satellite parity error - */ - (NxCqFir, bit(18)) ? defaultMaskedError; - -}; - -################################################################################ -# PB Chiplet NXCXAFIR_0 -################################################################################ - -# p8dd1_mss_FFDC_73_final.xls - -rule NxCxaFir_0 -{ - CHECK_STOP: - NXCXAFIR_0 & ~NXCXAFIR_0_MASK & ~NXCXAFIR_0_ACT0 & ~NXCXAFIR_0_ACT1; - RECOVERABLE: - NXCXAFIR_0 & ~NXCXAFIR_0_MASK & ~NXCXAFIR_0_ACT0 & NXCXAFIR_0_ACT1; -}; - -group gNxCxaFir_0 filter singlebit -{ - /** NXCXAFIR_0[0] - * BAR_PE - */ - (NxCxaFir_0, bit(0)) ? defaultMaskedError; - - /** NXCXAFIR_0[1] - * REGISTER_PE - */ - (NxCxaFir_0, bit(1)) ? Capp0MedThr1; - - /** NXCXAFIR_0[2] - * MASTER_ARRAY_CE - */ - (NxCxaFir_0, bit(2)) ? Capp0MedThr32PerDay; - - /** NXCXAFIR_0[3] - * MASTER_ARRAY_UE - */ - (NxCxaFir_0, bit(3)) ? Capp0MedThr1; - - /** NXCXAFIR_0[4] - * TIMER_EXPIRED_RECOV_ERROR - */ - (NxCxaFir_0, bit(4)) ? defaultMaskedError; - - /** NXCXAFIR_0[5] - * TIMER_EXPIRED_XSTOP_ERROR - */ - (NxCxaFir_0, bit(5)) ? Capp0MedThr1; - - /** NXCXAFIR_0[6] - * PSL_CMD_UE - */ - (NxCxaFir_0, bit(6)) ? defaultMaskedError; - - /** NXCXAFIR_0[7] - * PSL_CMD_SUE - */ - (NxCxaFir_0, bit(7)) ? defaultMaskedError; - - /** NXCXAFIR_0[8] - * SNOOP_ARRAY_CE - */ - (NxCxaFir_0, bit(8)) ? callout2ndLvlMedThr32; - - /** NXCXAFIR_0[9] - * SNOOP_ARRAY_UE - */ - (NxCxaFir_0, bit(9)) ? Capp0MedThr1; - - /** NXCXAFIR_0[10] - * RECOVERY_FAILED - */ - (NxCxaFir_0, bit(10)) ? Capp0MedThr1; - - /** NXCXAFIR_0[11] - * ILLEGAL_LPC_BAR_ACCESS - */ - (NxCxaFir_0, bit(11)) ? defaultMaskedError; - - /** NXCXAFIR_0[12] - * XPT_RECOVERABLE_ERROR_MASK - */ - (NxCxaFir_0, bit(12)) ? defaultMaskedError; - - /** NXCXAFIR_0[13] - * MASTER_RECOVERABLE_ERROR - */ - (NxCxaFir_0, bit(13)) ? defaultMaskedError; - - /** NXCXAFIR_0[14] - * SNOOPER_RECOVERABLE_ERROR - */ - (NxCxaFir_0, bit(14)) ? defaultMaskedError; - - /** NXCXAFIR_0[15] - * XPT_RECOVERABLE_ERROR - */ - (NxCxaFir_0, bit(15)) ? defaultMaskedError; - - /** NXCXAFIR_0[16] - * MASTER_SYS_XSTOP_ERROR - */ - (NxCxaFir_0, bit(16)) ? Capp0MedThr1; - - /** NXCXAFIR_0[17] - * SNOOPER_SYS_XSTOP_ERROR - */ - (NxCxaFir_0, bit(17)) ? Capp0MedThr1; - - /** NXCXAFIR_0[18] - * XPT_SYS_XSTOP_ERROR - */ - (NxCxaFir_0, bit(18)) ? Capp0MedThr1; - - /** NXCXAFIR_0[19] - * MUOP_ERROR_1 - */ - (NxCxaFir_0, bit(19)) ? defaultMaskedError; - - /** NXCXAFIR_0[20] - * MUOP_ERROR_2 - */ - (NxCxaFir_0, bit(20)) ? defaultMaskedError; - - /** NXCXAFIR_0[21] - * MUOP_ERROR_3 - */ - (NxCxaFir_0, bit(21)) ? defaultMaskedError; - - /** NXCXAFIR_0[22] - * SUOP_ERROR_1 - */ - (NxCxaFir_0, bit(22)) ? defaultMaskedError; - - /** NXCXAFIR_0[23] - * SUOP_ERROR_2 - */ - (NxCxaFir_0, bit(23)) ? defaultMaskedError; - - /** NXCXAFIR_0[24] - * SUOP_ERROR_3 - */ - (NxCxaFir_0, bit(24)) ? defaultMaskedError; - - /** NXCXAFIR_0[25] - * POWERBUS_MISC_ERROR - */ - (NxCxaFir_0, bit(25)) ? SelfHighThr1; - - /** NXCXAFIR_0[26] - * POWERBUS_INTERFACE_PE - */ - (NxCxaFir_0, bit(26)) ? SelfHighThr1; - - /** NXCXAFIR_0[27] - *POWERBUS_DATA_HANG_ERROR - */ - (NxCxaFir_0, bit(27)) ? defaultMaskedError; - - /** NXCXAFIR_0[28] - * POWERBUS_HANG_ERROR - */ - (NxCxaFir_0, bit(28)) ? defaultMaskedError; - - /** NXCXAFIR_0[29] - * LD_CLASS_CMD_ADDR_ERR - */ - (NxCxaFir_0, bit(29)) ? callout2ndLvlMedThr1; - - /** NXCXAFIR_0[30] - * ST_CLASS_CMD_ADDR_ERR - */ - (NxCxaFir_0, bit(30)) ? callout2ndLvlMedThr1; - - /** NXCXAFIR_0[31] - * PHB_LINK_DOWN - */ - (NxCxaFir_0, bit(31)) ? defaultMaskedError; - - /** NXCXAFIR_0[32] - * LD_CLASS_CMD_FOREIGN_LINK_FAIL - */ - (NxCxaFir_0, bit(32)) ? defaultMaskedError; - - /** NXCXAFIR_0[33] - * FOREIGN_LINK_HANG_ERROR - */ - (NxCxaFir_0, bit(33)) ? defaultMaskedError; - - /** NXCXAFIR_0[34] - * XPT_POWERBUS_CE - */ - (NxCxaFir_0, bit(34)) ? callout2ndLvlMedThr32; - - /** NXCXAFIR_0[35] - * XPT_POWERBUS_UE - */ - (NxCxaFir_0, bit(35)) ? defaultMaskedError; - - /** NXCXAFIR_0[36] - * XPT_POWERBUS_SUE - */ - (NxCxaFir_0, bit(36)) ? defaultMaskedError; - - /** NXCXAFIR_0[37] - * TLBI_TIMEOUT - */ - (NxCxaFir_0, bit(37)) ? defaultMaskedError; - - /** NXCXAFIR_0[38] - * TLBI_SEQ_ERR - */ - (NxCxaFir_0, bit(38)) ? SelfHighThr1; - - /** NXCXAFIR_0[39] - * TLBI_BAD_OP_ERR - */ - (NxCxaFir_0, bit(39)) ? SelfHighThr1; - - /** NXCXAFIR_0[40] - * TLBI_SEQ_NUM_PARITY_ERR - */ - (NxCxaFir_0, bit(40)) ? SelfHighThr1; - - /** NXCXAFIR_0[41] - * ST_CLASS_CMD_FOREIGN_LINK_FAIL - */ - (NxCxaFir_0, bit(41)) ? defaultMaskedError; - - /** NXCXAFIR_0[42] - * TIMEBASE_ERR - */ - (NxCxaFir_0, bit(42)) ? defaultMaskedError; - - /** NXCXAFIR_0[43] - * XPT_INFORMATIONAL_ERR - */ - (NxCxaFir_0, bit(43)) ? defaultMaskedError; - - /** NXCXAFIR_0[44] - * COMMAND_QUEUE_CE - */ - (NxCxaFir_0, bit(44)) ? defaultMaskedError; # Naples only - - /** NXCXAFIR_0[45] - * COMMAND_QUEUE_UE - */ - (NxCxaFir_0, bit(45)) ? defaultMaskedError; # Naples only - - /** NXCXAFIR_0[46] - * PSL_CREDIT_TIMEOUT - */ - (NxCxaFir_0, bit(46)) ? defaultMaskedError; - - /** NXCXAFIR_0[47|48] - * Spare - */ - (NxCxaFir_0, bit(47|48)) ? defaultMaskedError; - - /** NXCXAFIR_0[49] - * SCOM_ERR2: Local FIR Parity Error RAS Duplicate - */ - (NxCxaFir_0, bit(49)) ? defaultMaskedError; - - /** NXCXAFIR_0[50] - * SCOM_ERR: Local FIR Parity Error of ACTION/MASK registers - */ - (NxCxaFir_0, bit(50)) ? defaultMaskedError; -}; - -rule NxCxaFir_1 -{ - CHECK_STOP: - NXCXAFIR_1 & ~NXCXAFIR_1_MASK & ~NXCXAFIR_1_ACT0 & ~NXCXAFIR_1_ACT1; - RECOVERABLE: - NXCXAFIR_1 & ~NXCXAFIR_1_MASK & ~NXCXAFIR_1_ACT0 & NXCXAFIR_1_ACT1; -}; - -group gNxCxaFir_1 filter singlebit -{ - /** NXCXAFIR_1[0] - * BAR_PE - */ - (NxCxaFir_1, bit(0)) ? defaultMaskedError; - - /** NXCXAFIR_1[1] - * REGISTER_PE - */ - (NxCxaFir_1, bit(1)) ? Capp1MedThr1; - - /** NXCXAFIR_1[2] - * MASTER_ARRAY_CE - */ - (NxCxaFir_1, bit(2)) ? Capp1MedThr32PerDay; - - /** NXCXAFIR_1[3] - * MASTER_ARRAY_UE - */ - (NxCxaFir_1, bit(3)) ? Capp1MedThr1; - - /** NXCXAFIR_1[4] - * TIMER_EXPIRED_RECOV_ERROR - */ - (NxCxaFir_1, bit(4)) ? defaultMaskedError; - - /** NXCXAFIR_1[5] - * TIMER_EXPIRED_XSTOP_ERROR - */ - (NxCxaFir_1, bit(5)) ? Capp1MedThr1; - - /** NXCXAFIR_1[6] - * PSL_CMD_UE - */ - (NxCxaFir_1, bit(6)) ? defaultMaskedError; - - /** NXCXAFIR_1[7] - * PSL_CMD_SUE - */ - (NxCxaFir_1, bit(7)) ? defaultMaskedError; - - /** NXCXAFIR_1[8] - * SNOOP_ARRAY_CE - */ - (NxCxaFir_1, bit(8)) ? callout2ndLvlMedThr32; - - /** NXCXAFIR_1[9] - * SNOOP_ARRAY_UE - */ - (NxCxaFir_1, bit(9)) ? Capp1MedThr1; - - /** NXCXAFIR_1[10] - * RECOVERY_FAILED - */ - (NxCxaFir_1, bit(10)) ? Capp1MedThr1; - - /** NXCXAFIR_1[11] - * ILLEGAL_LPC_BAR_ACCESS - */ - (NxCxaFir_1, bit(11)) ? defaultMaskedError; - - /** NXCXAFIR_1[12] - * XPT_RECOVERABLE_ERROR_MASK - */ - (NxCxaFir_1, bit(12)) ? defaultMaskedError; - - /** NXCXAFIR_1[13] - * MASTER_RECOVERABLE_ERROR - */ - (NxCxaFir_1, bit(13)) ? defaultMaskedError; - - /** NXCXAFIR_1[14] - * SNOOPER_RECOVERABLE_ERROR - */ - (NxCxaFir_1, bit(14)) ? defaultMaskedError; - - /** NXCXAFIR_1[15] - * XPT_RECOVERABLE_ERROR - */ - (NxCxaFir_1, bit(15)) ? defaultMaskedError; - - /** NXCXAFIR_1[16] - * MASTER_SYS_XSTOP_ERROR - */ - (NxCxaFir_1, bit(16)) ? Capp1MedThr1; - - /** NXCXAFIR_1[17] - * SNOOPER_SYS_XSTOP_ERROR - */ - (NxCxaFir_1, bit(17)) ? Capp1MedThr1; - - /** NXCXAFIR_1[18] - * XPT_SYS_XSTOP_ERROR - */ - (NxCxaFir_1, bit(18)) ? Capp1MedThr1; - - /** NXCXAFIR_1[19] - * MUOP_ERROR_1 - */ - (NxCxaFir_1, bit(19)) ? defaultMaskedError; - - /** NXCXAFIR_1[20] - * MUOP_ERROR_2 - */ - (NxCxaFir_1, bit(20)) ? defaultMaskedError; - - /** NXCXAFIR_1[21] - * MUOP_ERROR_3 - */ - (NxCxaFir_1, bit(21)) ? defaultMaskedError; - - /** NXCXAFIR_1[22] - * SUOP_ERROR_1 - */ - (NxCxaFir_1, bit(22)) ? defaultMaskedError; - - /** NXCXAFIR_1[23] - * SUOP_ERROR_2 - */ - (NxCxaFir_1, bit(23)) ? defaultMaskedError; - - /** NXCXAFIR_1[24] - * SUOP_ERROR_3 - */ - (NxCxaFir_1, bit(24)) ? defaultMaskedError; - - /** NXCXAFIR_1[25] - * POWERBUS_MISC_ERROR - */ - (NxCxaFir_1, bit(25)) ? SelfHighThr1; - - /** NXCXAFIR_1[26] - * POWERBUS_INTERFACE_PE - */ - (NxCxaFir_1, bit(26)) ? SelfHighThr1; - - /** NXCXAFIR_1[27] - *POWERBUS_DATA_HANG_ERROR - */ - (NxCxaFir_1, bit(27)) ? defaultMaskedError; - - /** NXCXAFIR_1[28] - * POWERBUS_HANG_ERROR - */ - (NxCxaFir_1, bit(28)) ? defaultMaskedError; - - /** NXCXAFIR_1[29] - * LD_CLASS_CMD_ADDR_ERR - */ - (NxCxaFir_1, bit(29)) ? callout2ndLvlMedThr1; - - /** NXCXAFIR_1[30] - * ST_CLASS_CMD_ADDR_ERR - */ - (NxCxaFir_1, bit(30)) ? callout2ndLvlMedThr1; - - /** NXCXAFIR_1[31] - * PHB_LINK_DOWN - */ - (NxCxaFir_1, bit(31)) ? defaultMaskedError; - - /** NXCXAFIR_1[32] - * LD_CLASS_CMD_FOREIGN_LINK_FAIL - */ - (NxCxaFir_1, bit(32)) ? defaultMaskedError; - - /** NXCXAFIR_1[33] - * FOREIGN_LINK_HANG_ERROR - */ - (NxCxaFir_1, bit(33)) ? defaultMaskedError; - - /** NXCXAFIR_1[34] - * XPT_POWERBUS_CE - */ - (NxCxaFir_1, bit(34)) ? callout2ndLvlMedThr32; - - /** NXCXAFIR_1[35] - * XPT_POWERBUS_UE - */ - (NxCxaFir_1, bit(35)) ? defaultMaskedError; - - /** NXCXAFIR_1[36] - * XPT_POWERBUS_SUE - */ - (NxCxaFir_1, bit(36)) ? defaultMaskedError; - - /** NXCXAFIR_1[37] - * TLBI_TIMEOUT - */ - (NxCxaFir_1, bit(37)) ? defaultMaskedError; - - /** NXCXAFIR_1[38] - * TLBI_SEQ_ERR - */ - (NxCxaFir_1, bit(38)) ? SelfHighThr1; - - /** NXCXAFIR_1[39] - * TLBI_BAD_OP_ERR - */ - (NxCxaFir_1, bit(39)) ? SelfHighThr1; - - /** NXCXAFIR_1[40] - * TLBI_SEQ_NUM_PARITY_ERR - */ - (NxCxaFir_1, bit(40)) ? SelfHighThr1; - - /** NXCXAFIR_1[41] - * ST_CLASS_CMD_FOREIGN_LINK_FAIL - */ - (NxCxaFir_1, bit(41)) ? defaultMaskedError; - - /** NXCXAFIR_1[42] - * TIMEBASE_ERR - */ - (NxCxaFir_1, bit(42)) ? defaultMaskedError; - - /** NXCXAFIR_1[43] - * XPT_INFORMATIONAL_ERR - */ - (NxCxaFir_1, bit(43)) ? defaultMaskedError; - - /** NXCXAFIR_1[44] - * COMMAND_QUEUE_CE - */ - (NxCxaFir_1, bit(44)) ? defaultMaskedError; # Naples only - - /** NXCXAFIR_1[45] - * COMMAND_QUEUE_UE - */ - (NxCxaFir_1, bit(45)) ? defaultMaskedError; # Naples only - - /** NXCXAFIR_1[46] - * PSL_CREDIT_TIMEOUT - */ - (NxCxaFir_1, bit(46)) ? defaultMaskedError; - - /** NXCXAFIR_1[47|48] - * Spare - */ - (NxCxaFir_1, bit(47|48)) ? defaultMaskedError; - - /** NXCXAFIR_1[49] - * SCOM_ERR2: Local FIR Parity Error RAS Duplicate - */ - (NxCxaFir_1, bit(49)) ? defaultMaskedError; - - /** NXCXAFIR_1[50] - * SCOM_ERR: Local FIR Parity Error of ACTION/MASK registers - */ - (NxCxaFir_1, bit(50)) ? defaultMaskedError; -}; -################################################################################ -# PB Chiplet MCDFIR -################################################################################ -# based on p8dd1_mss_FFDC_59.xls -################################################################################ - -rule McdFir -{ - CHECK_STOP: MCDFIR & ~MCDFIR_MASK & ~MCDFIR_ACT0 & ~MCDFIR_ACT1; - RECOVERABLE: MCDFIR & ~MCDFIR_MASK & ~MCDFIR_ACT0 & MCDFIR_ACT1; -}; - -group gMcdFir filter singlebit -{ - /** MCDFIR[0] - * MCD_ARRAY_ECC_UE_ERR - */ - (McdFir, bit(0)) ? SelfHighThr32PerDay; - - /** MCDFIR[1] - * MCD_ARRAY_ECC_CE_ERR - */ - (McdFir, bit(1)) ? SelfHighThr32PerDay; - - /** MCDFIR[2] - * MCD_REG_PARITY_ERR - */ - (McdFir, bit(2)) ? defaultMaskedError; - - /** MCDFIR[3] - * MCD_SM_ERR - */ - (McdFir, bit(3)) ? calloutNxThr1; - - /** MCDFIR[4] - * MCD_REC_HANG_ERR - */ - (McdFir, bit(4)) ? defaultMaskedError; - - /** MCDFIR[5] - * MCD_PB_PARITY_ERR - */ - (McdFir, bit(5)) ? defaultMaskedError; - - /** MCDFIR[6] - * MCD_UNSOLICITED_CRESP_ERR - */ - (McdFir, bit(6)) ? defaultMaskedError; - - /** MCDFIR[7] - * MCD_ACK_DEAD_ERR - */ - (McdFir, bit(7)) ? defaultMaskedError; - - /** MCDFIR[8] - * FIR_PARITY_ERR2 - */ - (McdFir, bit(8)) ? defaultMaskedError; - - /** MCDFIR[9] - * FIR_PARITY_ERR - */ - (McdFir, bit(9)) ? defaultMaskedError; -}; - -################################################################################ -# PB Chiplet PBEASTFIR and PBWESTFIR -################################################################################ - -# All these FIRs should have the same bit definition. Ideally, we want -# to have only one copy of the bit definition. Currently rule code -# parser does not have the support for something like this. -# Maybe we can add this as a later feature. - -################################################################################ -# based on p8dd1_mss_FFDC_37_ reviewd.xls -################################################################################ - -rule PbEastFir -{ - CHECK_STOP: PBEASTFIR & ~PBEASTFIR_MASK & ~PBEASTFIR_ACT0 & ~PBEASTFIR_ACT1; - RECOVERABLE: PBEASTFIR & ~PBEASTFIR_MASK & ~PBEASTFIR_ACT0 & PBEASTFIR_ACT1; -}; - -rule PbWestFir -{ - CHECK_STOP: PBWESTFIR & ~PBWESTFIR_MASK & ~PBWESTFIR_ACT0 & ~PBWESTFIR_ACT1; - RECOVERABLE: PBWESTFIR & ~PBWESTFIR_MASK & ~PBWESTFIR_ACT0 & PBWESTFIR_ACT1; -}; - -group gPbWestEastFir filter singlebit -{ - /** PBWESTFIR[0] - * PB_WEST_PBIEX01_PBH_HW_ERROR - */ - (PbWestFir, bit(0)) ? SelfHighThr1; - - /** PBEASTFIR[0] - * PB_EAST_PBIEX04_PBH_HW_ERROR - */ - (PbEastFir, bit(0)) ? SelfHighThr1; - - /** PBWESTFIR[1] - * PB_WEST_PBIEX01_PBH_RECOV_ERROR - */ - (PbWestFir, bit(1)) ? SelfHighThr1; - - /** PBEASTFIR[1] - * PB_EAST_PBIEX04_PBH_RECOV_ERROR - */ - (PbEastFir, bit(1)) ? SelfHighThr1; - - /** PBWESTFIR[2] - * PB_WEST_PBIEX01_PBH_PROTOCOL_ERROR - */ - (PbWestFir, bit(2)) ? calloutProcLevel2MedThr1; - - /** PBEASTFIR[2] - * PB_EAST_PBIEX04_PBH_PROTOCOL_ERROR - */ - (PbEastFir, bit(2)) ? calloutProcLevel2MedThr1; - - /** PBWESTFIR[3] - * PB_WEST_PBIEX01_PBH_OVERFLOW_ERROR - */ - (PbWestFir, bit(3)) ? calloutProcLevel2MedThr1; - - /** PBEASTFIR[3] - * PB_EAST_PBIEX04_PBH_OVERFLOW_ERROR - */ - (PbEastFir, bit(3)) ? calloutProcLevel2MedThr1; - - /** PBWESTFIR[4] - * PB_WEST_PBIEX02_PBH_HW_ERROR - */ - (PbWestFir, bit(4)) ? SelfHighThr1; - - /** PBEASTFIR[4] - * PB_EAST_PBIEX05_PBH_HW_ERROR - */ - (PbEastFir, bit(4)) ? SelfHighThr1; - - /** PBWESTFIR[5] - * PB_WEST_PBIEX02_PBH_RECOV_ERROR - */ - (PbWestFir, bit(5)) ? SelfHighThr1; - - /** PBEASTFIR[5] - * PB_EAST_PBIEX05_PBH_RECOV_ERROR - */ - (PbEastFir, bit(5)) ? SelfHighThr1; - - /** PBWESTFIR[6] - * PB_WEST_PBIEX02_PBH_PROTOCOL_ERROR - */ - (PbWestFir, bit(6)) ? calloutProcLevel2MedThr1; - - /** PBEASTFIR[6] - * PB_EAST_PBIEX05_PBH_PROTOCOL_ERROR - */ - (PbEastFir, bit(6)) ? calloutProcLevel2MedThr1; - - /** PBWESTFIR[7] - * PB_WEST_PBIEX02_PBH_OVERFLOW_ERROR - */ - (PbWestFir, bit(7)) ? calloutProcLevel2MedThr1; - - /** PBEASTFIR[7] - * PB_EAST_PBIEX05_PBH_OVERFLOW_ERROR - */ - (PbEastFir, bit(7)) ? calloutProcLevel2MedThr1; - - /** PBWESTFIR[8] - * PB_WEST_PBIEX03_PBH_HW_ERROR - */ - (PbWestFir, bit(8)) ? SelfHighThr1; - - /** PBEASTFIR[8] - * PB_EAST_PBIEX06_PBH_HW_ERROR - */ - (PbEastFir, bit(8)) ? SelfHighThr1; - - /** PBWESTFIR[9] - * PB_WEST_PBIEX03_PBH_RECOV_ERROR - */ - (PbWestFir, bit(9)) ? SelfHighThr1; - - /** PBEASTFIR[9] - * PB_EAST_PBIEX06_PBH_RECOV_ERROR - */ - (PbEastFir, bit(9)) ? SelfHighThr1; - - /** PBWESTFIR[10] - * PB_WEST_PBIEX03_PBH_PROTOCOL_ERROR - */ - (PbWestFir, bit(10)) ? calloutProcLevel2MedThr1; - - /** PBEASTFIR[10] - * PB_EAST_PBIEX06_PBH_PROTOCOL_ERROR - */ - (PbEastFir, bit(10)) ? calloutProcLevel2MedThr1; - - /** PBWESTFIR[11] - * PB_WEST_PBIEX03_PBH_OVERFLOW_ERROR - */ - (PbWestFir, bit(11)) ? calloutProcLevel2MedThr1; - - /** PBEASTFIR[11] - * PB_EAST_PBIEX06_PBH_OVERFLOW_ERROR - */ - (PbEastFir, bit(11)) ? calloutProcLevel2MedThr1; - - /** PBWESTFIR[12] - * PB_WEST_PBIEX09_PBH_HW_ERROR - */ - (PbWestFir, bit(12)) ? SelfHighThr1; - - /** PBEASTFIR[12] - * PB_EAST_PBIEX12_PBH_HW_ERROR - */ - (PbEastFir, bit(12)) ? SelfHighThr1; - - /** PBWESTFIR[13] - * PB_WEST_PBIEX09_PBH_RECOV_ERROR - */ - (PbWestFir, bit(13)) ? SelfHighThr1; - - /** PBEASTFIR[13] - * PB_EAST_PBIEX12_PBH_RECOV_ERROR - */ - (PbEastFir, bit(13)) ? SelfHighThr1; - - /** PBWESTFIR[14] - * PB_WEST_PBIEX09_PBH_PROTOCOL_ERROR - */ - (PbWestFir, bit(14)) ? calloutProcLevel2MedThr1; - - /** PBEASTFIR[14] - * PB_EAST_PBIEX12_PBH_PROTOCOL_ERROR - */ - (PbEastFir, bit(14)) ? calloutProcLevel2MedThr1; - - /** PBWESTFIR[15] - * PB_WEST_PBIEX09_PBH_OVERFLOW_ERROR - */ - (PbWestFir, bit(15)) ? calloutProcLevel2MedThr1; - - /** PBEASTFIR[15] - * PB_EAST_PBIEX12_PBH_OVERFLOW_ERROR - */ - (PbEastFir, bit(15)) ? calloutProcLevel2MedThr1; - - /** PBWESTFIR[16] - * PB_WEST_PBIEX10_PBH_HW_ERROR - */ - (PbWestFir, bit(16)) ? SelfHighThr1; - - /** PBEASTFIR[16] - * PB_EAST_PBIEX13_PBH_HW_ERROR - */ - (PbEastFir, bit(16)) ? SelfHighThr1; - - /** PBWESTFIR[17] - * PB_WEST_PBIEX10_PBH_RECOV_ERROR - */ - (PbWestFir, bit(17)) ? SelfHighThr1; - - /** PBEASTFIR[17] - * PB_EAST_PBIEX13_PBH_RECOV_ERROR - */ - (PbEastFir, bit(17)) ? SelfHighThr1; - - /** PBWESTFIR[18] - * PB_WEST_PBIEX10_PBH_PROTOCOL_ERROR - */ - (PbWestFir, bit(18)) ? calloutProcLevel2MedThr1; - - /** PBEASTFIR[18] - * PB_EAST_PBIEX13_PBH_PROTOCOL_ERROR - */ - (PbEastFir, bit(18)) ? calloutProcLevel2MedThr1; - - /** PBWESTFIR[19] - * PB_WEST_PBIEX10_PBH_OVERFLOW_ERROR - */ - (PbWestFir, bit(19)) ? calloutProcLevel2MedThr1; - - /** PBEASTFIR[19] - * PB_EAST_PBIEX13_PBH_OVERFLOW_ERROR - */ - (PbEastFir, bit(19)) ? calloutProcLevel2MedThr1; - - /** PBWESTFIR[20] - * PB_WEST_PBIEX11_PBH_HW_ERROR - */ - (PbWestFir, bit(20)) ? SelfHighThr1; - - /** PBEASTFIR[20] - * PB_EAST_PBIEX14_PBH_HW_ERROR - */ - (PbEastFir, bit(20)) ? SelfHighThr1; - - /** PBWESTFIR[21] - * PB_WEST_PBIEX11_PBH_RECOV_ERROR - */ - (PbWestFir, bit(21)) ? SelfHighThr1; - - /** PBEASTFIR[21] - * PB_EAST_PBIEX14_PBH_RECOV_ERROR - */ - (PbEastFir, bit(21)) ? SelfHighThr1; - - /** PBWESTFIR[22] - * PB_WEST_PBIEX11_PBH_PROTOCOL_ERROR - */ - (PbWestFir, bit(22)) ? calloutProcLevel2MedThr1; - - /** PBEASTFIR[22] - * PB_EAST_PBIEX14_PBH_PROTOCOL_ERROR - */ - (PbEastFir, bit(22)) ? calloutProcLevel2MedThr1; - - /** PBWESTFIR[23] - * PB_WEST_PBIEX11_PBH_OVERFLOW_ERROR - */ - (PbWestFir, bit(23)) ? calloutProcLevel2MedThr1; - - /** PBEASTFIR[23] - * PB_EAST_PBIEX14_PBH_OVERFLOW_ERROR - */ - (PbEastFir, bit(23)) ? calloutProcLevel2MedThr1; - - /** PBWESTFIR[24] - * PB_WEST_DATA_OVERFLOW_ERROR - */ - (PbWestFir, bit(24)) ? calloutProcLevel2MedThr1; - - /** PBEASTFIR[24] - * PB_EAST_DATA_OVERFLOW_ERROR - */ - (PbEastFir, bit(24)) ? calloutProcLevel2MedThr1; - - /** PBWESTFIR[25] - * PB_WEST_DATA_PROTOCOL_ERROR - */ - (PbWestFir, bit(25)) ? calloutProcLevel2MedThr1; - - /** PBEASTFIR[25] - * PB_EAST_DATA_PROTOCOL_ERROR - */ - (PbEastFir, bit(25)) ? calloutProcLevel2MedThr1; - - /** PBWESTFIR[26] - * PB_WEST_DATA_ROUTE_ERROR - */ - (PbWestFir, bit(26)) ? calloutProcLevel2MedThr1; - - /** PBEASTFIR[26] - * PB_EAST_DATA_ROUTE_ERROR - */ - (PbEastFir, bit(26)) ? calloutProcLevel2MedThr1; - - /** PBWESTFIR[27] - * PB_WEST_CMD_OVERFLOW_ERROR - */ - (PbWestFir, bit(27)) ? calloutProcLevel2MedThr1; - - /** PBEASTFIR[27] - * PB_EAST_CMD_OVERFLOW_ERROR - */ - (PbEastFir, bit(27)) ? calloutProcLevel2MedThr1; - - /** PBWESTFIR[28] - * PB_WEST_CMD_OVERFLOW_ERROR - */ - (PbWestFir, bit(28)) ? calloutProcLevel2MedThr1; - - /** PBEASTFIR[28] - * PB_EAST_CMD_OVERFLOW_ERROR - */ - (PbEastFir, bit(28)) ? calloutProcLevel2MedThr1; - - /** PBWESTFIR[29|30|31] - * PB_WEST_FIR_SPARE_0,1 and 2 - */ - (PbWestFir, bit(29|30|31)) ? defaultMaskedError; - - /** PBEASTFIR[29|30] - * PB_EAST_FIR_SPARE - */ - (PbEastFir, bit(29|30)) ? defaultMaskedError; - - /** PBEASTFIR[31] - * SW initiated reboot with diagnostics - */ - # Intended to be used by OPAL to initiate a reboot if there is an issue like - # a memory UE that prevents OPAL to continue loading. Generally, PRD should - # be able to isolate to the memory UE and blame that as the root cause, - # however, it is possible there are no hardware errors and OPAL just needs - # to force a reboot. Therefore, the callout will be 2nd Level Support. It is - # possible that PRD may need to force memory diagnostics on all memory but - # that is not a requirement at this time. - (PbEastFir, bit(31)) ? callout2ndLvlMedThr1; - - /** PBWESTFIR[32] - * FIR_SCOM_WEST_ERR - */ - (PbWestFir, bit(32)) ? defaultMaskedError; - - /** PBEASTFIR[32] - * FIR_SCOM_EAST_ERR - */ - (PbEastFir, bit(32)) ? defaultMaskedError; - - /** PBWESTFIR[33] - * FIR_SCOM_WEST_ERR_DUP - */ - (PbWestFir, bit(33)) ? defaultMaskedError; - - /** PBEASTFIR[33] - * FIR_SCOM_EAST_ERR_DUP - */ - (PbEastFir, bit(33)) ? defaultMaskedError; -}; - -################################################################################ -# PB Chiplet PBCENTFIR -################################################################################ - -rule PbCentFir -{ - CHECK_STOP: PBCENTFIR & ~PBCENTFIR_MASK & ~PBCENTFIR_ACT0 & ~PBCENTFIR_ACT1; - RECOVERABLE: PBCENTFIR & ~PBCENTFIR_MASK & ~PBCENTFIR_ACT0 & PBCENTFIR_ACT1; - SPECIAL: PBCENTFIR & ~PBCENTFIR_MASK & PBCENTFIR_ACT0 & ~PBCENTFIR_ACT1; -}; - -group gPbCentFir filter singlebit, - secondarybits( 9 ) -{ - /** PBCENTFIR[0] - * PB_CENT_PROTOCOL_ERROR - */ - (PbCentFir, bit(0)) ? calloutProcLevel2MedThr1; - - /** PBCENTFIR[1] - * PB_CENT_OVERFLOW_ERROR - */ - (PbCentFir, bit(1)) ? calloutProcLevel2MedThr1; - - /** PBCENTFIR[2] - * PB_CENT_HW_PARITY_ERROR - */ - (PbCentFir, bit(2)) ? calloutProcLevel2MedThr1; - - /** PBCENTFIR[3] - * PB_CENT_TLBIE_TM_TIMEOUT_ERROR - */ - (PbCentFir, bit(3)) ? defaultMaskedError; - - /** PBCENTFIR[4] - * PB_CENT_COHERENCY_ERROR - */ - (PbCentFir, bit(4)) ? calloutProcLevel2MedThr1; - - /** PBCENTFIR[5] - * PB_CENT_CRESP_ADDR_ERROR - */ - (PbCentFir, bit(5)) ? combinedResponseError; - - /** PBCENTFIR[6] - * PB_CENT_CRESP_ERROR - */ - (PbCentFir, bit(6)) ? calloutProcLevel2MedThr1; - - /** PBCENTFIR[7] - * PB_CENT_HANG_RECOVERY_LIMIT_ERROR - */ - (PbCentFir, bit(7)) ? defaultMaskedError; - - /** PBCENTFIR[8] - * PB_CENT_DATA_ROUTE_ERROR - */ - (PbCentFir, bit(8)) ? calloutProcLevel2MedThr1; - - /** PBCENTFIR[9] - * PB_CENT_HANG_RECOVERY_GTE_LEVEL1 - */ - (PbCentFir, bit(9)) ? PbCentHangRecoveryGte; - - /** PBCENTFIR[10] - * PB_CENT_FORCE_MP_IPL - */ - (PbCentFir, bit(10)) ? forceMpIpl; - - /** PBCENTFIR[11] - * Programming Error - */ - (PbCentFir, bit(11)) ? calloutProcLevel2MedThr1; - - /** PBCENTFIR[12] - * PB_CENT_F0LINK_ERROR - */ - (PbCentFir, bit(12)) ? defaultMaskedError; - - /** PBCENTFIR[13] - * PB_CENT_F1LINK_ERROR - */ - (PbCentFir, bit(13)) ? defaultMaskedError; - - /** PBCENTFIR[14] - * PB_CENT_F0_OVERFLOW - */ - (PbCentFir, bit(14)) ? defaultMaskedError; - - /** PBCENTFIR[15] - * PB_CENT_F1_OVERFLOW - */ - (PbCentFir, bit(15)) ? defaultMaskedError; - - /** PBCENTFIR[16] - * FIR_SCOM_CENT_ERR - */ - (PbCentFir, bit(16)) ? defaultMaskedError; - - /** PBCENTFIR[17] - * FIR_SCOM_CENT_ERR_DUP - */ - (PbCentFir, bit(17)) ? defaultMaskedError; -}; - -################################################################################ -# PB Chiplet PSIHBFIR -################################################################################ - -#actions for bits updated based on p8dd1_mss_FFDC_54 - -rule PsiHbFir -{ - CHECK_STOP: PSIHBFIR & ~PSIHBFIR_MASK & ~PSIHBFIR_ACT0 & ~PSIHBFIR_ACT1; - RECOVERABLE: PSIHBFIR & ~PSIHBFIR_MASK & ~PSIHBFIR_ACT0 & PSIHBFIR_ACT1; -}; - -group gPsiHbFir filter singlebit -{ - /** PSIHBFIR[0] - * PB_ECC_ERR_CE - */ - (PsiHbFir, bit(0)) ? SelfHighThr32PerDay; - - /** PSIHBFIR[1] - * PB_ECC_ERR_UE - */ - (PsiHbFir, bit(1)) ? SelfHighThr1; - - /** PSIHBFIR[2] - * PB_ECC_ERR_SUE - */ - (PsiHbFir, bit(2)) ? defaultMaskedError; - - /** PSIHBFIR[3] - * INTERRUPT_FROM_ERROR - */ - (PsiHbFir, bit(3)) ? defaultMaskedError; - - /** PSIHBFIR[4] - * INTERRUPT_FROM_FSP - */ - (PsiHbFir, bit(4)) ? defaultMaskedError; - - /** PSIHBFIR[5] - * FSP_ECC_ERR_CE - */ - (PsiHbFir, bit(5)) ? calloutPsiThr32; - - /** PSIHBFIR[6] - * FSP_ECC_ERR_UE - */ - (PsiHbFir, bit(6)) ? calloutPsiThr1; - - /** PSIHBFIR[7] - * ERROR_STATE - */ - (PsiHbFir, bit(7)) ? defaultMaskedError; - - /** PSIHBFIR[8] - * INVALID_TTYPE - */ - (PsiHbFir, bit(8)) ? calloutProcLevel2MedThr1dumpShNoGard; - - /** PSIHBFIR[9] - * INVALID_CRESP - */ - (PsiHbFir, bit(9)) ? calloutProcLevel2MedThr1dumpShNoGard; - - /** PSIHBFIR[10] - * PB_DATA_TIME_OUT - */ - (PsiHbFir, bit(10)) ? callout2ndLvlMedThr1; - - /** PSIHBFIR[11] - * PB_PARITY_ERROR - */ - (PsiHbFir, bit(11)) ? callout2ndLvlMedThr1; - - /** PSIHBFIR[12] - * FSP_ACCESS_TRUSTED_SPACE - */ - (PsiHbFir, bit(12)) ? callout2ndLvlMedThr1; - - /** PSIHBFIR[13] - * UNEXPECTED_PB - */ - (PsiHbFir, bit(13)) ? calloutProcLevel2MedThr1dumpShNoGard; - - /** PSIHBFIR[14] - * INTERRUPT_REG_CHANGE_WHILE_ACTIVE - */ - (PsiHbFir, bit(14)) ? defaultMaskedError; - - /** PSIHBFIR[15] - * INTERRUPT0_ADDRESS_ERROR - */ - (PsiHbFir, bit(15)) ? calloutProcLevel2MedThr1dumpShNoGard; - - /** PSIHBFIR[16] - * INTERRUPT1_ADDRESS_ERROR - */ - (PsiHbFir, bit(16)) ? calloutProcLevel2MedThr1dumpShNoGard; - - /** PSIHBFIR[17] - * INTERRUPT2_ADDRESS_ERROR - */ - (PsiHbFir, bit(17)) ? calloutProcLevel2MedThr1dumpShNoGard; - - /** PSIHBFIR[18] - * INTERRUPT3_ADDRESS_ERROR - */ - (PsiHbFir, bit(18)) ? calloutProcLevel2MedThr1dumpShNoGard; - - /** PSIHBFIR[19] - * INTERRUPT4_ADDRESS_ERROR - */ - (PsiHbFir, bit(19)) ? calloutProcLevel2MedThr1dumpShNoGard; - - /** PSIHBFIR[20] - * INTERRUPT5_ADDRESS_ERROR - */ - (PsiHbFir, bit(20)) ? calloutProcLevel2MedThr1dumpShNoGard; - - /** PSIHBFIR[21] - * TCBR_TP_PSI_GLB_ERR_0 - */ - #FIXME RTC 23127 Need to get validation from Rolf Fitz - (PsiHbFir, bit(21)) ? defaultMaskedError; - - /** PSIHBFIR[22] - * TCBR_TP_PSI_GLB_ERR_1 - */ - (PsiHbFir, bit(22)) ? defaultMaskedError; - - /** PSIHBFIR[23] - * UPSTREAM_FIR - */ - (PsiHbFir, bit(23)) ? calloutProcLevel2MedThr32dumpShNoGard; - - /** PSIHBFIR[24|25|26] - * SPARE_FIR - */ - (PsiHbFir, bit(24|25|26)) ? defaultMaskedError; - - /** PSIHBFIR[27] - * SCOM_ERROR - */ - (PsiHbFir, bit(27)) ? defaultMaskedError; - - /** PSIHBFIR[28] - * FIR_PARITY_ERROR - */ - (PsiHbFir, bit(28)) ? defaultMaskedError; -}; - -################################################################################ -# PB Chiplet ICPFIR -################################################################################ - -#Based on p8dd1_mss_FFDC_70.xls -rule IcpFir -{ - CHECK_STOP: ICPFIR & ~ICPFIR_MASK & ~ICPFIR_ACT0 & ~ICPFIR_ACT1; - RECOVERABLE: ICPFIR & ~ICPFIR_MASK & ~ICPFIR_ACT0 & ICPFIR_ACT1; -}; - -group gIcpFir filter singlebit -{ - /** ICPFIR[0] - * INT_HW_ERROR_EOI_Q - */ - (IcpFir, bit(0)) ? SelfMedThr1; - - /** ICPFIR[1] - * INT_HW_ERROR_FWD_Q - */ - (IcpFir, bit(1)) ? SelfMedThr1; - - /** ICPFIR[2] - * INT_HW_ERROR_IR_QU - */ - (IcpFir, bit(2)) ? SelfMedThr1; - - /** ICPFIR[3] - * INT_HW_ERROR_RET_Q - */ - (IcpFir, bit(3)) ? SelfMedThr32PerDay; - - /** ICPFIR[4] - * INT_HW_ERROR_ADDRI - */ - (IcpFir, bit(4)) ? defaultMaskedError; - - /** ICPFIR[5] - * INT_HW_ERROR_DATAI - */ - (IcpFir, bit(5)) ? SelfMedThr32PerDay; - - /** ICPFIR[6] - * INT_HW_ERROR_ADDRO - */ - (IcpFir, bit(6)) ? SelfMedThr32PerDay; - - /** ICPFIR[7] - * INT_HW_ERROR_DATAO - */ - (IcpFir, bit(7)) ? SelfMedThr32PerDay; - - /** ICPFIR[8] - * INT_HW_ERROR_LDSTQ - */ - (IcpFir, bit(8)) ? SelfMedThr32PerDay; - - /** ICPFIR[9] - * INT_HW_ERROR_REQQ - */ - (IcpFir, bit(9)) ? SelfMedThr32PerDay; - - /** ICPFIR[10] - * SCOM_REG_CHECK - */ - (IcpFir, bit(10)) ? SelfMedThr32PerDay; - - /** ICPFIR[11] - * LOOP IN CHAIN OF LINK REGISTER OR INVALID CORE ID - */ - (IcpFir, bit(11)) ? defaultMaskedError; - - /** ICPFIR[12] - * INVALID CORE NUMBER IN INTERRUPT COMMANDS - */ - (IcpFir, bit(12)) ? defaultMaskedError; - - /** ICPFIR[13] - * INVALID CORE NUMBER IN MMIO COMMANDS - */ - (IcpFir, bit(13)) ? defaultMaskedError; - - /** ICPFIR[14] - * UNSOLICITED_CRESP - */ - (IcpFir, bit(14)) ? defaultMaskedError; - - /** ICPFIR[15] - * UNSOLICITED_DATA - */ - (IcpFir, bit(15)) ? defaultMaskedError; - - /** ICPFIR[16] - * INVALID_CMD - */ - (IcpFir, bit(16)) ? defaultMaskedError; - - /** ICPFIR[17] - * INVALID_CRESPZ - */ - (IcpFir, bit(17)) ? defaultMaskedError; - - /** ICPFIR[18] - * INVALID_CRESP - */ - (IcpFir, bit(18)) ? defaultMaskedError; - - /** ICPFIR[19] - * Reserved field (Access type is reserved) - */ - (IcpFir, bit(19)) ? defaultMaskedError; - - /** ICPFIR[20] - * ECC_CE_ON_DATA - */ - (IcpFir, bit(20)) ? SelfMedThr32PerDay; - - /** ICPFIR[21] - * ECC_UE_ON_DATA - */ - (IcpFir, bit(21)) ? SelfMedThr32PerDay; - - /** ICPFIR[22] - * ECC_SUE_ON_DATA - */ - (IcpFir, bit(22)) ? SelfMedThr32PerDay; - - /** ICPFIR[23] - * PARITY_CHK_ADDRESS - */ - (IcpFir, bit(23)) ? SelfMedThr32PerDay; - - /** ICPFIR[24] - * PARITY_CHK_TAG - */ - (IcpFir, bit(24)) ? SelfMedThr32PerDay; - - /** ICPFIR[25] - * TIMEOUT_LD_STQ - */ - (IcpFir, bit(25)) ? SelfMedThr32PerDay; - - /** ICPFIR[26] - * TIMEOUT_RETURNQ - */ - (IcpFir, bit(26)) ? SelfMedThr32PerDay; - - /** ICPFIR[27] - * TIMEOUT_FWDQ - */ - (IcpFir, bit(27)) ? SelfMedThr32PerDay; - - /** ICPFIR[28] - * TIMEOUT_EOIQ - */ - (IcpFir, bit(28)) ? SelfMedThr32PerDay; - - /** ICPFIR[29] - * RESERVED - */ - (IcpFir, bit(29)) ? SelfMedThr32PerDay; - - /** ICPFIR[30] - * RESERVED - */ - (IcpFir, bit(30)) ? SelfMedThr32PerDay; - - /** ICPFIR[31] - * RESERVED - */ - (IcpFir, bit(31)) ? defaultMaskedError; - - /** ICPFIR[32] - * EXT_TRACE_0 - */ - (IcpFir, bit(32)) ? SelfMedThr32PerDay; - - /** ICPFIR[33] - * EXT_TRACE_1 - */ - (IcpFir, bit(33)) ? SelfMedThr32PerDay; - - /** ICPFIR[34] - * ADU_RECOV - */ - (IcpFir, bit(34)) ? SelfMedThr32PerDay; - - /** ICPFIR[35] - * EXT_XSTOP - */ - (IcpFir, bit(35)) ? SelfMedThr32PerDay; - - /** ICPFIR[36:37] - * Reserved - */ - (IcpFir, bit(36|37)) ? defaultMaskedError; -}; - -################################################################################ -# PB Chiplet PBAFIR -################################################################################ - -rule PbaFir -{ - CHECK_STOP: PBAFIR & ~PBAFIR_MASK & ~PBAFIR_ACT0 & ~PBAFIR_ACT1; - RECOVERABLE: PBAFIR & ~PBAFIR_MASK & ~PBAFIR_ACT0 & PBAFIR_ACT1; -}; - -group gPbaFir filter singlebit -{ - /** PBAFIR[0] - * PBAFIR_OCI_APAR_ERR - */ - (PbaFir, bit(0)) ? SelfHighThr1; - - /** PBAFIR[1] - * PBAFIR_PB_RDADRERR_FW - */ - (PbaFir, bit(1)) ? callout2ndLvlMedThr1; - - /** PBAFIR[2] - * PBAFIR_PB_RDDATATO_FW - */ - (PbaFir, bit(2)) ? callout2ndLvlMedThr1; - - /** PBAFIR[3] - * PBAFIR_PB_SUE_FW - */ - (PbaFir, bit(3)) ? callout2ndLvlMedThr32; - - /** PBAFIR[4] - * PBAFIR_PB_UE_FW - */ - (PbaFir, bit(4)) ? SelfHighThr1; - - /** PBAFIR[3:4] - * PBAFIR_PB_SUE_FW - */ - (PbaFir, bit(3,4)) ? callout2ndLvlMedThr32; - - /** PBAFIR[5] - * PBAFIR_PB_CE_FW - */ - (PbaFir, bit(5)) ? callout2ndLvlMedThr32; - - /** PBAFIR[6] - * PBAFIR_OCI_SLAVE_INIT - */ - (PbaFir, bit(6)) ? callout2ndLvlMedThr1; - - /** PBAFIR[7] - * PBAFIR_OCI_WRPAR_ERR - */ - (PbaFir, bit(7)) ? callout2ndLvlMedThr1; - - /** PBAFIR[8] - * PBAFIR_OCI_REREQTO - */ - (PbaFir, bit(8)) ? defaultMaskedError; - - /** PBAFIR[9] - * PBAFIR_PB_UNEXPCRESP - */ - (PbaFir, bit(9)) ? callout2ndLvlMedThr1; - - /** PBAFIR[10] - * PBAFIR_PB_UNEXPDATA - */ - (PbaFir, bit(10)) ? callout2ndLvlMedThr1; - - /** PBAFIR[11] - * PBAFIR_PB_PARITY_ERR - */ - (PbaFir, bit(11)) ? callout2ndLvlMedThr1; - - /** PBAFIR[12] - * PBAFIR_PB_WRADRERR_FW - */ - (PbaFir, bit(12)) ? callout2ndLvlMedThr1; - - /** PBAFIR[13] - * PBAFIR_PB_BADCRESP - */ - (PbaFir, bit(13)) ? callout2ndLvlMedThr1; - - /** PBAFIR[14] - * PBAFIR_PB_ACKDEAD_FW - */ - (PbaFir, bit(14)) ? callout2ndLvlMedThr1; - - /** PBAFIR[15] - * PBAFIR_PB_CRESPTO - */ - (PbaFir, bit(15)) ? callout2ndLvlMedThr1; - - /** PBAFIR[16:19] - * PBAFIR_BCUE - */ - (PbaFir, bit(16|17|18|19)) ? defaultMaskedError; - - /** PBAFIR[20:27] - * PBAFIR_BCDE - */ - (PbaFir, bit(20|21|22|23|24|25|26|27)) ? defaultMaskedError; - - /** PBAFIR[28] - * PBAFIR_INTERNAL_ERR - */ - (PbaFir, bit(28)) ? SelfHighThr1; - - /** PBAFIR[29] - * PBAFIR_ILLEGAL_CACHE_OP - */ - (PbaFir, bit(29)) ? callout2ndLvlMedThr1; - - /** PBAFIR[30] - * PBAFIR_OCI_BAD_REG_ADDR - */ - (PbaFir, bit(30)) ? callout2ndLvlMedThr1; - - /** PBAFIR[31:39] - * PBAFIR_AX - */ - (PbaFir, bit(31|32|33|34|35|36|37|38|39)) ? defaultMaskedError; - - /** PBAFIR[40] - * PBAFIR_PB_ACKDEAD_FW_WR - */ - (PbaFir, bit(40)) ? callout2ndLvlMedThr1; - - /** PBAFIR[41:43] - * RESERVED - */ - (PbaFir, bit(41|42|43)) ? defaultMaskedError; - - /** PBAFIR[44|45] - * PBAFIR_FIR_PARITY_ERR - */ - (PbaFir, bit(44|45)) ? defaultMaskedError; -}; - -################################################################################ -# PB Chiplet EHHCAFIR -################################################################################ -# based on p8dd1_mss_FFDC_59.xls -################################################################################ -rule EhHcaFir -{ - CHECK_STOP: EHHCAFIR & ~EHHCAFIR_MASK & ~EHHCAFIR_ACT0 & ~EHHCAFIR_ACT1; - RECOVERABLE: EHHCAFIR & ~EHHCAFIR_MASK & ~EHHCAFIR_ACT0 & EHHCAFIR_ACT1; -}; - -group gEhHcaFir filter singlebit -{ - /** EHHCAFIR[0] - * CE1_0_OUT: array0_a CE - */ - (EhHcaFir, bit(0)) ? defaultMaskedError; - - /** EHHCAFIR[1] - * CE2_0_OUT: array0_b CE - */ - (EhHcaFir, bit(1)) ? defaultMaskedError; - - /** EHHCAFIR[2] - * UE1_0_OUT: array0_a ue - */ - (EhHcaFir, bit(2)) ? SelfHighThr32PerDay; - - /** EHHCAFIR[3] - * UE2_0_OUT: array0_b ue - */ - (EhHcaFir, bit(3)) ? SelfHighThr32PerDay; - - /** EHHCAFIR[4] - * CE1_1_OUT: array1_a CE - */ - (EhHcaFir, bit(4)) ? defaultMaskedError; - - /** EHHCAFIR[5] - * CE2_1_OUT: array1_b CE - */ - (EhHcaFir, bit(5)) ? defaultMaskedError; - - /** EHHCAFIR[6] - * UE1_1_OUT: array1_a ue - */ - (EhHcaFir, bit(6)) ? SelfHighThr32PerDay; - - /** EHHCAFIR[7] - * UE2_1_OUT: array1_b ue - */ - (EhHcaFir, bit(7)) ? SelfHighThr32PerDay; - - /** EHHCAFIR[8] - * CE1_2_OUT: array2_a CE - */ - (EhHcaFir, bit(8)) ? defaultMaskedError; - - /** EHHCAFIR[9] - * CE2_2_OUT: array2_b CE - */ - (EhHcaFir, bit(9)) ? defaultMaskedError; - - /** EHHCAFIR[10] - * UE1_2_OUT: array2_a ue - */ - (EhHcaFir, bit(10)) ? SelfHighThr32PerDay; - - /** EHHCAFIR[11] - * UE2_2_OUT: array2_b ue - */ - (EhHcaFir, bit(11)) ? SelfHighThr32PerDay; - - /** EHHCAFIR[12] - * CE1_3_OUT: array3_a CE - */ - (EhHcaFir, bit(12)) ? defaultMaskedError; - - /** EHHCAFIR[13] - * CE2_3_OUT: array3_b CE - */ - (EhHcaFir, bit(13)) ? defaultMaskedError; - - /** EHHCAFIR[14] - * UE1_3_OUT: array3_a ue - */ - (EhHcaFir, bit(14)) ? SelfHighThr32PerDay; - - /** EHHCAFIR[15] - * UE2_3_OUT: array3_b ue - */ - (EhHcaFir, bit(15)) ? SelfHighThr32PerDay; - - /** EHHCAFIR[16] - * CE1_4_OUT: array4_a CE - */ - (EhHcaFir, bit(16)) ? defaultMaskedError; - - /** EHHCAFIR[17] - * CE2_4_OUT: array4_b CE - */ - (EhHcaFir, bit(17)) ? defaultMaskedError; - - /** EHHCAFIR[18] - * UE1_4_OUT: array4_a ue - */ - (EhHcaFir, bit(18)) ? SelfHighThr32PerDay; - - /** EHHCAFIR[19] - * UE2_4_OUT: array4_b ue - */ - (EhHcaFir, bit(19)) ? SelfHighThr32PerDay; - - /** EHHCAFIR[20] - * CE1_5_OUT: array5_a CE - */ - (EhHcaFir, bit(20)) ? defaultMaskedError; - - /** EHHCAFIR[21] - * CE2_5_OUT: array5_b CE - */ - (EhHcaFir, bit(21)) ? defaultMaskedError; - - /** EHHCAFIR[22] - * UE1_5_OUT: array5_a ue - */ - (EhHcaFir, bit(22)) ? SelfHighThr32PerDay; - - /** EHHCAFIR[23] - * UE2_5_OUT: array5_b ue - */ - (EhHcaFir, bit(23)) ? SelfHighThr32PerDay; - - /** EHHCAFIR[24] - * CE1_6_OUT: array6_a CE - */ - (EhHcaFir, bit(24)) ? defaultMaskedError; - - /** EHHCAFIR[25] - * CE2_6_OUT: array6_b CE - */ - (EhHcaFir, bit(25)) ? defaultMaskedError; - - /** EHHCAFIR[26] - * UE1_6_OUT: array6_a ue - */ - (EhHcaFir, bit(26)) ? SelfHighThr32PerDay; - - /** EHHCAFIR[27] - * UE2_6_OUT: array6_b ue - */ - (EhHcaFir, bit(27)) ? SelfHighThr32PerDay; - - /** EHHCAFIR[28] - * CE1_7_OUT: array7_a CE - */ - (EhHcaFir, bit(28)) ? defaultMaskedError; - - /** EHHCAFIR[29] - * CE2_7_OUT: array7_b CE - */ - (EhHcaFir, bit(29)) ? defaultMaskedError; - - /** EHHCAFIR[30] - * UE1_7_OUT: array7_a ue - */ - (EhHcaFir, bit(30)) ? SelfHighThr32PerDay; - - /** EHHCAFIR[31] - * UE2_7_OUT: array7_b ue - */ - (EhHcaFir, bit(31)) ? SelfHighThr32PerDay; - - /** EHHCAFIR[32] - * DROP_COUNTER_FULL: Drop Counter Full - */ - (EhHcaFir, bit(32)) ? defaultMaskedError; - - /** EHHCAFIR[33] - * INTERNAL_ERROR: Internal Error - */ - (EhHcaFir, bit(33)) ? defaultMaskedError; - - /** EHHCAFIR[34] - * SCOM_ERROR - */ - (EhHcaFir, bit(34)) ? defaultMaskedError; - - /** EHHCAFIR[35] - * FIR_PARITY_ERROR - */ - (EhHcaFir, bit(35)) ? defaultMaskedError; -}; - -################################################################################ -# PB Chiplet ENHCAFIR -################################################################################ -#action updated based on p8dd1_mss_FFDC_59.xls -################################################################################ - -rule EnHcaFir -{ - CHECK_STOP: ENHCAFIR & ~ENHCAFIR_MASK & ~ENHCAFIR_ACT0 & ~ENHCAFIR_ACT1; - RECOVERABLE: ENHCAFIR & ~ENHCAFIR_MASK & ~ENHCAFIR_ACT0 & ENHCAFIR_ACT1; -}; - -group gEnHcaFir filter singlebit -{ - /** ENHCAFIR[0] - * DPX0_DAT_UE: PB0 data UE - */ - (EnHcaFir, bit(0)) ? SelfHighThr32PerDay; - - /** ENHCAFIR[1] - * DPX0_DAT_SUE: PB0 data SUE - */ - (EnHcaFir, bit(1)) ? defaultMaskedError; - - /** ENHCAFIR[2] - * DPX0_DAT_CE: PB0 data ue - */ - (EnHcaFir, bit(2)) ? SelfHighThr32PerDay; - - /** ENHCAFIR[3] - * Undefined - */ - (EnHcaFir, bit(3)) ? defaultMaskedError; - - /** ENHCAFIR[4] - * CO_DROP_COUNTER_FULL: Castout Drop Counter Full - */ - (EnHcaFir, bit(4)) ? defaultMaskedError; - - /** ENHCAFIR[5] - * DATA_HANG_DETECT: Castout Drop Counter Full - */ - (EnHcaFir, bit(5)) ? defaultMaskedError; - - /** ENHCAFIR[6] - * UNEXPECTED_DATA_OR_CRESP: Castout Drop Counter Full - */ - (EnHcaFir, bit(6)) ? defaultMaskedError; - - /** ENHCAFIR[7] - * INTERNAL_ERROR: Castout Drop Counter Full - */ - (EnHcaFir, bit(7)) ? defaultMaskedError; - - /** ENHCAFIR[8] - * SCOM_ERROR - */ - (EnHcaFir, bit(8)) ? defaultMaskedError; - - /** ENHCAFIR[9] - * FIR_PARITY_ERROR - */ - (EnHcaFir, bit(9)) ? defaultMaskedError; -}; - -# PB Chiplet PCINESTFIRs -################################################################################ - -# All these FIRs should have the same bit definition. Ideally, we want -# to have only one copy of the bit definition. Currently rule code -# parser does not have the support for something like this. -# Maybe we can add this as a later feature. - -################################################################################ -# FIR last updated based on p8dd1_mss_FFDC_37_ reviewd.xls -################################################################################ -rule PciNestFir_0 -{ - CHECK_STOP: - PCINESTFIR_0 & ~PCINESTFIR_0_MASK & ~PCINESTFIR_0_ACT0 & ~PCINESTFIR_0_ACT1; - RECOVERABLE: - PCINESTFIR_0 & ~PCINESTFIR_0_MASK & ~PCINESTFIR_0_ACT0 & PCINESTFIR_0_ACT1; -}; - -rule PciNestFir_1 -{ - CHECK_STOP: - PCINESTFIR_1 & ~PCINESTFIR_1_MASK & ~PCINESTFIR_1_ACT0 & ~PCINESTFIR_1_ACT1; - RECOVERABLE: - PCINESTFIR_1 & ~PCINESTFIR_1_MASK & ~PCINESTFIR_1_ACT0 & PCINESTFIR_1_ACT1; -}; - -rule PciNestFir_2 -{ - CHECK_STOP: - PCINESTFIR_2 & ~PCINESTFIR_2_MASK & ~PCINESTFIR_2_ACT0 & ~PCINESTFIR_2_ACT1; - RECOVERABLE: - PCINESTFIR_2 & ~PCINESTFIR_2_MASK & ~PCINESTFIR_2_ACT0 & PCINESTFIR_2_ACT1; -}; - -group gPciNestFir filter singlebit -{ - /** PCINESTFIR_0[0] - * BAR_PE - */ - (PciNestFir_0, bit(0)) ? calloutConnPci0Th1NoGard; - - /** PCINESTFIR_1[0] - * BAR_PE - */ - (PciNestFir_1, bit(0)) ? calloutConnPci1Th1NoGard; - - /** PCINESTFIR_2[0] - * BAR_PE - */ - (PciNestFir_2, bit(0)) ? calloutConnPci2Th1NoGard; - - /** PCINESTFIR_0[1] - * NONBAR_PE - */ - (PciNestFir_0, bit(1)) ? defaultMaskedError; - - /** PCINESTFIR_1[1] - * NONBAR_PE - */ - (PciNestFir_1, bit(1)) ? defaultMaskedError; - - /** PCINESTFIR_2[1] - * NONBAR_PE - */ - (PciNestFir_2, bit(1)) ? defaultMaskedError; - - /** PCINESTFIR_0[2] - * PB_TO_PEC_CE - */ - (PciNestFir_0, bit(2)) ? calloutConnPci0Th32NoGard; - - /** PCINESTFIR_1[2] - * PB_TO_PEC_CE - */ - (PciNestFir_1, bit(2)) ? calloutConnPci1Th32NoGard; - - /** PCINESTFIR_2[2] - * PB_TO_PEC_CE - */ - (PciNestFir_2, bit(2)) ? calloutConnPci1Th32NoGard; - - /** PCINESTFIR_0[3] - * PB_TO_PEC_UE - */ - (PciNestFir_0, bit(3)) ? defaultMaskedError; - - /** PCINESTFIR_1[3] - * PB_TO_PEC_UE - */ - (PciNestFir_1, bit(3)) ? defaultMaskedError; - - /** PCINESTFIR_2[3] - * PB_TO_PEC_UE - */ - (PciNestFir_2, bit(3)) ? defaultMaskedError; - - /** PCINESTFIR_0[4] - * PB_TO_PEC_SUE - */ - (PciNestFir_0, bit(4)) ? defaultMaskedError; - - /** PCINESTFIR_1[4] - * PB_TO_PEC_SUE - */ - (PciNestFir_1, bit(4)) ? defaultMaskedError; - - /** PCINESTFIR_2[4] - * PB_TO_PEC_SUE - */ - (PciNestFir_2, bit(4)) ? defaultMaskedError; - - /** PCINESTFIR_0[5] - * ARY_ECC_CE - */ - (PciNestFir_0, bit(5)) ? calloutConnPci0Th32NoGard; - - /** PCINESTFIR_1[5] - * ARY_ECC_CE - */ - (PciNestFir_1, bit(5)) ? calloutConnPci1Th32NoGard; - - /** PCINESTFIR_2[5] - * ARY_ECC_CE - */ - (PciNestFir_2, bit(5)) ? calloutConnPci2Th32NoGard; - - /** PCINESTFIR_0[6] - * ARY_ECC_UE - */ - (PciNestFir_0, bit(6)) ? defaultMaskedError; - - /** PCINESTFIR_1[6] - * ARY_ECC_UE - */ - (PciNestFir_1, bit(6)) ? defaultMaskedError; - - /** PCINESTFIR_2[6] - * ARY_ECC_UE - */ - (PciNestFir_2, bit(6)) ? defaultMaskedError; - - /** PCINESTFIR_0[7] - * ARY_ECC_SUE - */ - (PciNestFir_0, bit(7)) ? defaultMaskedError; - - /** PCINESTFIR_1[7] - * ARY_ECC_SUE - */ - (PciNestFir_1, bit(7)) ? defaultMaskedError; - - /** PCINESTFIR_2[7] - * ARY_ECC_SUE - */ - (PciNestFir_2, bit(7)) ? defaultMaskedError; - - /** PCINESTFIR_0[8] - * REGISTER_ARRAY_PE - */ - (PciNestFir_0, bit(8)) ? calloutConnPci0Th1NoGard; - - /** PCINESTFIR_1[8] - * REGISTER_ARRAY_PE - */ - (PciNestFir_1, bit(8)) ? calloutConnPci1Th1NoGard; - - /** PCINESTFIR_2[8] - * REGISTER_ARRAY_PE - */ - (PciNestFir_2, bit(8)) ? calloutConnPci2Th1NoGard; - - /** PCINESTFIR_0[9] - * PB_INTERFACE_PE - */ - (PciNestFir_0, bit(9)) ? calloutConnPci0Th1NoGard; - - /** PCINESTFIR_1[9] - * PB_INTERFACE_PE - */ - (PciNestFir_1, bit(9)) ? calloutConnPci1Th1NoGard; - - /** PCINESTFIR_2[9] - * PB_INTERFACE_PE - */ - (PciNestFir_2, bit(9)) ? calloutConnPci2Th1NoGard; - - /** PCINESTFIR_0[10] - * PB_DATA_HANG_ERRORS - */ - (PciNestFir_0, bit(10)) ? defaultMaskedError; - - /** PCINESTFIR_1[10] - * PB_DATA_HANG_ERRORS - */ - (PciNestFir_1, bit(10)) ? defaultMaskedError; - - /** PCINESTFIR_2[10] - * PB_DATA_HANG_ERRORS - */ - (PciNestFir_2, bit(10)) ? defaultMaskedError; - - /** PCINESTFIR_0[11] - * PB_HANG_ERRORS - */ - (PciNestFir_0, bit(11)) ? defaultMaskedError; - - /** PCINESTFIR_1[11] - * PB_HANG_ERRORS - */ - (PciNestFir_1, bit(11)) ? defaultMaskedError; - - /** PCINESTFIR_2[11] - * PB_HANG_ERRORS - */ - (PciNestFir_2, bit(11)) ? defaultMaskedError; - - /** PCINESTFIR_0[12] - * RD_ARE_ERRORS - */ - (PciNestFir_0, bit(12)) ? defaultMaskedError; - - /** PCINESTFIR_1[12] - * RD_ARE_ERRORS - */ - (PciNestFir_1, bit(12)) ? defaultMaskedError; - - /** PCINESTFIR_2[12] - * RD_ARE_ERRORS - */ - (PciNestFir_2, bit(12)) ? defaultMaskedError; - - /** PCINESTFIR_0[13] - * NONRD_ARE_ERRORS - */ - (PciNestFir_0, bit(13)) ? defaultMaskedError; - - /** PCINESTFIR_1[13] - * NONRD_ARE_ERRORS - */ - (PciNestFir_1, bit(13)) ? defaultMaskedError; - - /** PCINESTFIR_2[13] - * NONRD_ARE_ERRORS - */ - (PciNestFir_2, bit(13)) ? defaultMaskedError; - - /** PCINESTFIR_0[14] - * PCI_HANG_ERROR - */ - (PciNestFir_0, bit(14)) ? defaultMaskedError; - - /** PCINESTFIR_1[14] - * PCI_HANG_ERROR - */ - (PciNestFir_1, bit(14)) ? defaultMaskedError; - - /** PCINESTFIR_2[14] - * PCI_HANG_ERROR - */ - (PciNestFir_2, bit(14)) ? defaultMaskedError; - - /** PCINESTFIR_0[15] - * PCI_CLOCK_ERROR - * - * These should never trigger directly themselves. - * Should be handled by global PRD PLL code. - */ - (PciNestFir_0, bit(15)) ? threshold32pday; - - /** PCINESTFIR_1[15] - * PCI_CLOCK_ERROR - * - * These should never trigger directly themselves. - * Should be handled by global PRD PLL code. - */ - (PciNestFir_1, bit(15)) ? threshold32pday; - - /** PCINESTFIR_2[15] - * PCI_CLOCK_ERROR - * - * These should never trigger directly themselves. - * Should be handled by global PRD PLL code. - */ - (PciNestFir_2, bit(15)) ? threshold32pday; - - /** PCINESTFIR_0[16] - * AIB_FENCE - */ - (PciNestFir_0, bit(16)) ? defaultMaskedError; - - /** PCINESTFIR_1[16] - * AIB_FENCE - */ - (PciNestFir_1, bit(16)) ? defaultMaskedError; - - /** PCINESTFIR_2[16] - * AIB_FENCE - */ - (PciNestFir_2, bit(16)) ? defaultMaskedError; - - /** PCINESTFIR_0[17] - * HW_ERRORS - */ - (PciNestFir_0, bit(17)) ? calloutConnPci0Th1NoGard; - - /** PCINESTFIR_1[17] - * HW_ERRORS - */ - (PciNestFir_1, bit(17)) ? calloutConnPci1Th1NoGard; - - /** PCINESTFIR_2[17] - * HW_ERRORS - */ - (PciNestFir_2, bit(17)) ? calloutConnPci2Th1NoGard; - - /** PCINESTFIR_0[18] - * UNSOLICITIEDPBDATA - */ - (PciNestFir_0, bit(18)) ? callout2ndLvlMedThr1; - - /** PCINESTFIR_1[18] - * UNSOLICITIEDPBDATA - */ - (PciNestFir_1, bit(18)) ? callout2ndLvlMedThr1; - - /** PCINESTFIR_2[18] - * UNSOLICITIEDPBDATA - */ - (PciNestFir_2, bit(18)) ? callout2ndLvlMedThr1; - - /** PCINESTFIR_0[19] - * UNEXPECTEDCRESP - */ - (PciNestFir_0, bit(19)) ? callout2ndLvlMedThr1; - - /** PCINESTFIR_1[19] - * UNEXPECTEDCRESP - */ - (PciNestFir_1, bit(19)) ? callout2ndLvlMedThr1; - - /** PCINESTFIR_2[19] - * UNEXPECTEDCRESP - */ - (PciNestFir_2, bit(19)) ? callout2ndLvlMedThr1; - - /** PCINESTFIR_0[20] - * INVALIDCRESP - */ - (PciNestFir_0, bit(20)) ? calloutProcLevel2MedThr1; - - /** PCINESTFIR_1[20] - * INVALIDCRESP - */ - (PciNestFir_1, bit(20)) ? calloutProcLevel2MedThr1; - - /** PCINESTFIR_2[20] - * INVALIDCRESP - */ - (PciNestFir_2, bit(20)) ? calloutProcLevel2MedThr1; - - /** PCINESTFIR_0[21] - * PBUNSUPPORTEDSIZE - */ - (PciNestFir_0, bit(21)) ? calloutProcLevel2MedThr1; - - /** PCINESTFIR_1[21] - * PBUNSUPPORTEDSIZE - */ - (PciNestFir_1, bit(21)) ? calloutProcLevel2MedThr1; - - /** PCINESTFIR_2[21] - * PBUNSUPPORTEDSIZE - */ - (PciNestFir_2, bit(21)) ? calloutProcLevel2MedThr1; - - /** PCINESTFIR_0[22] - * PBUNSUPPORTEDCMD - */ - (PciNestFir_0, bit(22)) ? calloutProcLevel2MedThr1; - - /** PCINESTFIR_1[22] - * PBUNSUPPORTEDCMD - */ - (PciNestFir_1, bit(22)) ? calloutProcLevel2MedThr1; - - /** PCINESTFIR_2[22] - * PBUNSUPPORTEDCMD - */ - (PciNestFir_2, bit(22)) ? calloutProcLevel2MedThr1; - - /** PCINESTFIR_0[23] - * AIB_PE - */ - (PciNestFir_0, bit(23)) ? defaultMaskedError; - - /** PCINESTFIR_1[23] - * AIB_PE - */ - (PciNestFir_1, bit(23)) ? defaultMaskedError; - - /** PCINESTFIR_2[23] - * AIB_PE - */ - (PciNestFir_2, bit(23)) ? defaultMaskedError; - - /** PCINESTFIR_0[24] - * ASB_ERROR - */ - (PciNestFir_0, bit(24)) ? defaultMaskedError; - - /** PCINESTFIR_1[24] - * ASB_ERROR - */ - (PciNestFir_1, bit(24)) ? defaultMaskedError; - - /** PCINESTFIR_2[24] - * ASB_ERROR - */ - (PciNestFir_2, bit(24)) ? defaultMaskedError; - - /** PCINESTFIR_0[25] - * FOREIGN_LINK_FAIL - */ - (PciNestFir_0, bit(25)) ? defaultMaskedError; - - /** PCINESTFIR_1[25] - * FOREIGN_LINK_FAIL - */ - (PciNestFir_1, bit(25)) ? defaultMaskedError; - - /** PCINESTFIR_2[25] - * FOREIGN_LINK_FAIL - */ - (PciNestFir_2, bit(25)) ? defaultMaskedError; - - /** PCINESTFIR_0[26] - * FOREIGN_PB_HANG - */ - (PciNestFir_0, bit(26)) ? defaultMaskedError; - - /** PCINESTFIR_1[26] - * FOREIGN_PB_HANG - */ - (PciNestFir_1, bit(26)) ? defaultMaskedError; - - /** PCINESTFIR_2[26] - * FOREIGN_PB_HANG - */ - (PciNestFir_2, bit(26)) ? defaultMaskedError; - - /** PCINESTFIR_0[27] - * CAPP_ERROR - */ - (PciNestFir_0, bit(27)) ? defaultMaskedError; - - /** PCINESTFIR_1[27] - * CAPP_ERROR - */ - (PciNestFir_1, bit(27)) ? defaultMaskedError; - - /** PCINESTFIR_2[27] - * CAPP_ERROR - */ - (PciNestFir_2, bit(27)) ? defaultMaskedError; - - /** PCINESTFIR_0[28] - * SYNC_SCOM_ERR - */ - (PciNestFir_0, bit(28)) ? defaultMaskedError; - - /** PCINESTFIR_1[28] - * SYNC_SCOM_ERR - */ - (PciNestFir_1, bit(28)) ? defaultMaskedError; - - /** PCINESTFIR_2[28] - * SYNC_SCOM_ERR - */ - (PciNestFir_2, bit(28)) ? defaultMaskedError; - - /** PCINESTFIR_0[29] - * SCOM Engine ERROR 0 - */ - (PciNestFir_0, bit(29)) ? defaultMaskedError; - - /** PCINESTFIR_1[29] - * SCOM Engine ERROR 0 - */ - (PciNestFir_1, bit(29)) ? defaultMaskedError; - - /** PCINESTFIR_2[29] - * SCOM Engine ERROR 0 - */ - (PciNestFir_2, bit(29)) ? defaultMaskedError; - - /** PCINESTFIR_0[30] - * SCOM Engine ERROR 0 - */ - (PciNestFir_0, bit(30)) ? defaultMaskedError; - - /** PCINESTFIR_1[30] - * SCOM Engine ERROR 1 - */ - (PciNestFir_1, bit(30)) ? defaultMaskedError; - - /** PCINESTFIR_2[30] - * SCOM Engine ERROR 1 - */ - (PciNestFir_2, bit(30)) ? defaultMaskedError; - -}; - -rule PciNestFir_3 -{ - CHECK_STOP: - PCINESTFIR_3 & ~PCINESTFIR_3_MASK & ~PCINESTFIR_3_ACT0 & ~PCINESTFIR_3_ACT1; - RECOVERABLE: - PCINESTFIR_3 & ~PCINESTFIR_3_MASK & ~PCINESTFIR_3_ACT0 & PCINESTFIR_3_ACT1; -}; - -group gPciNestFir3 filter singlebit -{ - /** PCINESTFIR_3[0] - * BAR_PE - */ - (PciNestFir_3, bit(0)) ? calloutConnPci3Th1NoGard; - - /** PCINESTFIR_3[1] - * NONBAR_PE - */ - (PciNestFir_3, bit(1)) ? defaultMaskedError; - - /** PCINESTFIR_3[2] - * PB_TO_PEC_CE - */ - (PciNestFir_3, bit(2)) ? calloutConnPci3Th32NoGard; - - /** PCINESTFIR_3[3] - * PB_TO_PEC_UE - */ - (PciNestFir_3, bit(3)) ? defaultMaskedError; - - /** PCINESTFIR_3[4] - * PB_TO_PEC_SUE - */ - (PciNestFir_3, bit(4)) ? defaultMaskedError; - - /** PCINESTFIR_3[5] - * ARY_ECC_CE - */ - (PciNestFir_3, bit(5)) ? calloutConnPci3Th32NoGard; - - /** PCINESTFIR_3[6] - * ARY_ECC_UE - */ - (PciNestFir_3, bit(6)) ? defaultMaskedError; - - /** PCINESTFIR_3[7] - * ARY_ECC_SUE - */ - (PciNestFir_3, bit(7)) ? defaultMaskedError; - - /** PCINESTFIR_3[8] - * REGISTER_ARRAY_PE - */ - (PciNestFir_3, bit(8)) ? calloutConnPci3Th1NoGard; - - /** PCINESTFIR_3[9] - * PB_INTERFACE_PE - */ - (PciNestFir_3, bit(9)) ? calloutConnPci3Th1NoGard; - - /** PCINESTFIR_3[10] - * PB_DATA_HANG_ERRORS - */ - (PciNestFir_3, bit(10)) ? defaultMaskedError; - - /** PCINESTFIR_3[11] - * PB_HANG_ERRORS - */ - (PciNestFir_3, bit(11)) ? defaultMaskedError; - - /** PCINESTFIR_3[12] - * RD_ARE_ERRORS - */ - (PciNestFir_3, bit(12)) ? defaultMaskedError; - - /** PCINESTFIR_3[13] - * NONRD_ARE_ERRORS - */ - (PciNestFir_3, bit(13)) ? defaultMaskedError; - - /** PCINESTFIR_3[14] - * PCI_HANG_ERROR - */ - (PciNestFir_3, bit(14)) ? defaultMaskedError; - - /** PCINESTFIR_3[15] - * PCI_CLOCK_ERROR - * - * These should never trigger directly themselves. - * Should be handled by global PRD PLL code. - */ - (PciNestFir_3, bit(15)) ? threshold32pday; - - /** PCINESTFIR_3[16] - * AIB_FENCE - */ - (PciNestFir_3, bit(16)) ? defaultMaskedError; - - /** PCINESTFIR_3[17] - * HW_ERRORS - */ - (PciNestFir_3, bit(17)) ? calloutConnPci3Th1NoGard; - - /** PCINESTFIR_3[18] - * UNSOLICITIEDPBDATA - */ - (PciNestFir_3, bit(18)) ? callout2ndLvlMedThr1; - - /** PCINESTFIR_3[19] - * UNEXPECTEDCRESP - */ - (PciNestFir_3, bit(19)) ? callout2ndLvlMedThr1; - - /** PCINESTFIR_0[20] - * INVALIDCRESP - */ - (PciNestFir_3, bit(20)) ? calloutProcLevel2MedThr1; - - /** PCINESTFIR_0[21] - * PBUNSUPPORTEDSIZE - */ - (PciNestFir_3, bit(21)) ? calloutProcLevel2MedThr1; - - /** PCINESTFIR_0[22] - * PBUNSUPPORTEDCMD - */ - (PciNestFir_3, bit(22)) ? calloutProcLevel2MedThr1; - - /** PCINESTFIR_0[23] - * AIB_PE - */ - (PciNestFir_3, bit(23)) ? defaultMaskedError; - - /** PCINESTFIR_3[24] - * ASB_ERROR - */ - (PciNestFir_3, bit(24)) ? defaultMaskedError; - - /** PCINESTFIR_3[25] - * FOREIGN_LINK_FAIL - */ - (PciNestFir_3, bit(25)) ? defaultMaskedError; - - /** PCINESTFIR_3[26] - * FOREIGN_PB_HANG - */ - (PciNestFir_3, bit(26)) ? defaultMaskedError; - - /** PCINESTFIR_3[27] - * CAPP_ERROR - */ - (PciNestFir_3, bit(27)) ? defaultMaskedError; - - /** PCINESTFIR_3[28] - * SYNC_SCOM_ERR - */ - (PciNestFir_3, bit(28)) ? defaultMaskedError; - - /** PCINESTFIR_3[29] - * SCOM Engine ERROR 0 - */ - (PciNestFir_3, bit(29)) ? defaultMaskedError; - - /** PCINESTFIR_3[30] - * SCOM Engine ERROR 0 - */ - (PciNestFir_3, bit(30)) ? defaultMaskedError; -}; - -################################################################################ -# PB Chiplet IOMCFIR_0 -################################################################################ -# RAS spreadsheet: p8dd1_mss_FFDC_37_ reviewd.xls - -rule IomcFir_0 -{ - CHECK_STOP: IOMCFIR_0 & ~IOMCFIR_0_MASK & ~IOMCFIR_0_ACT0 & ~IOMCFIR_0_ACT1; - RECOVERABLE: IOMCFIR_0 & ~IOMCFIR_0_MASK & ~IOMCFIR_0_ACT0 & IOMCFIR_0_ACT1; -}; - -group gIomcFir_0 filter priority( 10, 18, 26, 34, # Channel failure - 2, # Recoverable - 11, 19, 27, 35, # Recoverable - 12, 20, 28, 36, # Recoverable - 9, 17, 25, 33 ), # Recoverable - secondarybits( 0, 1, 3, 4, 5, 6, 7, - 8, 9,11,12,13,14,15, - 16,17,19,20,21,22,23, - 24,25,27,28,29,30,31, - 32,33,35,36,37,38,39, - 40,41,43,44,45,46,47,48,49) -{ - /** IOMCFIR_0[0] - * FIR_RX_INVALID_STATE_OR_PARITY_ERROR - */ - (IomcFir_0, bit(0)) ? defaultMaskedError; - - /** IOMCFIR_0[1] - * FIR_TX_INVALID_STATE_OR_PARITY_ERROR - */ - (IomcFir_0, bit(1)) ? defaultMaskedError; - - /** IOMCFIR_0[2] - * FIR_GCR_HANG_ERROR - */ - (IomcFir_0, bit(2)) ? SelfHighThr1; - - /** IOMCFIR_0[3:7] - * Reserved - */ - (IomcFir_0, bit(3|4|5|6|7)) ? defaultMaskedError; - - /** IOMCFIR_0[8] - * MCS0 Training Error - */ - (IomcFir_0, bit(8)) ? defaultMaskedError; - - /** IOMCFIR_0[9] - * MCS0 Spare Deployed - */ - (IomcFir_0, bit(9)) ? spareDeployed_dmiBus0; - - /** IOMCFIR_0[10] - * MCS0 Max Spares Exceeded - */ - (IomcFir_0, bit(10)) ? maxSparesExceeded_dmiBus0; - - /** IOMCFIR_0[11] - * MCS0 Recalibration or Dynamic Repair Error - */ - (IomcFir_0, bit(11)) ? calloutDmiBus0Th1; - - /** IOMCFIR_0[12] - * MCS0 Too Many Bus Errors - */ - (IomcFir_0, bit(12)) ? calloutDmiBus0Th1; - - /** IOMCFIR_0[13:15] - * Reserved - */ - (IomcFir_0, bit(13|14|15)) ? defaultMaskedError; - - /** IOMCFIR_0[16] - * MCS1 Training Error - */ - (IomcFir_0, bit(16)) ? defaultMaskedError; - - /** IOMCFIR_0[17] - * MCS1 Spare Deployed - */ - (IomcFir_0, bit(17)) ? spareDeployed_dmiBus1; - - /** IOMCFIR_0[18] - * MCS1 Max Spares Exceeded - */ - (IomcFir_0, bit(18)) ? maxSparesExceeded_dmiBus1; - - /** IOMCFIR_0[19] - * MCS1 Recalibration or Dynamic Repair Error - */ - (IomcFir_0, bit(19)) ? calloutDmiBus1Th1; - - /** IOMCFIR_0[20] - * MCS1 Too Many Bus Errors - */ - (IomcFir_0, bit(20)) ? calloutDmiBus1Th1; - - /** IOMCFIR_0[21:23] - * Reserved - */ - (IomcFir_0, bit(21|22|23)) ? defaultMaskedError; - - /** IOMCFIR_0[24] - * MCS2 Training Error - */ - (IomcFir_0, bit(24)) ? defaultMaskedError; - - /** IOMCFIR_0[25] - * MCS2 Spare Deployed - */ - (IomcFir_0, bit(25)) ? spareDeployed_dmiBus2; - - /** IOMCFIR_0[26] - * MCS2 Max Spares Exceeded - */ - (IomcFir_0, bit(26)) ? maxSparesExceeded_dmiBus2; - - /** IOMCFIR_0[27] - * MCS2 Recalibration or Dynamic Repair Error - */ - (IomcFir_0, bit(27)) ? calloutDmiBus2Th1; - - /** IOMCFIR_0[28] - * MCS2 Too Many Bus Errors - */ - (IomcFir_0, bit(28)) ? calloutDmiBus2Th1; - - /** IOMCFIR_0[29:31] - * Reserved - */ - (IomcFir_0, bit(29|30|31)) ? defaultMaskedError; - - /** IOMCFIR_0[32] - * MCS3 Training Error - */ - (IomcFir_0, bit(32)) ? defaultMaskedError; - - /** IOMCFIR_0[33] - * MCS3 Spare Deployed - */ - (IomcFir_0, bit(33)) ? spareDeployed_dmiBus3; - - /** IOMCFIR_0[34] - * MCS3 Max Spares Exceeded - */ - (IomcFir_0, bit(34)) ? maxSparesExceeded_dmiBus3; - - /** IOMCFIR_0[35] - * MCS3 Recalibration or Dynamic Repair Error - */ - (IomcFir_0, bit(35)) ? calloutDmiBus3Th1; - - /** IOMCFIR_0[36] - * MCS3 Too Many Bus Errors - */ - (IomcFir_0, bit(36)) ? calloutDmiBus3Th1; - - /** IOMCFIR_0[37:39] - * Reserved - */ - (IomcFir_0, bit(37|38|39)) ? defaultMaskedError; - - /** IOMCFIR_0[40:47] - * FIR_RX_BUS4 unused - */ - (IomcFir_0, bit(40|41|42|43|44|45|46|47)) ? defaultMaskedError; - - /** IOMCFIR_0[48] - * FIR_SCOMFIR_ERROR - */ - (IomcFir_0, bit(48)) ? defaultMaskedError; - - /** IOMCFIR_0[49] - * FIR_SCOMFIR_ERROR_CLONE - */ - (IomcFir_0, bit(49)) ? defaultMaskedError; -}; - -################################################################################ -# PB Chiplet IOMCFIR_1 -################################################################################ -# RAS spreadsheet: p8dd1_mss_FFDC_72_ reviewd.xls on Jan 18,2014 - -rule IomcFir_1 -{ - CHECK_STOP: IOMCFIR_1 & ~IOMCFIR_1_MASK & ~IOMCFIR_1_ACT0 & ~IOMCFIR_1_ACT1; - RECOVERABLE: IOMCFIR_1 & ~IOMCFIR_1_MASK & ~IOMCFIR_1_ACT0 & IOMCFIR_1_ACT1; -}; - -group gIomcFir_1 filter priority( 10, 18, 26, 34, # Channel failure - 2, # Recoverable - 11, 19, 27, 35, # Recoverable - 12, 20, 28, 36, # Recoverable - 9, 17, 25, 33 ), # Recoverable - secondarybits( 0, 1, 3, 4, 5, 6, 7, - 8, 9,11,12,13,14,15, - 16,17,19,20,21,22,23, - 24,25,27,28,29,30,31, - 32,33,35,36,37,38,39, - 40,41,43,44,45,46,47,48,49) -{ - /** IOMCFIR_1[0] - * FIR_RX_INVALID_STATE_OR_PARITY_ERROR - */ - (IomcFir_1, bit(0)) ? defaultMaskedError; - - /** IOMCFIR_1[1] - * FIR_TX_INVALID_STATE_OR_PARITY_ERROR - */ - (IomcFir_1, bit(1)) ? defaultMaskedError; - - /** IOMCFIR_1[2] - * FIR_GCR_HANG_ERROR - */ - (IomcFir_1, bit(2)) ? SelfHighThr1; - - /** IOMCFIR_1[3:7] - * Reserved - */ - (IomcFir_1, bit(3|4|5|6|7)) ? defaultMaskedError; - - /** IOMCFIR_1[8] - * MCS4 Training Error - */ - (IomcFir_1, bit(8)) ? defaultMaskedError; - - /** IOMCFIR_1[9] - * MCS4 Spare Deployed - */ - (IomcFir_1, bit(9)) ? spareDeployed_dmiBus4; - - /** IOMCFIR_1[10] - * MCS4 Max Spares Exceeded - */ - (IomcFir_1, bit(10)) ? maxSparesExceeded_dmiBus4; - - /** IOMCFIR_1[11] - * MCS4 Recalibration or Dynamic Repair Error - */ - (IomcFir_1, bit(11)) ? calloutDmiBus4Th1; - - /** IOMCFIR_1[12] - * MCS4 Too Many Bus Errors - */ - (IomcFir_1, bit(12)) ? calloutDmiBus4Th1; - - /** IOMCFIR_1[13:15] - * Reserved - */ - (IomcFir_1, bit(13|14|15)) ? defaultMaskedError; - - /** IOMCFIR_1[16] - * MCS5 Training Error - */ - (IomcFir_1, bit(16)) ? defaultMaskedError; - - /** IOMCFIR_1[17] - * MCS5 Spare Deployed - */ - (IomcFir_1, bit(17)) ? spareDeployed_dmiBus5; - - /** IOMCFIR_1[18] - * MCS5 Max Spares Exceeded - */ - (IomcFir_1, bit(18)) ? maxSparesExceeded_dmiBus5; - - /** IOMCFIR_1[19] - * MCS5 Recalibration or Dynamic Repair Error - */ - (IomcFir_1, bit(19)) ? calloutDmiBus5Th1; - - /** IOMCFIR_1[20] - * MCS5 Too Many Bus Errors - */ - (IomcFir_1, bit(20)) ? calloutDmiBus5Th1; - - /** IOMCFIR_1[21:23] - * Reserved - */ - (IomcFir_1, bit(21|22|23)) ? defaultMaskedError; - - /** IOMCFIR_1[24] - * MCS6 Training Error - */ - (IomcFir_1, bit(24)) ? defaultMaskedError; - - /** IOMCFIR_1[25] - * MCS6 Spare Deployed - */ - (IomcFir_1, bit(25)) ? spareDeployed_dmiBus6; - - /** IOMCFIR_1[26] - * MCS6 Max Spares Exceeded - */ - (IomcFir_1, bit(26)) ? maxSparesExceeded_dmiBus6; - - /** IOMCFIR_1[27] - * MCS6 Recalibration or Dynamic Repair Error - */ - (IomcFir_1, bit(27)) ? calloutDmiBus6Th1; - - /** IOMCFIR_1[28] - * MCS6 Too Many Bus Errors - */ - (IomcFir_1, bit(28)) ? calloutDmiBus6Th1; - - /** IOMCFIR_1[29:31] - * Reserved - */ - (IomcFir_1, bit(29|30|31)) ? defaultMaskedError; - - /** IOMCFIR_1[32] - * MCS7 Training Error - */ - (IomcFir_1, bit(32)) ? defaultMaskedError; - - /** IOMCFIR_1[33] - * MCS7 Spare Deployed - */ - (IomcFir_1, bit(33)) ? spareDeployed_dmiBus7; - - /** IOMCFIR_1[34] - * MCS7 Max Spares Exceeded - */ - (IomcFir_1, bit(34)) ? maxSparesExceeded_dmiBus7; - - /** IOMCFIR_1[35] - * MCS7 Recalibration or Dynamic Repair Error - */ - (IomcFir_1, bit(35)) ? calloutDmiBus7Th1; - - /** IOMCFIR_1[36] - * MCS7 Too Many Bus Errors - */ - (IomcFir_1, bit(36)) ? calloutDmiBus7Th1; - - /** IOMCFIR_1[37:39] - * Reserved - */ - (IomcFir_1, bit(37|38|39)) ? defaultMaskedError; - - /** IOMCFIR_1[40:47] - * FIR_RX_BUS4 unused - */ - (IomcFir_1, bit(40|41|42|43|44|45|46|47)) ? defaultMaskedError; - - /** IOMCFIR_1[48] - * FIR_SCOMFIR_ERROR - */ - (IomcFir_1, bit(48)) ? defaultMaskedError; - - /** IOMCFIR_1[49] - * FIR_SCOMFIR_ERROR_CLONE - */ - (IomcFir_1, bit(49)) ? defaultMaskedError; -}; - -################################################################################ -# Actions specific to PB chiplet -################################################################################ - -/** Callout the connected PCI 0 controller. */ -actionclass calloutConnPci0NoGard -{ - callout(connected(TYPE_PCI,0), MRU_MED, NO_GARD); -}; - -/** Callout the connected PCI 1 controller. */ -actionclass calloutConnPci1NoGard -{ - callout(connected(TYPE_PCI,1), MRU_MED, NO_GARD); -}; - -/** Callout the connected PCI 2 controller. */ -actionclass calloutConnPci2NoGard -{ - callout(connected(TYPE_PCI,2), MRU_MED, NO_GARD); -}; - -/** Callout the connected PCI 3 controller. */ -actionclass calloutConnPci3NoGard -{ - callout(connected(TYPE_PCI,3), MRU_MED, NO_GARD); -}; - -/** Callout the connected PCI 0 controller, threshold 1 , no garding */ -actionclass calloutConnPci0Th1NoGard -{ - calloutConnPci0NoGard; - threshold1; -}; - -/** Callout the connected PCI 1 controller, threshold 1, no garding */ -actionclass calloutConnPci1Th1NoGard -{ - callout(connected(TYPE_PCI,1), MRU_MED, NO_GARD); - threshold1; -}; - -/** Callout the connected PCI 2 controller, threshold 1, no garding */ -actionclass calloutConnPci2Th1NoGard -{ - calloutConnPci2NoGard; - threshold1; -}; - -/** Callout the connected PCI 3 controller, threshold 1, no garding */ -actionclass calloutConnPci3Th1NoGard -{ - calloutConnPci3NoGard; - threshold1; -}; - -/** Callout the connected PCI 0 controller, threshold 32 per day, no garding */ -actionclass calloutConnPci0Th32NoGard -{ - calloutConnPci0NoGard; - threshold32pday; -}; - -/** Callout the connected PCI 1 controller, threshold 32 per day, no garding */ -actionclass calloutConnPci1Th32NoGard -{ - calloutConnPci1NoGard; - threshold32pday; -}; - -/** Callout the connected PCI 2 controller, threshold 32 per day , no garding */ -actionclass calloutConnPci2Th32NoGard -{ - calloutConnPci2NoGard; - threshold32pday; -}; - -/** Callout the connected PCI 3 controller, threshold 32 per day , no garding */ -actionclass calloutConnPci3Th32NoGard -{ - calloutConnPci3NoGard; - threshold32pday; -}; - -/** Callout the DMI bus 0 */ -actionclass calloutDmiBus0 -{ - callout(connected(TYPE_MCS, 0), MRU_MEDA); - callout(connected(TYPE_MEMBUF, 0), MRU_MEDA); - funccall("calloutInterface_dmi0"); -}; - -/** Callout the DMI bus 1 */ -actionclass calloutDmiBus1 -{ - callout(connected(TYPE_MCS, 1), MRU_MEDA); - callout(connected(TYPE_MEMBUF, 1), MRU_MEDA); - funccall("calloutInterface_dmi1"); -}; - -/** Callout the DMI bus 2 */ -actionclass calloutDmiBus2 -{ - callout(connected(TYPE_MCS, 2), MRU_MEDA); - callout(connected(TYPE_MEMBUF, 2), MRU_MEDA); - funccall("calloutInterface_dmi2"); -}; - -/** Callout the DMI bus 3 */ -actionclass calloutDmiBus3 -{ - callout(connected(TYPE_MCS, 3), MRU_MEDA); - callout(connected(TYPE_MEMBUF, 3), MRU_MEDA); - funccall("calloutInterface_dmi3"); -}; - -/** Callout the DMI bus 4 */ -actionclass calloutDmiBus4 -{ - callout(connected(TYPE_MCS, 4), MRU_MEDA); - callout(connected(TYPE_MEMBUF, 4), MRU_MEDA); - funccall("calloutInterface_dmi4"); -}; - -/** Callout the DMI bus 5 */ -actionclass calloutDmiBus5 -{ - callout(connected(TYPE_MCS, 5), MRU_MEDA); - callout(connected(TYPE_MEMBUF, 5), MRU_MEDA); - funccall("calloutInterface_dmi5"); -}; - -/** Callout the DMI bus 6 */ -actionclass calloutDmiBus6 -{ - callout(connected(TYPE_MCS, 6), MRU_MEDA); - callout(connected(TYPE_MEMBUF, 6), MRU_MEDA); - funccall("calloutInterface_dmi6"); -}; - -/** Callout the DMI bus 7 */ -actionclass calloutDmiBus7 -{ - callout(connected(TYPE_MCS, 7), MRU_MEDA); - callout(connected(TYPE_MEMBUF, 7), MRU_MEDA); - funccall("calloutInterface_dmi7"); -}; - -/** Callout the DMI bus 0, threshold 1 */ -actionclass calloutDmiBus0Th1 { calloutDmiBus0; threshold1; }; - -/** Callout the DMI bus 1, threshold 1 */ -actionclass calloutDmiBus1Th1 { calloutDmiBus1; threshold1; }; - -/** Callout the DMI bus 2, threshold 1 */ -actionclass calloutDmiBus2Th1 { calloutDmiBus2; threshold1; }; - -/** Callout the DMI bus 3, threshold 1 */ -actionclass calloutDmiBus3Th1 { calloutDmiBus3; threshold1; }; - -/** Callout the DMI bus 4, threshold 1 */ -actionclass calloutDmiBus4Th1 { calloutDmiBus4; threshold1; }; - -/** Callout the DMI bus 5, threshold 1 */ -actionclass calloutDmiBus5Th1 { calloutDmiBus5; threshold1; }; - -/** Callout the DMI bus 6, threshold 1 */ -actionclass calloutDmiBus6Th1 { calloutDmiBus6; threshold1; }; - -/** Callout the DMI bus 7, threshold 1 */ -actionclass calloutDmiBus7Th1 { calloutDmiBus7; threshold1; }; - -/** Lane Repair: spare deployed - DMI bus 0 */ -actionclass spareDeployed_dmiBus0 -{ calloutDmiBus0; funccall("spareDeployed_dmiBus0"); }; - -/** Lane Repair: spare deployed - DMI bus 1 */ -actionclass spareDeployed_dmiBus1 -{ calloutDmiBus1; funccall("spareDeployed_dmiBus1"); }; - -/** Lane Repair: spare deployed - DMI bus 2 */ -actionclass spareDeployed_dmiBus2 -{ calloutDmiBus2; funccall("spareDeployed_dmiBus2"); }; - -/** Lane Repair: spare deployed - DMI bus 3 */ -actionclass spareDeployed_dmiBus3 -{ calloutDmiBus3; funccall("spareDeployed_dmiBus3"); }; - -/** Lane Repair: spare deployed - DMI bus 4 */ -actionclass spareDeployed_dmiBus4 -{ calloutDmiBus4; funccall("spareDeployed_dmiBus4"); }; - -/** Lane Repair: spare deployed - DMI bus 5 */ -actionclass spareDeployed_dmiBus5 -{ calloutDmiBus5; funccall("spareDeployed_dmiBus5"); }; - -/** Lane Repair: spare deployed - DMI bus 6 */ -actionclass spareDeployed_dmiBus6 -{ calloutDmiBus6; funccall("spareDeployed_dmiBus6"); }; - -/** Lane Repair: spare deployed - DMI bus 7 */ -actionclass spareDeployed_dmiBus7 -{ calloutDmiBus7; funccall("spareDeployed_dmiBus7"); }; - -/** Lane Repair: max spares exceeded - DMI bus 0 */ -actionclass maxSparesExceeded_dmiBus0 -{ calloutDmiBus0Th1; funccall("maxSparesExceeded_dmiBus0"); }; - -/** Lane Repair: max spares exceeded - DMI bus 1 */ -actionclass maxSparesExceeded_dmiBus1 -{ calloutDmiBus1Th1; funccall("maxSparesExceeded_dmiBus1"); }; - -/** Lane Repair: max spares exceeded - DMI bus 2 */ -actionclass maxSparesExceeded_dmiBus2 -{ calloutDmiBus2Th1; funccall("maxSparesExceeded_dmiBus2"); }; - -/** Lane Repair: max spares exceeded - DMI bus 3 */ -actionclass maxSparesExceeded_dmiBus3 -{ calloutDmiBus3Th1; funccall("maxSparesExceeded_dmiBus3"); }; - -/** Lane Repair: max spares exceeded - DMI bus 4 */ -actionclass maxSparesExceeded_dmiBus4 -{ calloutDmiBus4Th1; funccall("maxSparesExceeded_dmiBus4"); }; - -/** Lane Repair: max spares exceeded - DMI bus 5 */ -actionclass maxSparesExceeded_dmiBus5 -{ calloutDmiBus5Th1; funccall("maxSparesExceeded_dmiBus5"); }; - -/** Lane Repair: max spares exceeded - DMI bus 6 */ -actionclass maxSparesExceeded_dmiBus6 -{ calloutDmiBus6Th1; funccall("maxSparesExceeded_dmiBus6"); }; - -/** Lane Repair: max spares exceeded - DMI bus 7 */ -actionclass maxSparesExceeded_dmiBus7 -{ calloutDmiBus7Th1; funccall("maxSparesExceeded_dmiBus7"); }; - -/** callout NX associated with Proc with a threshold of 32 per day*/ -actionclass calloutNxThr32 -{ - calloutNx; - threshold32pday; -}; - -/** callout NX associated with Proc with a threshold of 1 per day*/ -actionclass calloutNxThr1 -{ - calloutNx; - threshold1; -}; - -/**callout Nx connected to Proc */ -actionclass calloutNx -{ - callout(connected(TYPE_NX, 0), MRU_MED); -}; - -actionclass calloutNxThr5pHr -{ - calloutNx; - threshold5phour; -}; - -actionclass Capp0MedThr1 -{ - calloutCapp0; - threshold1; -}; - -actionclass Capp0MedThr32PerDay -{ - calloutCapp0; - threshold32pday; -}; - -actionclass Capp1MedThr1 -{ - calloutCapp1; - threshold1; -}; - -actionclass Capp1MedThr32PerDay -{ - calloutCapp1; - threshold32pday; -}; - -actionclass calloutCapp0 -{ - callout(connected(TYPE_CAPP, 0), MRU_MED); -}; - -actionclass calloutCapp1 -{ - callout(connected(TYPE_CAPP, 1), MRU_MED); -}; - - -actionclass combinedResponseError -{ - callout2ndLvlMed; - # TODO: RTC 116213 proc_mpipl_check_eligibility() is completely broken so - # reverting this bug fix to the original 810 and 820 behavior (per - # request from Kevin) until proc_mpipl_check_eligibility() is fixed - # in FW830. - funccall("analyzeMpIPL"); - #dumpSH; - funccall("combinedResponseCallout"); -}; - -actionclass forceMpIpl -{ - # TODO: RTC 116213 proc_mpipl_check_eligibility() is completely broken so - # reverting this bug fix to the original 810 and 820 behavior (per - # request from Kevin) until proc_mpipl_check_eligibility() is fixed - # in FW830. - funccall("analyzeMpIPL"); - #dumpSH; - callout2ndLvlMedThr1; -}; - -/** callout both ends of PSI Link.Threshold is 32 events per day. - */ -actionclass calloutPsiThr32 -{ - calloutPsiLink; - threshold32pday; -}; - -/** callout both ends of PSI Link on first instance.*/ -actionclass calloutPsiThr1 -{ - calloutPsiLink; - threshold1; -}; - -/** callout both ends of PSI link */ -actionclass calloutPsiLink -{ - funccall("calloutPeerPsiBusTgt"); -}; - -/** Callout the NX on first occurrence and collect additional FFDC. */ -actionclass nxUnitCheckstop -{ - calloutNxThr1; - flag(UNIT_CS); - # only collect NX debug traces on FSP - try(funccall("inHostboot"), funccall("collectNxTraceArray")); -}; - -/** - * Threshold 32/day (field) and 1 (mnfg). Do not predictively callout on - * threshold, instead just mask. - */ -actionclass PbCentHangRecoveryGte -{ - capture(PbCentMode); - calloutSelfMed; - threshold32pday; - funccall("ClearServiceCallFlag_mnfgInfo"); -}; - diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PCIE.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PCIE.rule deleted file mode 100755 index 1c58a3719..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PCIE.rule +++ /dev/null @@ -1,409 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PCIE.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2015 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -################################################################################ -# PCIE Chiplet Registers -################################################################################ - -rule PcieChipletFir -{ - CHECK_STOP: - (PCIE_CHIPLET_CS_FIR & `1FF0000000000000`) & ~PCIE_CHIPLET_FIR_MASK; - RECOVERABLE: - ((PCIE_CHIPLET_RE_FIR >> 2) & `1FF0000000000000`) & ~PCIE_CHIPLET_FIR_MASK; -}; - -group gPcieChipletFir filter singlebit -{ - /** PCIE_CHIPLET_FIR[3] - * Attention from LFIR - */ - (PcieChipletFir, bit(3)) ? analyze(gPcieLFir); - - /** PCIE_CHIPLET_FIR[4|5|6|7] - * Attention from PCICLOCKFIR (0-3) - */ - (PcieChipletFir, bit(4|5|6|7)) ? defaultMaskedError; - - /** PCIE_CHIPLET_FIR[8] - * Attention from PBFFIR - */ - #PBFFIR has been masked. Retaining the register for FFDC purpose. - (PcieChipletFir, bit(8)) ? defaultMaskedError; - - /** PCIE_CHIPLET_FIR[9|10] - * Attention from IOPCIFIR (0-1) - */ - (PcieChipletFir, bit(9|10)) ? analyze(gIopPciFir); - - /** PCIE_CHIPLET_FIR[11] - * Attention from IOPCIFIR_2 - */ - (PcieChipletFir, bit(11)) ? analyze(gIopPciFir_2); -}; - -rule PcieChipletSpa -{ - SPECIAL: PCIE_CHIPLET_SPA & ~PCIE_CHIPLET_SPA_MASK; -}; - -group gPcieChipletSpa filter singlebit -{ - /** PCIE_CHIPLET_SPA[0] - * Attention from PBFFIR - */ - (PcieChipletSpa, bit(0)) ? defaultMaskedError; -}; - -################################################################################ -# PCIE Chiplet LFIR -################################################################################ -# based on p8dd1_mss_FFDC_59.xls -################################################################################ - -rule PcieLFir -{ - CHECK_STOP: PCIE_LFIR & ~PCIE_LFIR_MASK & ~PCIE_LFIR_ACT0 & ~PCIE_LFIR_ACT1; - RECOVERABLE: PCIE_LFIR & ~PCIE_LFIR_MASK & ~PCIE_LFIR_ACT0 & PCIE_LFIR_ACT1; -}; - -group gPcieLFir filter singlebit -{ - /** PCIE_LFIR[0] - * CFIR internal parity error - */ - (PcieLFir, bit(0)) ? SelfHighThr32PerDay; - - /** PCIE_LFIR[1] - * Local errors from GPIO (PCB error) - */ - (PcieLFir, bit(1)) ? defaultMaskedError; - - /** PCIE_LFIR[2] - * Local errors from CC (PCB error) - */ - (PcieLFir, bit(2)) ? defaultMaskedError; - - /** PCIE_LFIR[3] - * Local errors from CC (OPCG, parity, scan collision, ...) - */ - (PcieLFir, bit(3)) ? callout2ndLvlMedThr32; - - /** PCIE_LFIR[4] - * Local errors from PSC (PCB error) - */ - (PcieLFir, bit(4)) ? defaultMaskedError; - - /** PCIE_LFIR[5] - * Local errors from PSC (parity error) - */ - (PcieLFir, bit(5)) ? defaultMaskedError; - - /** PCIE_LFIR[6] - * Local errors from Thermal (parity error) - */ - (PcieLFir, bit(6)) ? defaultMaskedError; - - /** PCIE_LFIR[7] - * Local errors from Thermal (PCB error) - */ - (PcieLFir, bit(7)) ? defaultMaskedError; - - /** PCIE_LFIR[8|9] - * Local errors from Thermal (Trip error) - */ - (PcieLFir, bit(8|9)) ? defaultMaskedError; - - /** PCIE_LFIR[10|11] - * Local errors from Trace Array ( error) - */ - (PcieLFir, bit(10|11)) ? defaultMaskedError; - - /** PCIE_LFIR[12:20] - * Unused local errors - */ - (PcieLFir, bit(12|13|14|15|16|17|18|19|20)) ? defaultMaskedError; - - /** PCIE_LFIR[21:30] - * Unused local errors - */ - (PcieLFir, bit(21|22|23|24|25|26|27|28|29|30)) ? defaultMaskedError; - - /** PCIE_LFIR[31:39] - * Unused local errors - */ - (PcieLFir, bit(31|32|33|34|35|36|37|38|39)) ? defaultMaskedError; - - /** PCIE_LFIR[40] - * Malfunction alert (local xstop in another chiplet) - */ - (PcieLFir, bit(40)) ? defaultMaskedError; -}; - -################################################################################ -# PCIE Chiplet IOPCIFIRs -################################################################################ - -# All these FIRs should have the same bit definition. Ideally, we want -# to have only one copy of the bit definition. Currently rule code -# parser does not have the support for something like this. -# Maybe we can add this as a later feature. - -################################################################################ -# based on p8dd1_mss_FFDC_59.xls -################################################################################ - -rule IopPciFir_0 -{ - CHECK_STOP: - IOPCIFIR_0 & ~IOPCIFIR_0_MASK & ~IOPCIFIR_0_ACT0 & ~IOPCIFIR_0_ACT1; - RECOVERABLE: - IOPCIFIR_0 & ~IOPCIFIR_0_MASK & ~IOPCIFIR_0_ACT0 & IOPCIFIR_0_ACT1; -}; - -rule IopPciFir_1 -{ - CHECK_STOP: - IOPCIFIR_1 & ~IOPCIFIR_1_MASK & ~IOPCIFIR_1_ACT0 & ~IOPCIFIR_1_ACT1; - RECOVERABLE: - IOPCIFIR_1 & ~IOPCIFIR_1_MASK & ~IOPCIFIR_1_ACT0 & IOPCIFIR_1_ACT1; -}; - -group gIopPciFir filter singlebit -{ - /** IOPCIFIR_0[0] - * FIR_STATUS_REG_G2_PLL_CCERR_STATUS - */ - (IopPciFir_0, bit(0)) ? calloutPhbBothClks_0; - - /** IOPCIFIR_1[0] - * FIR_STATUS_REG_G2_PLL_CCERR_STATUS - */ - (IopPciFir_1, bit(0)) ? calloutPhbBothClks_1; - - /** IOPCIFIR_0[1] - * FIR_STATUS_REG_G3_PLL_CCERR_STATUS - */ - (IopPciFir_0, bit(1)) ? calloutPhbBothClks_0; - - /** IOPCIFIR_1[1] - * FIR_STATUS_REG_G3_PLL_CCERR_STATUS - */ - (IopPciFir_1, bit(1)) ? calloutPhbBothClks_1; - - /** IOPCIFIR_0[2] - * FIR_STATUS_REG_TX_A_ERR_STATUS - */ - (IopPciFir_0, bit(2)) ? calloutPhbClkA_0_noGard; - - /** IOPCIFIR_1[2] - * FIR_STATUS_REG_TX_A_ERR_STATUS - */ - (IopPciFir_1, bit(2)) ? calloutPhbClkA_1_noGard; - - /** IOPCIFIR_0[3] - * FIR_STATUS_REG_TX_B_ERR_STATUS - */ - (IopPciFir_0, bit(3)) ? calloutPhbClkB_0_noGard; - - /** IOPCIFIR_1[3] - * FIR_STATUS_REG_TX_B_ERR_STATUS - */ - (IopPciFir_1, bit(3)) ? calloutPhbClkB_1_noGard; - - /** IOPCIFIR_0[4] - * FIR_STATUS_REG_RX_A_ERR_STATUS - */ - (IopPciFir_0, bit(4)) ? calloutPhbClkA_0_noGard; - - /** IOPCIFIR_1[4] - * FIR_STATUS_REG_RX_A_ERR_STATUS - */ - (IopPciFir_1, bit(4)) ? calloutPhbClkA_1_noGard; - - /** IOPCIFIR_0[5] - * FIR_STATUS_REG_RX_B_ERR_STATUS - */ - (IopPciFir_0, bit(5)) ? calloutPhbClkB_0_noGard; - - /** IOPCIFIR_1[5] - * FIR_STATUS_REG_RX_B_ERR_STATUS - */ - (IopPciFir_1, bit(5)) ? calloutPhbClkB_1_noGard; - - /** IOPCIFIR_0[6] - * FIR_STATUS_REG_ZCAL_B_ERR_STATUS - */ - (IopPciFir_0, bit(6)) ? calloutPhbBothClks_0; - - /** IOPCIFIR_1[6] - * FIR_STATUS_REG_ZCAL_B_ERR_STATUS - */ - (IopPciFir_1, bit(6)) ? calloutPhbBothClks_1; - - /** IOPCIFIR_0[7] - * FIR_STATUS_REG_SCOM_FIR_PERR0_STATUS - */ - (IopPciFir_0, bit(7)) ? defaultMaskedError; - - /** IOPCIFIR_1[7] - * FIR_STATUS_REG_SCOM_FIR_PERR0_STATUS - */ - (IopPciFir_1, bit(7)) ? defaultMaskedError; - - /** IOPCIFIR_0[8] - * FIR_STATUS_REG_SCOM_FIR_PERR1_STATUS - */ - (IopPciFir_0, bit(8)) ? defaultMaskedError; - - /** IOPCIFIR_1[8] - * FIR_STATUS_REG_SCOM_FIR_PERR1_STATUS - */ - (IopPciFir_1, bit(8)) ? defaultMaskedError; -}; - -rule IopPciFir_2 -{ - CHECK_STOP: - IOPCIFIR_2 & ~IOPCIFIR_2_MASK & ~IOPCIFIR_2_ACT0 & ~IOPCIFIR_2_ACT1; - RECOVERABLE: - IOPCIFIR_2 & ~IOPCIFIR_2_MASK & ~IOPCIFIR_2_ACT0 & IOPCIFIR_2_ACT1; -}; - -group gIopPciFir_2 filter singlebit -{ - /** IOPCIFIR_2[0] - * FIR_STATUS_REG_G2_PLL_CCERR_STATUS - */ - (IopPciFir_2, bit(0)) ? calloutPhbBothClks_2; - - /** IOPCIFIR_2[1] - * FIR_STATUS_REG_G3_PLL_CCERR_STATUS - */ - (IopPciFir_2, bit(1)) ? calloutPhbBothClks_2; - - /** IOPCIFIR_2[2] - * FIR_STATUS_REG_TX_A_ERR_STATUS - */ - (IopPciFir_2, bit(2)) ? calloutPhbClkA_2_noGard; - - /** IOPCIFIR_2[3] - * FIR_STATUS_REG_TX_B_ERR_STATUS - */ - (IopPciFir_2, bit(3)) ? calloutPhbClkB_2_noGard; - - /** IOPCIFIR_2[4] - * FIR_STATUS_REG_RX_A_ERR_STATUS - */ - (IopPciFir_2, bit(4)) ? calloutPhbClkA_2_noGard; - - /** IOPCIFIR_2[5] - * FIR_STATUS_REG_RX_B_ERR_STATUS - */ - (IopPciFir_2, bit(5)) ? calloutPhbClkB_2_noGard; - - /** IOPCIFIR_2[6] - * FIR_STATUS_REG_ZCAL_B_ERR_STATUS - */ - (IopPciFir_2, bit(6)) ? calloutPhbBothClks_2; - - /** IOPCIFIR_2[7] - * FIR_STATUS_REG_SCOM_FIR_PERR0_STATUS - */ - (IopPciFir_2, bit(7)) ? defaultMaskedError; - - /** IOPCIFIR_2[8] - * FIR_STATUS_REG_SCOM_FIR_PERR1_STATUS - */ - (IopPciFir_2, bit(8)) ? defaultMaskedError; -}; - -################################################################################ -# Actions specific to PCIE chiplet -################################################################################ - -/**callout PHB associated with IOPCIFIR0 clkA, no garding */ -actionclass calloutPhbClkA_0_noGard -{ - funccall("calloutPhbClkA_0"); - threshold1; -}; - -/**callout PHB associated with IOPCIFIR0 clkB, no garding */ -actionclass calloutPhbClkB_0_noGard -{ - funccall("calloutPhbClkB_0"); - threshold1; -}; - -/**callout PHB associated with IOPCIFIR1 clkA, no garding */ -actionclass calloutPhbClkA_1_noGard -{ - funccall("calloutPhbClkA_1"); - threshold1; -}; - -/**callout PHB associated with IOPCIFIR1 clkB, no garding */ -actionclass calloutPhbClkB_1_noGard -{ - funccall("calloutPhbClkB_1"); - threshold1; -}; - -/**callout PHB associated with IOPCIFIR2 clkA, no garding */ -actionclass calloutPhbClkA_2_noGard -{ - funccall("calloutPhbClkA_2"); - threshold1; -}; - -/**callout PHB associated with IOPCIFIR2 clkB, no garding */ -actionclass calloutPhbClkB_2_noGard -{ - funccall("calloutPhbClkB_2"); - threshold1; -}; - -/** callout all PHB associated with IOPCIFIR0, no garding */ -actionclass calloutPhbBothClks_0 -{ - funccall("calloutPhbBothClks_0"); - threshold1; -}; - -/** callout all PHB associated with IOPCIFIR1, no garding */ -actionclass calloutPhbBothClks_1 -{ - funccall("calloutPhbBothClks_1"); - threshold1; -}; - -/** callout all PHB associated with IOPCIFIR2, no garding */ -actionclass calloutPhbBothClks_2 -{ - funccall("calloutPhbBothClks_2"); - threshold1; -}; - diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_TP.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_TP.rule deleted file mode 100755 index 599ee06fb..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_TP.rule +++ /dev/null @@ -1,1332 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc_acts_TP.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2017 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -################################################################################ -# TP Chiplet Registers -################################################################################ - -rule TpChipletFir -{ - CHECK_STOP: - (TP_CHIPLET_CS_FIR & `1FFFF80000000000`) & ~TP_CHIPLET_FIR_MASK; - RECOVERABLE: - ((TP_CHIPLET_RE_FIR >> 2) & `1FFFF80000000000`) & ~TP_CHIPLET_FIR_MASK; -}; - -group gTpChipletFir filter singlebit -{ - /** TP_CHIPLET_FIR[3] - * Attention from TP_LFIR - */ - (TpChipletFir, bit(3)) ? analyze(gTpLFir); - - /** TP_CHIPLET_FIR[4] - * Attention from OCCFIR - */ - (TpChipletFir, bit(4)) ? analyze(gOccFir); - - /** TP_CHIPLET_FIR[5] - * Attention from MCIFIR (MCS 00 not used in Murano) - */ - (TpChipletFir, bit(5)) ? analyzeMcs00; - - /** TP_CHIPLET_FIR[6] - * Attention from MCIFIR (MCS 01 not used in Murano) - */ - (TpChipletFir, bit(6)) ? analyzeMcs01; - - /** TP_CHIPLET_FIR[7] - * Attention from MCIFIR (MCS 10 not used in Murano) - */ - (TpChipletFir, bit(7)) ? analyzeMcs10; - - /** TP_CHIPLET_FIR[8] - * Attention from MCIFIR (MCS 11 not used in Murano) - */ - (TpChipletFir, bit(8)) ? analyzeMcs11; - - /** TP_CHIPLET_FIR[9] - * Attention from MCIFIR (MCS 20) - */ - (TpChipletFir, bit(9)) ? analyzeMcs20; - - /** TP_CHIPLET_FIR[10] - * Attention from MCIFIR (MCS 21) - */ - (TpChipletFir, bit(10)) ? analyzeMcs21; - - /** TP_CHIPLET_FIR[11] - * Attention from MCIFIR (MCS 30) - */ - (TpChipletFir, bit(11)) ? analyzeMcs30; - - /** TP_CHIPLET_FIR[12] - * Attention from MCIFIR (MCS 31) - */ - (TpChipletFir, bit(12)) ? analyzeMcs31; - - /** TP_CHIPLET_FIR[13] - * Attention from IOMCFIR_0 (not used in Murano) - */ - (TpChipletFir, bit(13)) ? analyze(gIomcFir_0); - - /** TP_CHIPLET_FIR[14] - * Attention from IOMCFIR_1 - */ - (TpChipletFir, bit(14)) ? analyze(gIomcFir_1); - - /** TP_CHIPLET_FIR[15] - * Attention from PBAMFIR - */ - (TpChipletFir, bit(15)) ? analyze(gPbamFir); - - /** TP_CHIPLET_FIR[16|17|18|19] - * CS attention from MC 0-3 - */ - (TpChipletFir, bit(16|17|18|19)) ? defaultMaskedError; - - /** TP_CHIPLET_FIR[20] - * Attention from PMCFIR - */ - (TpChipletFir, bit(20)) ? analyze(gPmcFir); -}; - -rule TpChipletSpa -{ - SPECIAL: TP_CHIPLET_SPA & ~TP_CHIPLET_SPA_MASK; -}; - -group gTpChipletSpa filter singlebit -{ - /** TP_CHIPLET_SPA[0] - * Attention from OCCFIR - */ - (TpChipletSpa, bit(0)) ? analyze(gOccFir); - - /** TP_CHIPLET_SPA[1] - * Attention from MCIFIR_00 (not used in Murano) - */ - (TpChipletSpa, bit(1)) ? analyzeMcs00; - - /** TP_CHIPLET_SPA[2] - * Attention from MCIFIR_01 (not used in Murano) - */ - (TpChipletSpa, bit(2)) ? analyzeMcs01; - - /** TP_CHIPLET_SPA[3] - * Attention from MCIFIR_10 (not used in Murano) - */ - (TpChipletSpa, bit(3)) ? analyzeMcs10; - - /** TP_CHIPLET_SPA[4] - * Attention from MCIFIR_11 (not used in Murano) - */ - (TpChipletSpa, bit(4)) ? analyzeMcs11; - - /** TP_CHIPLET_SPA[5] - * Attention from MCIFIR_20 - */ - (TpChipletSpa, bit(5)) ? analyzeMcs20; - - /** TP_CHIPLET_SPA[6] - * Attention from MCIFIR_21 - */ - (TpChipletSpa, bit(6)) ? analyzeMcs21; - - /** TP_CHIPLET_SPA[7] - * Attention from MCIFIR_30 - */ - (TpChipletSpa, bit(7)) ? analyzeMcs30; - - /** TP_CHIPLET_SPA[8] - * Attention from MCIFIR_31 - */ - (TpChipletSpa, bit(8)) ? analyzeMcs31; -}; - -################################################################################ -# TP Chiplet LFIR -################################################################################ - -rule TpLFir -{ - CHECK_STOP: TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & ~TP_LFIR_ACT1; - RECOVERABLE: TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & TP_LFIR_ACT1; -}; - -group gTpLFir filter singlebit, secondarybits( 16, 17, 18 ) -{ - /** TP_LFIR[0] - * CFIR internal parity error - */ - (TpLFir, bit(0)) ? SelfHighThr32PerDay; - - /** TP_LFIR[1] - * Local errors from GPIO (PCB error) - */ - (TpLFir, bit(1)) ? defaultMaskedError; - - /** TP_LFIR[2] - * Local errors from CC (PCB error) - */ - (TpLFir, bit(2)) ? defaultMaskedError; - - /** TP_LFIR[3] - * Local errors from CC (OPCG, parity, scan collision, ...) - */ - (TpLFir, bit(3)) ? SelfHighThr32PerDay; - - /** TP_LFIR[4] - * Local errors from PSC (PCB error) - */ - (TpLFir, bit(4)) ? defaultMaskedError; - - /** TP_LFIR[5] - * Local errors from PSC (parity error) - */ - (TpLFir, bit(5)) ? defaultMaskedError; - - /** TP_LFIR[6] - * Local errors from Thermal (parity error) - */ - (TpLFir, bit(6)) ? defaultMaskedError; - - /** TP_LFIR[7] - * Local errors from Thermal (PCB error) - */ - (TpLFir, bit(7)) ? defaultMaskedError; - - /** TP_LFIR[8|9] - * Local errors from Thermal (Trip error) - */ - (TpLFir, bit(8|9)) ? defaultMaskedError; - - /** TP_LFIR[10] - * Local errors from Trace Array ( error) - */ - (TpLFir, bit(10)) ? SelfHighThr32PerDay; - - /** TP_LFIR[11] - * Local errors from Trace Array ( error) - */ - (TpLFir, bit(11)) ? SelfHighThr32PerDay; - - /** TP_LFIR[12|13] - * Local errors from I2CM - */ - (TpLFir, bit(12|13)) ? defaultMaskedError; - - /** TP_LFIR[14] - * Local errors from PCB - */ - (TpLFir, bit(14)) ? SelfHighThr32PerDay; - - /** TP_LFIR[15] - * Local errors from Trace Array ( error) - */ - (TpLFir, bit(15)) ? defaultMaskedError; - - /** TP_LFIR[16] - * Error in TOD backup topology - */ - (TpLFir, bit(16)) ? analyzeTodBackupTopology; - - /** TP_LFIR[17] - * TOD PIB Errors - */ - (TpLFir, bit(17)) ? analyzePibError; - - /** TP_LFIR[18] - * PHYP detected TOD Error - */ - (TpLFir, bit(18)) ? analyzePhypTodError; - - /** TP_LFIR[19] - * PCB Slave Internal Parity Error - * - * This bit is also shared with the PLL Lock error. - * PLL error should already be handled by global PRD PLL code. - */ - (TpLFir, bit(19)) ? PcbSlaveInternalParity; - - /** TP_LFIR[20] - * Sbe indicated error_event0to4 enabled by mask bit 5 to 9 - */ - (TpLFir, bit(20)) ? defaultMaskedError; - - /** TP_LFIR[21] - * Sbe indicated error_event0to4 enabled by mask bit 10 to 14 - */ - (TpLFir, bit(21)) ? defaultMaskedError; - - /** TP_LFIR[22|23] - * local errors from I2CS - */ - (TpLFir, bit(22|23)) ? defaultMaskedError; - - /** TP_LFIR[24] - * Local errors from OTP - */ - (TpLFir, bit(24)) ? SelfHighThr1; - - /** TP_LFIR[25] - * local error from Ext trigger - */ - (TpLFir, bit(25)) ? defaultMaskedError; - - /** TP_LFIR[26] - * Fast xstop fir error - */ - (TpLFir, bit(26)) ? defaultMaskedError; - - /** TP_LFIR[27] - * PCB mcast grp error - */ - (TpLFir, bit(27)) ? SelfHighThr1; - - /** TP_LFIR[28] - * PCB Parity error - */ - (TpLFir, bit(28)) ? defaultMaskedError; - - /** TP_LFIR[29|30] - * EECB lpc fir error - */ - (TpLFir, bit(29|30)) ? defaultMaskedError; - - /** TP_LFIR[31|32] - * EECB i2c fir error - */ - (TpLFir, bit(31|32)) ? defaultMaskedError; - - /** TP_LFIR[33|34] - * Local errors from PIBMEM - */ - (TpLFir, bit(33|34)) ? defaultMaskedError; - - /** TP_LFIR[35] - * OTP correctable error - */ - (TpLFir, bit(35)) ? SelfHighThr1; - - /** TP_LFIR[36] - * Deadman Timer - */ - (TpLFir, bit(36)) ? deadManTimer; - - /** TP_LFIR[37|38|39] - * Unused error - */ - (TpLFir, bit(37|38|39)) ? defaultMaskedError; - - /** TP_LFIR[40] - * Malfunction alert - */ - (TpLFir, bit(40)) ? defaultMaskedError; - -}; - -################################################################################ -# TP Chiplet OCCFIR -################################################################################ - -rule OccFir -{ - CHECK_STOP: OCCFIR & ~OCCFIR_MASK & ~OCCFIR_ACT0 & ~OCCFIR_ACT1; - RECOVERABLE: OCCFIR & ~OCCFIR_MASK & ~OCCFIR_ACT0 & OCCFIR_ACT1; - SPECIAL: OCCFIR & ~OCCFIR_MASK & OCCFIR_ACT0 & ~OCCFIR_ACT1; -}; - -#based on spreadsheet p8dd1_mss_FFDC_51/60.xls -group gOccFir filter singlebit, - secondarybits( 10, 39 ) -{ - /** OCCFIR[0] - * Cooling system error - */ - (OccFir, bit(0)) ? coolingSystemError; - - /** OCCFIR[1] - * OCC_SCOM_OCCFIR_OCC_FW1 - */ - (OccFir, bit(1)) ? defaultMaskedError; - - /** OCCFIR[2] - * OCC_SCOM_OCCFIR_OCC_FW2 - */ - (OccFir, bit(2)) ? defaultMaskedError; - - /** OCCFIR[3] - * OCC_SCOM_OCCFIR_OCC_FW3 - */ - (OccFir, bit(3)) ? defaultMaskedError; - - /** OCCFIR[4] - * OCC_SCOM_OCCFIR_PMC_PORE_SW_MALF - */ - (OccFir, bit(4)) ? defaultMaskedError; - - /** OCCFIR[5] - * OCC_SCOM_OCCFIR_PMC_OCC_HB_MALF - */ - (OccFir, bit(5)) ? defaultMaskedError; - - /** OCCFIR[6] - * OCC_SCOM_OCCFIR_PORE_GPE0_FATAL_ERR - */ - (OccFir, bit(6)) ? defaultMaskedError; - - /** OCCFIR[7] - * OCC_SCOM_OCCFIR_PORE_GPE1_FATAL_ERR - */ - (OccFir, bit(7)) ? defaultMaskedError; - - /** OCCFIR[8] - * OCC_SCOM_OCCFIR_OCB_ERROR - */ - (OccFir, bit(8)) ? defaultMaskedError; - - /** OCCFIR[9] - * OCC_SCOM_OCCFIR_SRT_UE - */ - (OccFir, bit(9)) ? defaultMaskedError; - - /** OCCFIR[10] - * OCC_SCOM_OCCFIR_SRT_CE - */ - (OccFir, bit(10)) ? thresholdAndMask_self; - - /** OCCFIR[11] - * OCC_SCOM_OCCFIR_SRT_READ_ERROR - */ - (OccFir, bit(11)) ? defaultMaskedError; - - /** OCCFIR[12] - * OCC_SCOM_OCCFIR_SRT_WRITE_ERROR - */ - (OccFir, bit(12)) ? defaultMaskedError; - - /** OCCFIR[13] - * OCC_SCOM_OCCFIR_SRT_DATAOUT_PERR - */ - (OccFir, bit(13)) ? defaultMaskedError; - - /** OCCFIR[14] - * OCC_SCOM_OCCFIR_SRT_OCI_WRITE_DATA_PARITY - */ - (OccFir, bit(14)) ? defaultMaskedError; - - /** OCCFIR[15] - * OCC_SCOM_OCCFIR_SRT_OCI_BE_PARITY_ER - */ - (OccFir, bit(15)) ? defaultMaskedError; - - /** OCCFIR[16] - * OCC_SCOM_OCCFIR_SRT_OCI_ADDR_PARITY_ERR - */ - (OccFir, bit(16)) ? defaultMaskedError; - - /** OCCFIR[17] - * OCC_SCOM_OCCFIR_PORE_SW_ERROR_ERR - */ - (OccFir, bit(17)) ? defaultMaskedError; - - /** OCCFIR[18] - *OCC_SCOM_OCCFIR_PORE_GPE0_ERROR_ERR - */ - (OccFir, bit(18)) ? defaultMaskedError; - - /** OCCFIR[19] - * OCC_SCOM_OCCFIR_PORE_GPE1_ERROR_ERR - */ - (OccFir, bit(19)) ? defaultMaskedError; - - /** OCCFIR[20] - * OCC_SCOM_OCCFIR_EXTERNAL_TRAP - */ - (OccFir, bit(20)) ? defaultMaskedError; - - /** OCCFIR[21] - * OCC_SCOM_OCCFIR_PPC405_CORE_RESET - */ - (OccFir, bit(21)) ? defaultMaskedError; - - /** OCCFIR[22] - * OCC_SCOM_OCCFIR_PPC405_CHIP_RESET - */ - (OccFir, bit(22)) ? defaultMaskedError; - - /** OCCFIR[23] - * OCC_SCOM_OCCFIR_PPC405_SYSTEM_RESET - */ - (OccFir, bit(23)) ? defaultMaskedError; - - /** OCCFIR[24] - *OCC_SCOM_OCCFIR_PPC405_DBGMSRWE - */ - (OccFir, bit(24)) ? defaultMaskedError; - - /** OCCFIR[25] - * OCC_SCOM_OCCFIR_PPC405_DBGSTOPACK - */ - (OccFir, bit(25)) ? defaultMaskedError; - - /** OCCFIR[26] - * OCC_SCOM_OCCFIR_OCB_DB_OCI_TIMEOUT - */ - (OccFir, bit(26)) ? SelfMedThr1NoGard; - - /** OCCFIR[27] - * OCC_SCOM_OCCFIR_OCB_DB_OCI_READ_DATA_PARITY - */ - (OccFir, bit(27)) ? SelfMedThr1NoGard; - - /** OCCFIR[28] - * OCC_SCOM_OCCFIR_OCB_DB_OCI_SLAVE_ERROR - */ - (OccFir, bit(28)) ? SelfMedThr1NoGard; - - /** OCCFIR[29] - * OCC_SCOM_OCCFIR_OCB_PIB_ADDR_PARITY_ERR - */ - (OccFir, bit(29)) ? SelfMedThr1NoGard; - - /** OCCFIR[30] - * OCC_SCOM_OCCFIR_OCB_DB_PIB_DATA_PARITY_ERR - */ - (OccFir, bit(30)) ? SelfMedThr1NoGard; - - /** OCCFIR[31] - * OCC_SCOM_OCCFIR_OCB_IDC0_ERROR - */ - (OccFir, bit(31)) ? defaultMaskedError; - - /** OCCFIR[32] - * OCC_SCOM_OCCFIR_OCB_IDC1_ERROR - */ - (OccFir, bit(32)) ? defaultMaskedError; - - /** OCCFIR[33] - * OCC_SCOM_OCCFIR_OCB_IDC2_ERROR - */ - (OccFir, bit(33)) ? defaultMaskedError; - - /** OCCFIR[34] - * OCC_SCOM_OCCFIR_OCB_IDC3_ERROR - */ - (OccFir, bit(34)) ? defaultMaskedError; - - /** OCCFIR[35] - * OCC_SCOM_OCCFIR_SRT_FSM_ERR - */ - (OccFir, bit(35)) ? defaultMaskedError; - - /** OCCFIR[36] - * OCC_SCOM_OCCFIR_JTAGACC_ERR - */ - (OccFir, bit(36)) ? defaultMaskedError; - - /** OCCFIR[37] - * OCC_SCOM_OCCFIR_OCB_DW_ERR - */ - (OccFir, bit(37)) ? defaultMaskedError; - - /** OCCFIR[38] - * OCC_SCOM_OCCFIR_C405_ECC_UE - */ - (OccFir, bit(38)) ? SelfMedThr1NoGard; - - /** OCCFIR[39] - * OCC_SCOM_OCCFIR_C405_ECC_CE - */ - (OccFir, bit(39)) ? thresholdAndMask_self; - - /** OCCFIR[40] - * OCC_SCOM_OCCFIR_C405_OCI_MACHINECHECK - */ - (OccFir, bit(40)) ? defaultMaskedError; - - /** OCCFIR[41] - * OCC_SCOM_OCCFIR_SRAM_SPARE_DIRECT_ERROR0 - */ - (OccFir, bit(41)) ? defaultMaskedError; - - /** OCCFIR[42] - * OCC_SCOM_OCCFIR_SRAM_SPARE_DIRECT_ERROR1 - */ - (OccFir, bit(42)) ? defaultMaskedError; - - /** OCCFIR[43] - * OCC_SCOM_OCCFIR_SRAM_SPARE_DIRECT_ERROR2 - */ - (OccFir, bit(43)) ? defaultMaskedError; - - /** OCCFIR[44] - * OCC_SCOM_OCCFIR_SRAM_SPARE_DIRECT_ERROR3 - */ - (OccFir, bit(44)) ? defaultMaskedError; - - /** OCCFIR[45] - * OCC_SCOM_OCCFIR_SLW_OCISLV_ERR - */ - (OccFir, bit(45)) ? SelfMedThr1NoGard; - - /** OCCFIR[46] - * OCC_SCOM_OCCFIR_GPE_OCISLV_ERR - */ - (OccFir, bit(46)) ? defaultMaskedError; - - /** OCCFIR[47] - * OCC_SCOM_OCCFIR_OCB_OCISLV_ERR - */ - (OccFir, bit(47)) ? defaultMaskedError; - - /** OCCFIR[48] - * OCC_SCOM_OCCFIR_C405ICU_M_TIMEOUT - */ - (OccFir, bit(48)) ? defaultMaskedError; - - /** OCCFIR[49] - * OCC_SCOM_OCCFIR_C405DCU_M_TIMEOUT - */ - (OccFir, bit(49)) ? defaultMaskedError; - - /** OCCFIR[50] - * OCC initiated attention - */ - (OccFir, bit(50)) ? occInitiatedAttn; - - /** OCCFIR[51|52|53|54|55|56|57|58|59|60|61] - * OCC_SCOM_OCCLFIR_SPARE_FIR - */ - (OccFir, bit(51|52|53|54|55|56|57|58|59|60|61)) ? defaultMaskedError; - - /** OCCFIR[62|63] - * OCC_SCOM_OCCFIR_FIR_PARITY_ERR_DUP - */ - (OccFir, bit(62|63)) ? defaultMaskedError; -}; - -################################################################################ -# TP Chiplet PBAMFIR -################################################################################ - -rule PbamFir -{ - CHECK_STOP: PBAMFIR & ~PBAMFIR_MASK & ~PBAMFIR_ACT0 & ~PBAMFIR_ACT1; - RECOVERABLE: PBAMFIR & ~PBAMFIR_MASK & ~PBAMFIR_ACT0 & PBAMFIR_ACT1; -}; - -group gPbamFir filter singlebit -{ - /** PBAMFIR[0] - * INVALID_TRANSFER_SIZE - */ - (PbamFir, bit(0)) ? SelfHighThr1; - - /** PBAMFIR[1] - * INVALID_COMMAND - */ - (PbamFir, bit(1)) ? SelfHighThr1; - - /** PBAMFIR[2] - * INVALID_ADDRESS_ALIGNMENT - */ - (PbamFir, bit(2)) ? SelfHighThr1; - - /** PBAMFIR[3] - * OPB_ERROR - */ - (PbamFir, bit(3)) ? defaultMaskedError; - - /** PBAMFIR[4] - * OPB_TIMEOUT - */ - (PbamFir, bit(4)) ? SelfHighThr1; - - /** PBAMFIR[5] - * OPB_MASTER_HANG_TIMEOUT - */ - (PbamFir, bit(5)) ? SelfHighThr1; - - /** PBAMFIR[6] - * CMD_BUFFER_PAR_ERR - */ - (PbamFir, bit(6)) ? SelfHighThr1; - - /** PBAMFIR[7] - * DAT_BUFFER_PAR_ERR - */ - (PbamFir, bit(7)) ? SelfHighThr1; - - /** PBAMFIR[8] - * RETURNQ_ERROR - */ - (PbamFir, bit(8)) ? defaultMaskedError; - - /** PBAMFIR[9] - * RESERVED - */ - (PbamFir, bit(9)) ? defaultMaskedError; - - /** PBAMFIR[10|11] - * FIR_PARITY_ERR - */ - (PbamFir, bit(10|11)) ? defaultMaskedError; - -}; - -################################################################################ -# TP Chiplet PMCFIR -################################################################################ - -rule PmcFir -{ - CHECK_STOP: PMCFIR & ~PMCFIR_MASK & ~PMCFIR_ACT0 & ~PMCFIR_ACT1; - RECOVERABLE: PMCFIR & ~PMCFIR_MASK & ~PMCFIR_ACT0 & PMCFIR_ACT1; -}; - -group gPmcFir filter singlebit -{ - /** PMCFIR[0] - * LFIR_PSTATE_OCI_MASTER_RDERR - */ - (PmcFir, bit(0)) ? SelfHighThr1; - - /** PMCFIR[1] - * LFIR_PSTATE_OCI_MASTER_RDDATA_PARITY_ERR - */ - (PmcFir, bit(1)) ? SelfHighThr1; - - /** PMCFIR[2] - * LFIR_PSTATE_GPST_CHECKBYTE_ERR - */ - (PmcFir, bit(2)) ? SelfHighThr1; - - /** PMCFIR[3] - * LFIR_PSTATE_GACK_TO_ERR - */ - (PmcFir, bit(3)) ? SelfHighThr1; - - /** PMCFIR[4] - * LFIR_PSTATE_PIB_MASTER_NONOFFLINE_ERR - */ - (PmcFir, bit(4)) ? SelfHighThr1; - - /** PMCFIR[5] - * LFIR_PSTATE_PIB_MASTER_OFFLINE_ERR - */ - (PmcFir, bit(5)) ? SelfHighThr1; - - /** PMCFIR[6] - * LFIR_PSTATE_OCI_MASTER_TO_ERR - */ - (PmcFir, bit(6)) ? SelfHighThr1; - - /** PMCFIR[7] - * LFIR_PSTATE_INTERCHIP_UE_ERR - */ - (PmcFir, bit(7)) ? SelfHighThr1; - - /** PMCFIR[8] - * LFIR_PSTATE_INTERCHIP_ERRORFRAME_ERR - */ - (PmcFir, bit(8)) ? SelfHighThr1; - - /** PMCFIR[9] - * LFIR_PSTATE_MS_FSM_ERR - */ - (PmcFir, bit(9)) ? SelfHighThr1; - - /** PMCFIR[10] - * LFIR_MS_COMP_PARITY_ERR - */ - (PmcFir, bit(10)) ? defaultMaskedError; - - /** PMCFIR[11:17] - * LFIR_IDLE - */ - (PmcFir, bit(11|12|13|14|15|16|17)) ? defaultMaskedError; - - /** PMCFIR[18] - * LFIR_INT_COMP_PARITY_ERR - */ - (PmcFir, bit(18)) ? defaultMaskedError; - - /** PMCFIR[19] - * LFIR_PMC_OCC_HEARTBEAT_TIMEOUT - */ - (PmcFir, bit(19)) ? defaultMaskedError; - - /** PMCFIR[20:25] - * LFIR_SPIVID - */ - (PmcFir, bit(20|21|22|23|24|25)) ? defaultMaskedError; - - /** PMCFIR[26:32] - * LFIR_O2S - */ - (PmcFir, bit(26|27|28|29|30|31|32)) ? defaultMaskedError; - - /** PMCFIR[33:34] - * LFIR_O2P - */ - (PmcFir, bit(33|34)) ? defaultMaskedError; - - /** PMCFIR[35] - * LFIR_OCI_SLAVE_ERR - */ - (PmcFir, bit(35)) ? defaultMaskedError; - - /** PMCFIR[36] - * LFIR_IF_COMP_PARITY_ERROR - */ - (PmcFir, bit(36)) ? defaultMaskedError; - - /** PMCFIR[37] - * SLW Malf Alert received by PHYP - */ - (PmcFir, bit(37)) ? SLWRecovery; - - /** PMCFIR[38:46] - * SPARE - */ - (PmcFir, bit(38|39|40|41|42|43|44|45|46)) ? defaultMaskedError; - - /** PMCFIR[47|48] - * FIR_PARITY_ERR - */ - (PmcFir, bit(47|48)) ? defaultMaskedError; -}; - -######################################################################## -# -# TOD Rules and Groups -# -######################################################################## - -rule TodErrors -{ - TOD_ERRORREGISTER & (~TOD_ERRORMASK) & (~TOD_ERRORACTION); -}; - - -group gTodErrors filter singlebit -{ - /** TOD_ERRORREGISTER[0] - * M_PATH_CONTROL_REG_DATA_PARITY_ERROR - */ - (TodErrors,bit(0)) ? defaultMaskedError; - - /** TOD_ERRORREGISTER[1] - * M_PATH_0_PARITY_ERROR - */ - (TodErrors,bit(1)) ? selfCapThr32TopReConfig; - - /** TOD_ERRORREGISTER[2] - * M_PATH_1_PARITY_ERROR - */ - (TodErrors,bit(2)) ? selfCapThr32TopReConfig; - - /** TOD_ERRORREGISTER[3] - * PCRP0_DATA_PARITY_ERROR - */ - (TodErrors,bit(3)) ? defaultMaskedError; - - /** TOD_ERRORREGISTER[4] - * PCRP1_DATA_PARITY_ERROR - */ - (TodErrors,bit(4)) ? defaultMaskedError; - - /** TOD_ERRORREGISTER[5] - * SCRP0_DATA_PARITY_ERROR - */ - (TodErrors,bit(5)) ? defaultMaskedError; - - /** TOD_ERRORREGISTER[6] - * SCRP1_DATA_PARITY_ERROR - */ - (TodErrors,bit(6)) ? defaultMaskedError; - - /** TOD_ERRORREGISTER[7] - * SPCR_DATA_PARITY_ERROR - */ - (TodErrors,bit(7)) ? defaultMaskedError; - - /** TOD_ERRORREGISTER[8] - * IPCR_DATA_PARITY_ERROR - */ - (TodErrors,bit(8)) ? defaultMaskedError; - - /** TOD_ERRORREGISTER[9] - * PSMSCR_DATA_PARITY_ERROR - */ - (TodErrors,bit(9)) ? defaultMaskedError; - - /** TOD_ERRORREGISTER[10] - * S_PATH_0_PARITY_ERROr - */ - (TodErrors,bit(10)) ? selfCapThr32TopReConfig; - - /** TOD_ERRORREGISTER[11] - * REG_0X08_DATA_PARITY_ERROR - */ - (TodErrors,bit(11)) ? selfCaptThr32; - - - /** TOD_ERRORREGISTER[12] - * M_PATH_STATUS_REG_DATA_PARITY_ERROR - */ - (TodErrors,bit(12)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[13] - * S_PATH_STATUS_REG_DATA_PARITY_ERROR - */ - (TodErrors,bit(13)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[14] - * M_PATH_0_STEP_CHECK_ERROR - */ - (TodErrors,bit(14)) ? analyzeStepCheckErr; - - /** TOD_ERRORREGISTER[15] - * M_PATH_1_STEP_CHECK_ERROR - */ - (TodErrors,bit(15)) ? analyzeStepCheckErr; - - /** TOD_ERRORREGISTER[16] - * S_PATH_0_STEP_CHECK_ERROR - */ - (TodErrors,bit(16)) ? analyzeStepCheckErr; - - /** TOD_ERRORREGISTER[17] - * I_PATH_STEP_CHECK_ERROR - */ - (TodErrors,bit(17)) ? analyzeStepCheckErr; - - /** TOD_ERRORREGISTER[18] - * PSS HAMMING DISTANCE - */ - (TodErrors,bit(18)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[19] - * MISC_RESET_REG_DATA_PARITY_ERROR - */ - (TodErrors,bit(19)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[20] - * S_PATH_0_PARITY_ERROR - */ - (TodErrors,bit(20)) ? selfCapThr32TopReConfig; - - /** TOD_ERRORREGISTER[21] - * S_PATH_1_STEP_CHECK_ERROR - */ - (TodErrors,bit(21)) ? analyzeStepCheckErr; - - /** TOD_ERRORREGISTER[22] - * I_PATH_DELAY_STEP_CHECK_PARITY_ERROR - */ - (TodErrors,bit(22)) ? selfCapThr32TopReConfig; - - /** TOD_ERRORREGISTER[23] - * REG_0X0C DATA_PARITY ERROR - */ - (TodErrors,bit(23)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[24] - * REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY_ERROR - */ - (TodErrors,bit(24)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[25] - * REG_0X17_0X18_0X21_0X22_DATA_PARITY_ERROR - */ - (TodErrors,bit(25)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[26] - * REG_0X1D_0X1E_0X1F_DATA_PARITY_ERROR - */ - (TodErrors,bit(26)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[27] - * TIMER_VALUE_REG_DATA_PARITY_ERROR - */ - (TodErrors,bit(27)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[28] - * LOW_ORDER_STEP_REG_DATA_PARITY_ERROR - */ - (TodErrors,bit(28)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[29] - * FSM_REG_DATA_PARITY_ERROR - */ - (TodErrors,bit(29)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[30] - * RX_TTYPE_CONTROL_REG_DATA_PARITY_ERROR - */ - (TodErrors,bit(30)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[31] - * REG_0X30_0X31_0X32_0X33_DATA_PARITY_ERROR - */ - (TodErrors,bit(31)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[32] - * CHIP_CONTROL_REG_DATA_PARITY_ERROR - */ - (TodErrors,bit(32)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[33] - * I_PATH_SYNC_CHECK_ERROR - */ - (TodErrors,bit(33)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[34] - * I_PATH_FSM_STATE_PARITY_ERROR - */ - (TodErrors,bit(34)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[35] - * I_PATH_TIME_REG_PARITY_ERROR - */ - (TodErrors,bit(35)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[36] - * I_PATH_TIME_REG_OVERFLOW - */ - (TodErrors,bit(36)) ? maskTodError; - - /** TOD_ERRORREGISTER[37] - * WOF_LOW_ORDER_STEP_COUNTER_PARITY_ERROR - */ - (TodErrors,bit(37)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[38|39|40|41|42|43] - * RX_TTYPE_1 - */ - (TodErrors,bit(38|39|40|41|42|43)) ? defaultMaskedError; - - #Note: For firmware all the TOD-PIB errors are informational by nature.So, - # not doing any special analysis. - /** TOD_ERRORREGISTER[44] - * PIB_SLAVE_ADDR_INVALID_ERROR - */ - (TodErrors,bit(44)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[45] - * PIB_SLAVE_WRITE_INVALID_ERROR - */ - (TodErrors,bit(45)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[46] - * PIB_SLAVE_READ_INVALID_ERROR - */ - (TodErrors,bit(46)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[47] - * PIB_SLAVE_ADDR_PARITY_ERROR - */ - (TodErrors,bit(47)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[48] - * PIB_SLAVE_DATA_PARITY_ERROR - */ - (TodErrors,bit(48)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[49] - * TTYPE_CONTROL_REG_DATA_PARITY_ERROR - */ - #Note: Based on discussion with with Hardware Team and PHYP, this error - #shall be routed to PHYP instead of FSP - - (TodErrors,bit(49)) ? defaultMaskedError; - - /** TOD_ERRORREGISTER[50|51|52] - * PIB_MASTER_RSP_INFO_ERROR - */ - #ignoring TOD-PIB errors for any special analysis.Since erros are - #informational by nature. - (TodErrors,bit( 50|51|52 )) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[53] - * RX_TTYPE_INVALID_ERROR - */ - (TodErrors,bit(53 )) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[54] - * RX_TTYPE_4_DATA_PARITY_ERROR - */ - (TodErrors,bit(54)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[55] - * PIB_MASTER_REQUEST_ERROR - */ - (TodErrors,bit(55)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[56] - * PIB_RESET_DURING_PIB_ACCESS_ERROR - */ - (TodErrors,bit(56)) ? selfCaptThr32; - - /** TOD_ERRORREGISTER[57] - * EXTERNAL_XSTOP_ERROR - */ - #bit tells us that TOD has received an external check stop - #purpose is to merely provide an information. Hence not doing any - #analysis. - (TodErrors,bit(57)) ? defaultMaskedError; - - #bit[58:63] not implemented - /** TOD_ERRORREGISTER[58|59|60|61|62|63] - * SPARE_ERROR - */ - (TodErrors,bit(58|59|60|61|62|63)) ? defaultMaskedError; - -}; - -################################################################################ -# Actions specific to TP chiplet -################################################################################ - -/** Analyze connected MCS 00 */ -actionclass analyzeMcs00 -{ - analyze(connected(TYPE_MCS, 0)); -}; - -/** Analyze connected MCS 01 */ -actionclass analyzeMcs01 -{ - analyze(connected(TYPE_MCS, 1)); -}; - -/** Analyze connected MCS 10 */ -actionclass analyzeMcs10 -{ - analyze(connected(TYPE_MCS, 2)); -}; - -/** Analyze connected MCS 11 */ -actionclass analyzeMcs11 -{ - analyze(connected(TYPE_MCS, 3)); -}; - -/** Analyze connected MCS 20 */ -actionclass analyzeMcs20 -{ - analyze(connected(TYPE_MCS, 4)); -}; - -/** Analyze connected MCS 21 */ -actionclass analyzeMcs21 -{ - analyze(connected(TYPE_MCS, 5)); -}; - -/** Analyze connected MCS 30 */ -actionclass analyzeMcs30 -{ - analyze(connected(TYPE_MCS, 6)); -}; - -/** Analyze connected MCS 31 */ -actionclass analyzeMcs31 -{ - analyze(connected(TYPE_MCS, 7)); -}; - -# This action is for the case where TP_LFIR[19] comes on -# but PLL code fails to isolate to any PLL errors. The -# threshold is the same as PLL one 2 per 5 mins with -# callout/gard the chip at threshold along with PLL scom -# data captured. -/** PCB Slave Internal parity error action */ -actionclass PcbSlaveInternalParity -{ - capture(PllFIRs); - calloutSelfHigh; - thresholdPll; - funccall("AnalyzeParityErr"); - funccall("capturePllFfdc"); -}; - -# TOD Actions: -# * Get SH Content for all TOD errors. -# * Capture at least this chip TOD registers. -# -# * Threshold normal TOD errors (TOD error register) at 32/day. -# -# * Network Errors : Step Check Fault or "PHYP Failed Topology" -# - PHYP Failed Topology must be visible and "Request new Topology". -# - May have PHYP failure on another chip. -# - Capture TOD registers for whole system. -# - Isolate both topologies and make callout. - -/** - * Analyze TOD Register. - */ -actionclass TodReportByRegister -{ - dump(DUMP_CONTENT_SH); - try(analyze(gTodErrors),TodRegisterAnalyzeFail); -}; - -actionclass TodRegisterAnalyzeFail -{ - capture(TODReg); - SelfHighThr1; -}; - -/** - * PHYP Network fault. - */ -actionclass TodReportByPHYP -{ - dump(DUMP_CONTENT_SH); - threshold1; - funccall("todStepCheckFault"); -}; - -/** - * TOD Step Check Fault - Isolate topology. - */ -actionclass analyzeStepCheckErr -{ - threshold32pday; - funccall("todStepCheckFault"); -}; - -/** action for tod errors which do not need any specific ananlysis */ - -actionclass selfCaptThr32 -{ - calloutSelfHigh; - capture(TODReg); - threshold32pday; -}; - -/** - * Mask indication from PHYP due to all cores evacuated. - * - Mask TOD errors from this chip. - * - Not visible unless xstp. - * - Request new topology if chip is MDMT. - */ -actionclass maskTodError -{ - threshold1; - calloutSelfHigh; - capture(TODReg); - funccall("clearServiceCallFlag"); - funccall("todNewTopologyIfBackupMDMT"); -}; - -/** callout the master core of the Proc */ -actionclass deadManTimer -{ - funccall("deadManTimerCalloutAndFFDC"); - callout2ndLvlMed; - threshold1; - dumpSH; -}; - -/** - * Handle SLW malfunction alert event - */ -actionclass SLWRecovery -{ - funccall("slwRecovery"); - threshold1; -}; - -/** callout Proc reporting error. If threshold reaches 32 per day, request - * reconfiguration of topology. - */ -actionclass selfCapThr32TopReConfig -{ - capture(TODReg); - selfCaptThr32; - funccall("requestTopologySwitch"); -}; - -/** analyzes backup topology if TOD error analysis is enabled */ -actionclass analyzeTodBackupTopology -{ - try( funccall("isTodDisabled"), TodReportByRegister ); -}; - -/** analyzes active topology if TOD error analysis is enabled */ -actionclass analyzePhypTodError -{ - try( funccall("isTodDisabled"), TodReportByPHYP ); -}; - -/** callout and gard self if TOD error analysis is enabled */ -actionclass analyzePibError -{ - try( funccall("isTodDisabled"), SelfHighThr1 ); -}; - -/** analyzes backup topology if TOD error analysis is enabled */ -actionclass analyzeTodBackupTopology -{ - try( funccall("isTodDisabled"), TodReportByRegister ); -}; - -/** analyzes active topology if TOD error analysis is enabled */ -actionclass analyzePhypTodError -{ - try( funccall("isTodDisabled"), TodReportByPHYP ); -}; - -/** callout and gard self if TOD error analysis is enabled */ -actionclass analyzePibError -{ - capture(TODReg); - try( funccall("isTodDisabled"), SelfHighThr1 ); -}; - -/** Callout the cooling system error procedure */ -actionclass coolingSystemError -{ - callout(procedure(COOLING_SYSTEM_ERR), MRU_MED); - threshold1; -}; - -/** The OCC team wants this error log for FFDC. TMGT will make a callout if the - * OCC is reset more than three times in a week. Adding a threshold to protect - * from flooding. If the threshold is ever hit there is a code bug because the - * OCC should never be reset that many times. So calling out 2nd level support - * MED and the PROC LOW with no gard. */ -actionclass occInitiatedAttn -{ - callout2ndLvlMed; - calloutSelfLowNoGard; - threshold32pday; -}; - diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_XBUS.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_XBUS.rule deleted file mode 100755 index 744d10c6b..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_XBUS.rule +++ /dev/null @@ -1,805 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc_acts_XBUS.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2015 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -################################################################################ -# XBUS Chiplet Registers -################################################################################ - -rule XbusChipletFir -{ - CHECK_STOP: - (XBUS_CHIPLET_CS_FIR & `1FC0000000000000`) & ~XBUS_CHIPLET_FIR_MASK; - RECOVERABLE: - ((XBUS_CHIPLET_RE_FIR >> 2) & `1FC0000000000000`) & ~XBUS_CHIPLET_FIR_MASK; -}; - -group gXbusChipletFir filter singlebit -{ - /** XbusChipletFir[3] - * Attention from LFIR - */ - (XbusChipletFir, bit(3)) ? analyze(gXbusLFir); - - /** XbusChipletFir[4] - * Attention from PBENFIR - */ - (XbusChipletFir, bit(4)) ? analyze(gPbenFir); - - /** XbusChipletFir[5] - * Attention from IOXFIR_0 (Venice only) - */ - (XbusChipletFir, bit(5)) ? analyze(gIoxFir_0); - - /** XbusChipletFir[6] - * Attention from IOXFIR_1 - */ - (XbusChipletFir, bit(6)) ? analyze(gIoxFir_1); - - /** XbusChipletFir[7] - * Attention from IOXFIR_2 (Venice only) - */ - (XbusChipletFir, bit(7)) ? analyze(gIoxFir_2); - - /** XbusChipletFir[8] - * Attention from IOXFIR_3 (Venice only) - */ - (XbusChipletFir, bit(8)) ? analyze(gIoxFir_3); - - /** XbusChipletFir[9] - * Attention from PSIXBUSFIR - */ - (XbusChipletFir, bit(9)) ? defaultMaskedError; -}; - -################################################################################ -# XBUS Chiplet LFIR -################################################################################ - -rule XbusLFir -{ - CHECK_STOP: XBUS_LFIR & ~XBUS_LFIR_MASK & ~XBUS_LFIR_ACT0 & ~XBUS_LFIR_ACT1; - RECOVERABLE: XBUS_LFIR & ~XBUS_LFIR_MASK & ~XBUS_LFIR_ACT0 & XBUS_LFIR_ACT1; -}; - -group gXbusLFir filter singlebit -{ - /** XBUS_LFIR[0] - * CFIR internal parity error - */ - (XbusLFir, bit(0)) ? SelfHighThr32PerDay; - - /** XBUS_LFIR[1] - * Local errors from GPIO (PCB error) - */ - (XbusLFir, bit(1)) ? defaultMaskedError; - - /** XBUS_LFIR[2] - * Local errors from CC (PCB error) - */ - (XbusLFir, bit(2)) ? defaultMaskedError; - - /** XBUS_LFIR[3] - * Local errors from CC (OPCG, parity, scan collision, ...) - */ - (XbusLFir, bit(3)) ? defaultMaskedError; - - /** XBUS_LFIR[4] - * Local errors from PSC (PCB error) - */ - (XbusLFir, bit(4)) ? defaultMaskedError; - - /** XBUS_LFIR[5] - * Local errors from PSC (parity error) - */ - (XbusLFir, bit(5)) ? defaultMaskedError; - - /** XBUS_LFIR[6] - * Local errors from Thermal (parity error) - */ - (XbusLFir, bit(6)) ? defaultMaskedError; - - /** XBUS_LFIR[7] - * Local errors from Thermal (PCB error) - */ - (XbusLFir, bit(7)) ? defaultMaskedError; - - /** XBUS_LFIR[8|9] - * Local errors from Thermal (Trip error) - */ - (XbusLFir, bit(8|9)) ? defaultMaskedError; - - /** XBUS_LFIR[10:13] - * Local errors from Trace Array ( error) - */ - (XbusLFir, bit(10|11|12|13)) ? SelfHighThr32PerDay; - - /** XBUS_LFIR[14] - * FIR_IN14: local errors from dcadj - */ - (XbusLFir, bit(14)) ? SelfHighThr32PerDay; - - /** XBUS_LFIR[15:20] - * FIR_IN14: local errors from dcadj - */ - (XbusLFir, bit(15|16|17|18|19|20)) ? defaultMaskedError; - - /** XBUS_LFIR[21:30] - * FIR_IN15: unused local error - */ - (XbusLFir, bit(21|22|23|24|25|26|27|28|29|30)) ? defaultMaskedError; - - /** XBUS_LFIR[31:39] - * FIR_IN15: unused local error - */ - (XbusLFir, bit(31|32|33|34|35|36|37|38|39)) ? defaultMaskedError; - - /** XBUS_LFIR[40] - * FIR_IN40:malfunction alert (local xstop in another chiplet) - */ - (XbusLFir, bit(40)) ? defaultMaskedError; -}; - -################################################################################ -# XBUS Chiplet PBENFIR -################################################################################ - -#FIXME RTC 23127 We need to revisit the Firmware action -#FabricBus_CE_With_Repair. Description is same as P7 but -#it appears it may need change.This appilies to PBEN FIR. -#calloutXbus0InterfaceTh5pDay may need modification. - -rule PbenFir -{ - CHECK_STOP: PBENFIR & ~PBENFIR_MASK & ~PBENFIR_ACT0 & ~PBENFIR_ACT1; - RECOVERABLE: PBENFIR & ~PBENFIR_MASK & ~PBENFIR_ACT0 & PBENFIR_ACT1; -}; - -group gPbenFir filter singlebit, - secondarybits( 0, 3, 6, 9 ) -{ - /** PBENFIR[0] - * X0_LINK_RCV_CE: x0 link rcv ce - */ - (PbenFir, bit(0)) ? calloutXbus0InterfaceTh5pDay; - - /** PBENFIR[1] - * X0_LINK_RCV_DERR: x0 link rcv derr - */ - (PbenFir, bit(1)) ? defaultMaskedError; - - /** PBENFIR[2] - * X0_LINK_RCV_UE: x0 link rcv ue - */ - (PbenFir, bit(2)) ? calloutXbus0InterfaceTh1; - - /** PBENFIR[3] - * X1_LINK_RCV_CE: x1 link rcv ce - */ - (PbenFir, bit(3)) ? calloutXbus1InterfaceTh5pDay; - - /** PBENFIR[4] - * X1_LINK_RCV_DERR: x1 link rcv derr - */ - (PbenFir, bit(4)) ? defaultMaskedError; - - /** PBENFIR[5] - * X1_LINK_RCV_UE: x1 link rcv ue - */ - (PbenFir, bit(5)) ? calloutXbus1InterfaceTh1; - - /** PBENFIR[6] - * X2_LINK_RCV_CE: x2 link rcv ce - */ - (PbenFir, bit(6)) ? calloutXbus2InterfaceTh5pDay; - - /** PBENFIR[7] - * X2_LINK_RCV_DERR: x2 link rcv derr - */ - (PbenFir, bit(7)) ? defaultMaskedError; - - /** PBENFIR[8] - * X2_LINK_RCV_UE: x2 link rcv ue - */ - (PbenFir, bit(8)) ? calloutXbus2InterfaceTh1; - - /** PBENFIR[9] - * X3_LINK_RCV_CE: x3 link rcv ce - */ - (PbenFir, bit(9)) ? calloutXbus3InterfaceTh5pDay; - - /** PBENFIR[10] - * X3_LINK_RCV_DERR: x3 link rcv derr - */ - (PbenFir, bit(10)) ? defaultMaskedError; - - /** PBENFIR[11] - * X3_LINK_RCV_UE: x3 link rcv ue - */ - (PbenFir, bit(11)) ? calloutXbus3InterfaceTh1; - - /** PBENFIR[12] - * X_LINK_SND_CE: x link rcv ce - */ - (PbenFir, bit(12)) ? SelfHighThr5PerHour; - - /** PBENFIR[13] - * X_LINK_SND_SUE: x link rcv sue - */ - (PbenFir, bit(13)) ? defaultMaskedError; - - /** PBENFIR[14] - * X_LINK_SND_UE: x link rcv ue - */ - (PbenFir, bit(14)) ? SelfHighThr1; - - /** PBENFIR[15] - * X_LINK_CR_OVERFLOW: x link command/response/data buffer overflow - */ - (PbenFir, bit(15)) ? calloutProcLevel2MedThr1dumpShNoGard; - - /** PBENFIR[16] - * X0_LINK_FMR_ERR: x0 link framer error - */ - (PbenFir, bit(16)) ? SelfHighThr1; - - /** PBENFIR[17] - * X1_LINK_FMR_ERR: x1 link framer error - */ - (PbenFir, bit(17)) ? SelfHighThr1; - - /** PBENFIR[18] - * X2_LINK_FMR_ERR: x2 link framer error - */ - (PbenFir, bit(18)) ? SelfHighThr1; - - /** PBENFIR[19] - * X3_LINK_FMR_ERR: x3 link framer error - */ - (PbenFir, bit(19)) ? SelfHighThr1; - - /** PBENFIR[20] - * X_LINK_PSR_ERR: x link parser error - */ - (PbenFir, bit(20)) ? SelfHighThr1; - - /** PBENFIR[21:30] - * Reserved - */ - (PbenFir, bit(21|22|23|24|25|26|27|28|29|30)) ? defaultMaskedError; - - /** PBENFIR[31:35] - * Reserved - */ - (PbenFir, bit(31|32|33|34|35)) ? defaultMaskedError; - - /** PBENFIR[36:37] - * FIR_SCOM_ERR: pben iox fir_scom_err - */ - (PbenFir, bit(36|37)) ? defaultMaskedError; -}; - -################################################################################ -# XBUS Chiplet IOXFIR_0 -################################################################################ - -rule IoxFir_0 -{ - CHECK_STOP: IOXFIR_0 & ~IOXFIR_0_MASK & ~IOXFIR_0_ACT0 & ~IOXFIR_0_ACT1; - RECOVERABLE: IOXFIR_0 & ~IOXFIR_0_MASK & ~IOXFIR_0_ACT0 & IOXFIR_0_ACT1; -}; - -group gIoxFir_0 filter singlebit, - secondarybits( 9 ) -{ - /** IOXFIR_0[0] - * FIR_RX_INVALID_STATE_OR_PARITY_ERROR - */ - (IoxFir_0, bit(0)) ? defaultMaskedError; - - /** IOXFIR_0[1] - * FIR_TX_INVALID_STATE_OR_PARITY_ERROR - */ - (IoxFir_0, bit(1)) ? defaultMaskedError; - - /** IOXFIR_0[2] - * FIR_GCR_HANG_ERROR - */ - (IoxFir_0, bit(2)) ? calloutXbus0InterfaceTh1; - - /** IOXFIR_0[3:7] - * Reserved - */ - (IoxFir_0, bit(3|4|5|6|7)) ? defaultMaskedError; - - /** IOXFIR_0[8] - * Training Error - */ - (IoxFir_0, bit(8)) ? defaultMaskedError; - - /** IOXFIR_0[9] - * Spare Deployed - */ - (IoxFir_0, bit(9)) ? spareDeployed_xbus0; - - /** IOXFIR_0[10] - * Max Spares Exceeded - */ - (IoxFir_0, bit(10)) ? maxSparesExceeded_xbus0; - - /** IOXFIR_0[11] - * Recalibration or Dynamic Repair Error - */ - (IoxFir_0, bit(11)) ? defaultMaskedError; - - /** IOXFIR_0[12] - * Too Many Bus Errors - */ - (IoxFir_0, bit(12)) ? tooManyBusErrors_xbus0; - - /** IOXFIR_0[13:15] - * Reserved - */ - (IoxFir_0, bit(13|14|15)) ? defaultMaskedError; - - /** IOXFIR_0[16:23] - * FIR_RX_BUS1 unused - */ - (IoxFir_0, bit(16|17|18|19|20|21|22|23)) ? defaultMaskedError; - - /** IOXFIR_0[24:31] - * FIR_RX_BUS2 unused - */ - (IoxFir_0, bit(24|25|26|27|28|29|30|31)) ? defaultMaskedError; - - /** IOXFIR_0[32:39] - * FIR_RX_BUS3 unused - */ - (IoxFir_0, bit(32|33|34|35|36|37|38|39)) ? defaultMaskedError; - - /** IOXFIR_0[40:47] - * FIR_RX_BUS4 unused - */ - (IoxFir_0, bit(40|41|42|43|44|45|46|47)) ? defaultMaskedError; - - /** IOXFIR_0[48] - * FIR_SCOMFIR_ERROR - */ - (IoxFir_0, bit(48)) ? defaultMaskedError; - - /** IOXFIR_0[49] - * FIR_SCOMFIR_ERROR_CLONE - */ - (IoxFir_0, bit(49)) ? defaultMaskedError; -}; - -################################################################################ -# XBUS Chiplet IOXFIR_1 -################################################################################ - -rule IoxFir_1 -{ - CHECK_STOP: IOXFIR_1 & ~IOXFIR_1_MASK & ~IOXFIR_1_ACT0 & ~IOXFIR_1_ACT1; - RECOVERABLE: IOXFIR_1 & ~IOXFIR_1_MASK & ~IOXFIR_1_ACT0 & IOXFIR_1_ACT1; -}; - -group gIoxFir_1 filter singlebit, - secondarybits( 9 ) -{ - /** IOXFIR_1[0] - * FIR_RX_INVALID_STATE_OR_PARITY_ERROR - */ - (IoxFir_1, bit(0)) ? defaultMaskedError; - - /** IOXFIR_1[1] - * FIR_TX_INVALID_STATE_OR_PARITY_ERROR - */ - (IoxFir_1, bit(1)) ? defaultMaskedError; - - /** IOXFIR_1[2] - * FIR_GCR_HANG_ERROR - */ - (IoxFir_1, bit(2)) ? calloutXbus1InterfaceTh1; - - /** IOXFIR_1[3:7] - * Reserved - */ - (IoxFir_1, bit(3|4|5|6|7)) ? defaultMaskedError; - - /** IOXFIR_1[8] - * Training Error - */ - (IoxFir_1, bit(8)) ? defaultMaskedError; - - /** IOXFIR_1[9] - * Spare Deployed - */ - (IoxFir_1, bit(9)) ? spareDeployed_xbus1; - - /** IOXFIR_1[10] - * Max Spares Exceeded - */ - (IoxFir_1, bit(10)) ? maxSparesExceeded_xbus1; - - /** IOXFIR_1[11] - * Recalibration or Dynamic Repair Error - */ - (IoxFir_1, bit(11)) ? defaultMaskedError; - - /** IOXFIR_1[12] - * Too Many Bus Errors - */ - (IoxFir_1, bit(12)) ? tooManyBusErrors_xbus1; - - /** IOXFIR_1[13:15] - * Reserved - */ - (IoxFir_1, bit(13|14|15)) ? defaultMaskedError; - - /** IOXFIR_1[16:23] - * FIR_RX_BUS1 unused - */ - (IoxFir_1, bit(16|17|18|19|20|21|22|23)) ? defaultMaskedError; - - /** IOXFIR_1[24:31] - * FIR_RX_BUS2 unused - */ - (IoxFir_1, bit(24|25|26|27|28|29|30|31)) ? defaultMaskedError; - - /** IOXFIR_1[32:39] - * FIR_RX_BUS3 unused - */ - (IoxFir_1, bit(32|33|34|35|36|37|38|39)) ? defaultMaskedError; - - /** IOXFIR_1[40:47] - * FIR_RX_BUS4 unused - */ - (IoxFir_1, bit(40|41|42|43|44|45|46|47)) ? defaultMaskedError; - - /** IOXFIR_1[48] - * FIR_SCOMFIR_ERROR - */ - (IoxFir_1, bit(48)) ? defaultMaskedError; - - /** IOXFIR_1[49] - * FIR_SCOMFIR_ERROR_CLONE - */ - (IoxFir_1, bit(49)) ? defaultMaskedError; -}; - -################################################################################ -# XBUS Chiplet IOXFIR_2 -################################################################################ - -rule IoxFir_2 -{ - CHECK_STOP: IOXFIR_2 & ~IOXFIR_2_MASK & ~IOXFIR_2_ACT0 & ~IOXFIR_2_ACT1; - RECOVERABLE: IOXFIR_2 & ~IOXFIR_2_MASK & ~IOXFIR_2_ACT0 & IOXFIR_2_ACT1; -}; - -group gIoxFir_2 filter singlebit, - secondarybits( 9 ) -{ - /** IOXFIR_2[0] - * FIR_RX_INVALID_STATE_OR_PARITY_ERROR - */ - (IoxFir_2, bit(0)) ? defaultMaskedError; - - /** IOXFIR_2[1] - * FIR_TX_INVALID_STATE_OR_PARITY_ERROR - */ - (IoxFir_2, bit(1)) ? defaultMaskedError; - - /** IOXFIR_2[2] - * FIR_GCR_HANG_ERROR - */ - (IoxFir_2, bit(2)) ? calloutXbus2InterfaceTh1; - - /** IOXFIR_2[3:7] - * Reserved - */ - (IoxFir_2, bit(3|4|5|6|7)) ? defaultMaskedError; - - /** IOXFIR_2[8] - * Training Error - */ - (IoxFir_2, bit(8)) ? defaultMaskedError; - - /** IOXFIR_2[9] - * Spare Deployed - */ - (IoxFir_2, bit(9)) ? spareDeployed_xbus2; - - /** IOXFIR_2[10] - * Max Spares Exceeded - */ - (IoxFir_2, bit(10)) ? maxSparesExceeded_xbus2; - - /** IOXFIR_2[11] - * Recalibration or Dynamic Repair Error - */ - (IoxFir_2, bit(11)) ? defaultMaskedError; - - /** IOXFIR_2[12] - * Too Many Bus Errors - */ - (IoxFir_2, bit(12)) ? tooManyBusErrors_xbus2; - - /** IOXFIR_2[13:15] - * Reserved - */ - (IoxFir_2, bit(13|14|15)) ? defaultMaskedError; - - /** IOXFIR_2[16:23] - * FIR_RX_BUS1 unused - */ - (IoxFir_2, bit(16|17|18|19|20|21|22|23)) ? defaultMaskedError; - - /** IOXFIR_2[24:31] - * FIR_RX_BUS2 unused - */ - (IoxFir_2, bit(24|25|26|27|28|29|30|31)) ? defaultMaskedError; - - /** IOXFIR_2[32:39] - * FIR_RX_BUS3 unused - */ - (IoxFir_2, bit(32|33|34|35|36|37|38|39)) ? defaultMaskedError; - - /** IOXFIR_2[40:47] - * FIR_RX_BUS4 unused - */ - (IoxFir_2, bit(40|41|42|43|44|45|46|47)) ? defaultMaskedError; - - /** IOXFIR_2[48] - * FIR_SCOMFIR_ERROR - */ - (IoxFir_2, bit(48)) ? defaultMaskedError; - - /** IOXFIR_2[49] - * FIR_SCOMFIR_ERROR_CLONE - */ - (IoxFir_2, bit(49)) ? defaultMaskedError; -}; - -################################################################################ -# XBUS Chiplet IOXFIR_3 -################################################################################ - -rule IoxFir_3 -{ - CHECK_STOP: IOXFIR_3 & ~IOXFIR_3_MASK & ~IOXFIR_3_ACT0 & ~IOXFIR_3_ACT1; - RECOVERABLE: IOXFIR_3 & ~IOXFIR_3_MASK & ~IOXFIR_3_ACT0 & IOXFIR_3_ACT1; -}; - -group gIoxFir_3 filter singlebit, - secondarybits( 9 ) -{ - /** IOXFIR_3[0] - * FIR_RX_INVALID_STATE_OR_PARITY_ERROR - */ - (IoxFir_3, bit(0)) ? defaultMaskedError; - - /** IOXFIR_3[1] - * FIR_TX_INVALID_STATE_OR_PARITY_ERROR - */ - (IoxFir_3, bit(1)) ? defaultMaskedError; - - /** IOXFIR_3[2] - * FIR_GCR_HANG_ERROR - */ - (IoxFir_3, bit(2)) ? calloutXbus3InterfaceTh1; - - /** IOXFIR_3[3:7] - * Reserved - */ - (IoxFir_3, bit(3|4|5|6|7)) ? defaultMaskedError; - - /** IOXFIR_3[8] - * Training Error - */ - (IoxFir_3, bit(8)) ? defaultMaskedError; - - /** IOXFIR_3[9] - * Spare Deployed - */ - (IoxFir_3, bit(9)) ? spareDeployed_xbus3; - - /** IOXFIR_3[10] - * Max Spares Exceeded - */ - (IoxFir_3, bit(10)) ? maxSparesExceeded_xbus3; - - /** IOXFIR_3[11] - * Recalibration or Dynamic Repair Error - */ - (IoxFir_3, bit(11)) ? defaultMaskedError; - - /** IOXFIR_3[12] - * Too Many Bus Errors - */ - (IoxFir_3, bit(12)) ? tooManyBusErrors_xbus3; - - /** IOXFIR_3[13:15] - * Reserved - */ - (IoxFir_3, bit(13|14|15)) ? defaultMaskedError; - - /** IOXFIR_3[16:23] - * FIR_RX_BUS1 unused - */ - (IoxFir_3, bit(16|17|18|19|20|21|22|23)) ? defaultMaskedError; - - /** IOXFIR_3[24:31] - * FIR_RX_BUS2 unused - */ - (IoxFir_3, bit(24|25|26|27|28|29|30|31)) ? defaultMaskedError; - - /** IOXFIR_3[32:39] - * FIR_RX_BUS3 unused - */ - (IoxFir_3, bit(32|33|34|35|36|37|38|39)) ? defaultMaskedError; - - /** IOXFIR_3[40:47] - * FIR_RX_BUS4 unused - */ - (IoxFir_3, bit(40|41|42|43|44|45|46|47)) ? defaultMaskedError; - - /** IOXFIR_3[48] - * FIR_SCOMFIR_ERROR - */ - (IoxFir_3, bit(48)) ? defaultMaskedError; - - /** IOXFIR_3[49] - * FIR_SCOMFIR_ERROR_CLONE - */ - (IoxFir_3, bit(49)) ? defaultMaskedError; -}; - -################################################################################ -# Actions specific to XBUS chiplet -################################################################################ - -/** Callout the XBUS 0 interface */ -actionclass calloutXbus0Interface -{ - callout(connected(TYPE_XBUS, 0), MRU_MEDA); - callout(connected_peer(TYPE_XBUS, 0), MRU_MEDA); - funccall("calloutInterface_xbus0"); -}; - -/** Callout the XBUS 1 interface */ -actionclass calloutXbus1Interface -{ - callout(connected(TYPE_XBUS, 1), MRU_MEDA); - callout(connected_peer(TYPE_XBUS, 1), MRU_MEDA); - funccall("calloutInterface_xbus1"); -}; - -/** Callout the XBUS 2 interface */ -actionclass calloutXbus2Interface -{ - callout(connected(TYPE_XBUS, 2), MRU_MEDA); - callout(connected_peer(TYPE_XBUS, 2), MRU_MEDA); - funccall("calloutInterface_xbus2"); -}; - -/** Callout the XBUS 3 interface */ -actionclass calloutXbus3Interface -{ - callout(connected(TYPE_XBUS, 3), MRU_MEDA); - callout(connected_peer(TYPE_XBUS, 3), MRU_MEDA); - funccall("calloutInterface_xbus3"); -}; - -/** Callout the XBUS 0 interface, threshold 1 */ -actionclass calloutXbus0InterfaceTh1 { calloutXbus0Interface; threshold1; }; - -/** Callout the XBUS 1 interface, threshold 1 */ -actionclass calloutXbus1InterfaceTh1 { calloutXbus1Interface; threshold1; }; - -/** Callout the XBUS 2 interface, threshold 1 */ -actionclass calloutXbus2InterfaceTh1 { calloutXbus2Interface; threshold1; }; - -/** Callout the XBUS 3 interface, threshold 1 */ -actionclass calloutXbus3InterfaceTh1 { calloutXbus3Interface; threshold1; }; - -/** Lane Repair: spare deployed - XBUS 0 */ -actionclass spareDeployed_xbus0 -{ calloutXbus0Interface; funccall("spareDeployed_xbus0"); }; - -/** Lane Repair: max spares exceeded - XBUS 0 */ -actionclass maxSparesExceeded_xbus0 -{ calloutXbus0InterfaceTh1; funccall("maxSparesExceeded_xbus0"); }; - -/** Lane Repair: too many bus errors - XBUS 0 */ -actionclass tooManyBusErrors_xbus0 -{ calloutXbus0InterfaceTh1; funccall("tooManyBusErrors_xbus0"); }; - -/** Lane Repair: spare deployed - XBUS 1 */ -actionclass spareDeployed_xbus1 -{ calloutXbus1Interface; funccall("spareDeployed_xbus1"); }; - -/** Lane Repair: max spares exceeded - XBUS 1 */ -actionclass maxSparesExceeded_xbus1 -{ calloutXbus1InterfaceTh1; funccall("maxSparesExceeded_xbus1"); }; - -/** Lane Repair: too many bus errors - XBUS 1 */ -actionclass tooManyBusErrors_xbus1 -{ calloutXbus1InterfaceTh1; funccall("tooManyBusErrors_xbus1"); }; - -/** Lane Repair: spare deployed - XBUS 2 */ -actionclass spareDeployed_xbus2 -{ calloutXbus2Interface; funccall("spareDeployed_xbus2"); }; - -/** Lane Repair: max spares exceeded - XBUS 2 */ -actionclass maxSparesExceeded_xbus2 -{ calloutXbus2InterfaceTh1; funccall("maxSparesExceeded_xbus2"); }; - -/** Lane Repair: too many bus errors - XBUS 2 */ -actionclass tooManyBusErrors_xbus2 -{ calloutXbus2InterfaceTh1; funccall("tooManyBusErrors_xbus2"); }; - -/** Lane Repair: spare deployed - XBUS 3 */ -actionclass spareDeployed_xbus3 -{ calloutXbus3Interface; funccall("spareDeployed_xbus3"); }; - -/** Lane Repair: max spares exceeded - XBUS 3 */ -actionclass maxSparesExceeded_xbus3 -{ calloutXbus3InterfaceTh1; funccall("maxSparesExceeded_xbus3"); }; - -/** Lane Repair: too many bus errors - XBUS 3 */ -actionclass tooManyBusErrors_xbus3 -{ calloutXbus3InterfaceTh1; funccall("tooManyBusErrors_xbus3"); }; - -/** Threshold 5 per day, mask but do not predictively callout XBUS 0 */ -actionclass calloutXbus0InterfaceTh5pDay -{ - calloutXbus0Interface; - threshold5pday; - funccall("ClearServiceCallFlag"); -}; - -/** Threshold 5 per day, mask but do not predictively callout XBUS 1 */ -actionclass calloutXbus1InterfaceTh5pDay -{ - calloutXbus1Interface; - threshold5pday; - funccall("ClearServiceCallFlag"); -}; - -/** Threshold 5 per day, mask but do not predictively callout XBUS 2 */ -actionclass calloutXbus2InterfaceTh5pDay -{ calloutXbus2Interface; - threshold5pday; - funccall("ClearServiceCallFlag"); -}; - -/** Threshold 5 per day, mask but do not predictively callout XBUS 3 */ -actionclass calloutXbus3InterfaceTh5pDay -{ - calloutXbus3Interface; - threshold5pday; - funccall("ClearServiceCallFlag"); -}; - diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_common.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_common.rule deleted file mode 100755 index c9add00df..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_common.rule +++ /dev/null @@ -1,208 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc_acts_common.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2015 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - ############################################################################## - # # - # #### # # - # # # # # # ##### ### # # # ## ##### ### ### # # ### # - # # # # # # # # # # # # # # # # # ## # # # - # #### # # # #### ### # ####### # # # # # # # # ### # - # # # # # # # # # # # # # # # # # # ## # # - # # # ### #### ##### ### # # # ## # ### ### # # ### # - # # - ############################################################################## - -################################################################################ -# Global Broadcast Registers -################################################################################ - -#CS and RE in MuranoVenice and Naples specific rule files - -rule GlobalSpa -{ - SPECIAL: GLOBAL_SPA; -}; - -group gGlobalSpa attntype SPECIAL filter singlebit -{ - /** GLOBAL_SPA[1] - * Attention from TP chiplet - */ - (GlobalSpa, bit(1)) ? analyze(gTpChipletSpa); - - /** GLOBAL_SPA[2] - * Attention from PB chiplet - */ - (GlobalSpa, bit(2)) ? analyze(gPbChipletSpa); - - /** GLOBAL_SPA[9] - * Attention from PCIE - */ - (GlobalSpa, bit(9)) ? analyze(gPcieChipletSpa); - - /** GLOBAL_SPA[11] - * Attention from EX1 (Venice only) - */ - (GlobalSpa, bit(11)) ? analyzeEx1; - - /** GLOBAL_SPA[12] - * Attention from EX2 (Venice only) - */ - (GlobalSpa, bit(12)) ? analyzeEx2; - - /** GLOBAL_SPA[13] - * Attention from EX3 (Venice only) - */ - (GlobalSpa, bit(13)) ? analyzeEx3; - - /** GLOBAL_SPA[14] - * Attention from EX4 - */ - (GlobalSpa, bit(14)) ? analyzeEx4; - - /** GLOBAL_SPA[15] - * Attention from EX5 - */ - (GlobalSpa, bit(15)) ? analyzeEx5; - - /** GLOBAL_SPA[16] - * Attention from EX6 - */ - (GlobalSpa, bit(16)) ? analyzeEx6; - - /** GLOBAL_SPA[19] - * Attention from EX9 (Venice only) - */ - (GlobalSpa, bit(19)) ? analyzeEx9; - - /** GLOBAL_SPA[20] - * Attention from EX10 (Venice only) - */ - (GlobalSpa, bit(20)) ? analyzeEx10; - - /** GLOBAL_SPA[21] - * Attention from EX11 (Venice only) - */ - (GlobalSpa, bit(21)) ? analyzeEx11; - - /** GLOBAL_SPA[22] - * Attention from EX12 - */ - (GlobalSpa, bit(22)) ? analyzeEx12; - - /** GLOBAL_SPA[23] - * Attention from EX13 - */ - (GlobalSpa, bit(23)) ? analyzeEx13; - - /** GLOBAL_SPA[24] - * Attention from EX14 - */ - (GlobalSpa, bit(24)) ? analyzeEx14; -}; - - ############################################################################## - # # - # # ### # - # # # ## ##### ### ### # # # # # # ### ### ### ### # - # # # # # # # # # ## # # # # # # # # # # - # ####### # # # # # # # # # # ##### ### ### ## ### # - # # # # # # # # # # ## # # # # # # # # # # - # # # ## # ### ### # # ### ### # # ### ### ### ### # - # # - ############################################################################## - - -################################################################################ -# Analyze Connected Parts # -################################################################################ - -/** Analyze connected EX1 */ -actionclass analyzeEx1 { analyze(connected(TYPE_EX, 1)); }; - -/** Analyze connected EX2 */ -actionclass analyzeEx2 { analyze(connected(TYPE_EX, 2)); }; - -/** Analyze connected EX3 */ -actionclass analyzeEx3 { analyze(connected(TYPE_EX, 3)); }; - -/** Analyze connected EX4 */ -actionclass analyzeEx4 { analyze(connected(TYPE_EX, 4)); }; - -/** Analyze connected EX5 */ -actionclass analyzeEx5 { analyze(connected(TYPE_EX, 5)); }; - -/** Analyze connected EX6 */ -actionclass analyzeEx6 { analyze(connected(TYPE_EX, 6)); }; - -/** Analyze connected EX9 */ -actionclass analyzeEx9 { analyze(connected(TYPE_EX, 9)); }; - -/** Analyze connected EX10 */ -actionclass analyzeEx10 { analyze(connected(TYPE_EX, 10)); }; - -/** Analyze connected EX11 */ -actionclass analyzeEx11 { analyze(connected(TYPE_EX, 11)); }; - -/** Analyze connected EX12 */ -actionclass analyzeEx12 { analyze(connected(TYPE_EX, 12)); }; - -/** Analyze connected EX13 */ -actionclass analyzeEx13 { analyze(connected(TYPE_EX, 13)); }; - -/** Analyze connected EX14 */ -actionclass analyzeEx14 { analyze(connected(TYPE_EX, 14)); }; - -actionclass calloutProcLevel2MedThr1 -{ - calloutSelfLow; - callout2ndLvlMed; - threshold1; -}; - -/** callout Proc with low priority ,Sec level Med priority, Thr1 - * and dump type SH, garding not done */ -actionclass calloutProcLevel2MedThr1dumpShNoGard -{ - calloutSelfLowNoGard; - callout2ndLvlMedThr1; - dumpSH; -}; - -/** callout Proc with low priority ,Sec level Med priority, Thr 32per day - * and dump type SH , garding not done */ -actionclass calloutProcLevel2MedThr32dumpShNoGard -{ - calloutSelfLow; - callout2ndLvlMed; - threshold32pday; - dumpSH; -}; - -actionclass calloutProcHighThr1SUE -{ - calloutSelfHigh; - SUEGenerationPoint; - threshold1; -}; diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_ABUS.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_ABUS.rule deleted file mode 100755 index dd604358c..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_ABUS.rule +++ /dev/null @@ -1,190 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc_regs_ABUS.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2015 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -################################################################################ -# -# Chiplet Register Adddresses Description -# ======= ======================= ============================================ -# ABUS 0x08000000 - 0x0800FFFF ABUS pervasive logic (Murano/Venice only) -# -################################################################################ - - ############################################################################ - # ABUS Chiplet Registers - ############################################################################ - - register ABUS_CHIPLET_CS_FIR - { - name "ES.PBES_WRAP_TOP.TPC.XFIR"; - scomaddr 0x08040000; - capture group default; - }; - - register ABUS_CHIPLET_RE_FIR - { - name "ES.PBES_WRAP_TOP.TPC.RFIR"; - scomaddr 0x08040001; - capture group default; - }; - - register ABUS_CHIPLET_FIR_MASK - { - name "ES.PBES_WRAP_TOP.TPC.FIR_MASK"; - scomaddr 0x08040002; - capture group default; - }; - - ############################################################################ - # ABUS Chiplet LFIR - ############################################################################ - - register ABUS_LFIR - { - name "ES.PBES_WRAP_TOP.TPC.LOCAL_FIR"; - scomaddr 0x0804000a; - reset (&, 0x0804000b); - mask (|, 0x0804000f); - capture group default; - }; - - register ABUS_LFIR_MASK - { - name "ES.PBES_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_MASK"; - scomaddr 0x0804000d; - capture group default; - }; - - register ABUS_LFIR_ACT0 - { - name "ES.PBES_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_ACTION0"; - scomaddr 0x08040010; - capture type secondary; - capture group default; - capture req nonzero("ABUS_LFIR"); - }; - - register ABUS_LFIR_ACT1 - { - name "ES.PBES_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_ACTION1"; - scomaddr 0x08040011; - capture type secondary; - capture group default; - capture req nonzero("ABUS_LFIR"); - }; - - ############################################################################ - # ABUS Chiplet PBESFIR - ############################################################################ - - register PBESFIR - { - name "ES.PBES_WRAP_TOP.PBES_TOP.MISC_IO.SCOM.PB_IOA_FIR_REG"; - scomaddr 0x08010800; - reset (&, 0x08010801); - mask (|, 0x08010805); - capture group default; - }; - - register PBESFIR_MASK - { - name "ES.PBES_WRAP_TOP.PBES_TOP.MISC_IO.SCOM.PB_IOA_FIR_MASK_REG"; - scomaddr 0x08010803; - capture group default; - }; - - register PBESFIR_ACT0 - { - name "ES.PBES_WRAP_TOP.PBES_TOP.MISC_IO.SCOM.PB_IOA_FIR_ACTION0_REG"; - scomaddr 0x08010806; - capture type secondary; - capture group default; - capture req nonzero("PBESFIR"); - }; - - register PBESFIR_ACT1 - { - name "ES.PBES_WRAP_TOP.PBES_TOP.MISC_IO.SCOM.PB_IOA_FIR_ACTION1_REG"; - scomaddr 0x08010807; - capture type secondary; - capture group default; - capture req nonzero("PBESFIR"); - }; - - ############################################################################ - # ABUS Chiplet IOAFIR - ############################################################################ - - register IOAFIR - { - name "ABUS.BUSCTL.SCOM.FIR_REG"; - scomaddr 0x08010c00; - reset (&, 0x08010c01); - mask (|, 0x08010c05); - capture group default; - }; - - register IOAFIR_MASK - { - name "ABUS.BUSCTL.SCOM.FIR_MASK_REG"; - scomaddr 0x08010c03; - capture group default; - }; - - register IOAFIR_ACT0 - { - name "ABUS.BUSCTL.SCOM.FIR_ACTION0_REG"; - scomaddr 0x08010c06; - capture type secondary; - capture group default; - capture req nonzero("IOAFIR"); - }; - - register IOAFIR_ACT1 - { - name "ABUS.BUSCTL.SCOM.FIR_ACTION1_REG"; - scomaddr 0x08010c07; - capture type secondary; - capture group default; - capture req nonzero("IOAFIR"); - }; - - ############################################################################ - # ABUS Chiplet PLL Registers - ############################################################################ - - register ABUS_ERROR_REG - { - name "EH.TPCHIP.NET.PCBSLAB.ERROR_REG"; - scomaddr 0x080F001F; - capture group PllFIRs; - }; - - register ABUS_CONFIG_REG - { - name "EH.TPCHIP.NET.PCBSLAB.SLAVE_CONFIG_REG"; - scomaddr 0x080F001E; - capture group PllFIRs; - }; - diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_NV.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_NV.rule deleted file mode 100755 index d83a2beba..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_NV.rule +++ /dev/null @@ -1,227 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc_regs_NV.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2015 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -################################################################################ -# -# Chiplet Register Adddresses Description -# ======= ======================= ============================================ -# NV 0x08000000 - 0x0800FFFF NV pervasive logic (Naples only) -# -################################################################################ - - ############################################################################ - # NV Chiplet Registers - ############################################################################ - - register NV_CHIPLET_CS_FIR - { - name "NV_WRAP_TOP.TPC.XFIR"; - scomaddr 0x08040000; - capture group default; - }; - - register NV_CHIPLET_RE_FIR - { - name "NV_WRAP_TOP.TPC.RFIR"; - scomaddr 0x08040001; - capture group default; - }; - - register NV_CHIPLET_FIR_MASK - { - name "NV_WRAP_TOP.TPC.FIR_MASK"; - scomaddr 0x08040002; - capture group default; - }; - - ############################################################################ - # NV Chiplet LFIR - ############################################################################ - - register NV_LFIR - { - name "NV_WRAP_TOP.TPC.LOCAL_FIR"; - scomaddr 0x0804000a; - reset (&, 0x0804000b); - mask (|, 0x0804000f); - capture group default; - }; - - register NV_LFIR_MASK - { - name "NV_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_MASK"; - scomaddr 0x0804000d; - capture group default; - }; - - register NV_LFIR_ACT0 - { - name "NV_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_ACTION0"; - scomaddr 0x08040010; - capture type secondary; - capture group default; - capture req nonzero("NV_LFIR"); - }; - - register NV_LFIR_ACT1 - { - name "NV_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_ACTION1"; - scomaddr 0x08040011; - capture type secondary; - capture group default; - capture req nonzero("NV_LFIR"); - }; - - ############################################################################ - # NV Chiplet IONVFIR_0 - ############################################################################ - - register IONVFIR_0 - { - name "NVBUS0.BUSCTL.SCOM.FIR_REG"; - scomaddr 0x08010c00; - reset (&, 0x08010c01); - mask (|, 0x08010c05); - capture group default; - }; - - register IONVFIR_0_MASK - { - name "NVBUS0.BUSCTL.SCOM.FIR_MASK_REG"; - scomaddr 0x08010c03; - capture group default; - }; - - register IONVFIR_0_ACT0 - { - name "NVBUS0.BUSCTL.SCOM.FIR_ACTION0_REG"; - scomaddr 0x08010c06; - capture type secondary; - capture group default; - capture req nonzero("IONVFIR_0"); - }; - - register IONVFIR_0_ACT1 - { - name "NVBUS0.BUSCTL.SCOM.FIR_ACTION1_REG"; - scomaddr 0x08010c07; - capture type secondary; - capture group default; - capture req nonzero("IONVFIR_0"); - }; - - ############################################################################ - # NV Chiplet IONVFIR_1 - ############################################################################ - - register IONVFIR_1 - { - name "NVBUS1.BUSCTL.SCOM.FIR_REG"; - scomaddr 0x08010c40; - reset (&, 0x08010c41); - mask (|, 0x08010c45); - capture group default; - }; - - register IONVFIR_1_MASK - { - name "NVBUS1.BUSCTL.SCOM.FIR_MASK_REG"; - scomaddr 0x08010c43; - capture group default; - }; - - register IONVFIR_1_ACT0 - { - name "NVBUS1.BUSCTL.SCOM.FIR_ACTION0_REG"; - scomaddr 0x08010c46; - capture type secondary; - capture group default; - capture req nonzero("IONVFIR_1"); - }; - - register IONVFIR_1_ACT1 - { - name "NVBUS1.BUSCTL.SCOM.FIR_ACTION1_REG"; - scomaddr 0x08010c47; - capture type secondary; - capture group default; - capture req nonzero("IONVFIR_1"); - }; - - ############################################################################ - # NV Chiplet NPUFIR - ############################################################################ - - register NPUFIR - { - name "ES.NPU.NP_AT.REG.FIR_REG"; - scomaddr 0x08013d80; - reset (&, 0x08013d81); - mask (|, 0x08013d85); - capture group default; - }; - - register NPUFIR_MASK - { - name "ES.NPU.NP_AT.REG.FIR_MASK_REG"; - scomaddr 0x08013d83; - capture group default; - }; - - register NPUFIR_ACT0 - { - name "ES.NPU.NP_AT.REG.FIR_ACTION0_REG"; - scomaddr 0x08013d86; - capture type secondary; - capture group default; - capture req nonzero("NPUFIR"); - }; - - register NPUFIR_ACT1 - { - name "ES.NPU.NP_AT.REG.FIR_ACTION1_REG"; - scomaddr 0x08013d87; - capture type secondary; - capture group default; - capture req nonzero("NPUFIR"); - }; - - ############################################################################ - # NV Chiplet PLL Registers - ############################################################################ - - register NV_ERROR_REG - { - name "EH.TPCHIP.NET.PCBSLNV.ERROR_REG"; - scomaddr 0x080F001F; - capture group PllFIRs; - }; - - register NV_CONFIG_REG - { - name "EH.TPCHIP.NET.PCBSLNV.SLAVE_CONFIG_REG"; - scomaddr 0x080F001E; - capture group PllFIRs; - }; diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PB.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PB.rule deleted file mode 100755 index ec465dfb2..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PB.rule +++ /dev/null @@ -1,1237 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PB.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2015 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -################################################################################ -# -# Chiplet Register Adddresses Description -# ======= ======================= ============================================ -# PB 0x02000000 - 0x02FFFFFF PB pervasive logic, note that this does -# include the SCOM addresses characterized by -# the MCS target. See Mcs.rule for those -# address ranges. -# -################################################################################ - - ############################################################################ - # PB Chiplet Registers - ############################################################################ - - register PB_CHIPLET_CS_FIR - { - name "EH.TPC.XFIR"; - scomaddr 0x02040000; - capture group default; - }; - - register PB_CHIPLET_RE_FIR - { - name "EH.TPC.RFIR"; - scomaddr 0x02040001; - capture group default; - }; - - register PB_CHIPLET_FIR_MASK - { - name "EH.TPC.FIR_MASK"; - scomaddr 0x02040002; - capture group default; - }; - - register PB_CHIPLET_SPA - { - name "EH.TPC.EPS.FIR.SPATTN"; - scomaddr 0x02040004; - capture group default; - }; - - register PB_CHIPLET_SPA_MASK - { - name "EH.TPC.EPS.FIR.SPA_MASK"; - scomaddr 0x02040007; - capture group default; - }; - - ############################################################################ - # PB Chiplet LFIR - ############################################################################ - - register PB_LFIR - { - name "EH.TPC.LOCAL_FIR"; - scomaddr 0x0204000a; - reset (&, 0x0204000b); - mask (|, 0x0204000f); - capture group default; - }; - - register PB_LFIR_MASK - { - name "EH.TPC.EPS.FIR.LOCAL_FIR_MASK"; - scomaddr 0x0204000d; - capture group default; - }; - - register PB_LFIR_ACT0 - { - name "EH.TPC.EPS.FIR.LOCAL_FIR_ACTION0"; - scomaddr 0x02040010; - capture type secondary; - capture group default; - capture req nonzero("PB_LFIR"); - }; - - register PB_LFIR_ACT1 - { - name "EH.TPC.EPS.FIR.LOCAL_FIR_ACTION1"; - scomaddr 0x02040011; - capture type secondary; - capture group default; - capture req nonzero("PB_LFIR"); - }; - - ############################################################################ - # PB Chiplet NXDMAENGFIR - ############################################################################ - - register NXDMAENGFIR - { - name "EN.NX.DBG.NX_DMA_ENG_FIR"; - scomaddr 0x02013100; - reset (&, 0x02013101); - mask (|, 0x02013105); - capture group default; - }; - - register NXDMAENGFIR_MASK - { - name "EN.NX.DBG.NX_DMA_ENG_FIR_MASK"; - scomaddr 0x02013103; - capture group default; - }; - - register NXDMAENGFIR_MASK_OR - { - name "EN.NX.DBG.NX_DMA_ENG_FIR_MASK_OR"; - scomaddr 0x02013105; - capture group never; - access write_only; - }; - - register NXDMAENGFIR_ACT0 - { - name "EN.NX.DBG.NX_DMA_ENG_FIR_ACTION0"; - scomaddr 0x02013106; - capture type secondary; - capture group default; - capture req nonzero("NXDMAENGFIR"); - }; - - register NXDMAENGFIR_ACT1 - { - name "EN.NX.DBG.NX_DMA_ENG_FIR_ACTION1"; - scomaddr 0x02013107; - capture type secondary; - capture group default; - capture req nonzero("NXDMAENGFIR"); - }; - - register NXDMAENG_ERROR_REPORT_0 - { - name "EN.NX.DMA.SU_DMA_ERROR_REPORT_0"; - scomaddr 0x02013057; - capture group default; - capture group CerrRegs; - }; - - register NXDMAENG_ERROR_REPORT_1 - { - name "EN.NX.DMA.SU_DMA_ERROR_REPORT_1"; - scomaddr 0x02013058; - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # PB Chiplet NXCQFIR - ############################################################################ - - register NXCQFIR - { - name "EN.NX.PBI.CQ_WRAP.NXCQ_SCOM.NX_CQ_FIR_REG"; - scomaddr 0x02013080; - reset (&, 0x02013081); - mask (|, 0x02013085); - capture group default; - }; - - register NXCQFIR_MASK - { - name "EN.NX.PBI.CQ_WRAP.NXCQ_SCOM.NX_CQ_FIR_MASK_REG"; - scomaddr 0x02013083; - capture group default; - }; - - register NXCQFIR_ACT0 - { - name "EN.NX.PBI.CQ_WRAP.NXCQ_SCOM.NX_CQ_FIR_ACTION0_REG"; - scomaddr 0x02013086; - capture type secondary; - capture group default; - capture req nonzero("NXCQFIR"); - }; - - register NXCQFIR_ACT1 - { - name "EN.NX.PBI.CQ_WRAP.NXCQ_SCOM.NX_CQ_FIR_ACTION1_REG"; - scomaddr 0x02013087; - capture type secondary; - capture group default; - capture req nonzero("NXCQFIR"); - }; - - register NXCQFIR_ERROR_REPORT_0 - { - name "EN.NX.PBI.CQ_WRAP.NXCQ_SCOM.NX_PB_ERR_RPT_0"; - scomaddr 0x020130A2; - capture group default; - capture group CerrRegs; - }; - - register NXCQFIR_ERROR_REPORT_1 - { - name "EN.NX.PBI.CQ_WRAP.NXCQ_SCOM.NX_PB_ERR_RPT_1"; - scomaddr 0x020130A3; - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # PB Chiplet NXASFIR - ############################################################################ - - # NXASFIR has been modeled merely to collect FFDC. No attentions are - # expected from it. - register NXASFIR - { - name "EN.NX.AS.FIR_REG"; - scomaddr 0x020130c0; - capture group default; - }; - - register NXASFIR_MASK - { - name "EN.NX.AS.FIR_MASK_REG"; - scomaddr 0x020130c3; - capture group default; - }; - - register NXASFIR_IN_ERROR_HOLD_REPORT - { - name "EN.NX.AS.AS_IN_ERROR_HOLD"; - scomaddr 0x020130EB; - capture group default; - capture group CerrRegs; - }; - - register NXASFIR_ERROR_HOLD_REPORT - { - name "EN.NX.AS.AS_ERROR_HOLD"; - scomaddr 0x020130FF; - capture group default; - capture group CerrRegs; - }; - - register NXASFIR_EG_ERROR_HOLD_REPORT - { - name "EN.NX.AS.AS_EG_RLM.AS_EG_ERROR_HOLD"; - scomaddr 0x0201314E; - capture req funccall("isMuranoDD1"); - capture group default; - capture group CerrRegs; - }; - - register NXASFIR_CE_HOLD_REPORT - { - name "EN.NX.AS.AS_EG_RLM.AS_EG_CE_HOLD"; - scomaddr 0x0201314F; - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # PB Chiplet NXCXAFIR_0 - ############################################################################ - - register NXCXAFIR_0 - { - name "EN.NX.CXA0.CXA_XPT.XPT_SCOMFIR.FIR_REG"; - scomaddr 0x02013000; - reset (&, 0x02013001); - mask (|, 0x02013005); - capture group default; - }; - - register NXCXAFIR_0_MASK - { - name "EN.NX.CXA0.CXA_XPT.XPT_SCOMFIR.FIR_MASK_REG"; - scomaddr 0x02013003; - capture group default; - }; - - register NXCXAFIR_0_ACT0 - { - name "EN.NX.CXA0.CXA_XPT.XPT_SCOMFIR.FIR_ACTION0_REG"; - scomaddr 0x02013006; - capture type secondary; - capture group default; - capture req nonzero("NXCXAFIR_0"); - }; - - register NXCXAFIR_0_ACT1 - { - name "EN.NX.CXA0.CXA_XPT.XPT_SCOMFIR.FIR_ACTION1_REG"; - scomaddr 0x02013007; - capture type secondary; - capture group default; - capture req nonzero("NXCXAFIR_0"); - }; - - register NXCXAFIR_0_SNP_ERROR_REPORT - { - name "EN.NX.CXA0.CXA_SNPFE.SNP_REGS.CXA_SNP_ERROR_REPORT_REG"; - scomaddr 0x0201300A; - capture group default; - capture group CerrRegs; - }; - - register NXCXAFIR_0_APC1_ERROR_REPORT - { - name "EN.NX.CXA0.CXA_APC1.ERRRPT"; - scomaddr 0x0201300B; - capture group default; - capture group CerrRegs; - }; - - register NXCXAFIR_0_XPT_ERROR_REPORT - { - name "EN.NX.CXA0.XPT_ERROR_REPORT"; - scomaddr 0x0201300C; - capture group default; - capture group CerrRegs; - }; - - register NXCXAFIR_0_TLBI_ERROR_REPORT - { - name "EN.NX.CXA0.CXA_XPT.XPT_SCOMFIR.TLBI_ERROR_REPORT"; - scomaddr 0x0201300D; - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # PB Chiplet NXCXAFIR_1 - ############################################################################ - - # This FIR only exists on Naples. So we will have a conditional capture - # below, which is common on all P8/P8+ chips. - - register NXCXAFIR_1 - { - name "EN.NX.CXA1.CXA_XPT.XPT_SCOMFIR.FIR_REG"; - scomaddr 0x02013180; - reset (&, 0x02013181); - mask (|, 0x02013185); - capture req funccall("isNaplesProc"); - capture group default; - }; - - register NXCXAFIR_1_MASK - { - name "EN.NX.CXA1.CXA_XPT.XPT_SCOMFIR.FIR_MASK_REG"; - scomaddr 0x02013183; - capture req funccall("isNaplesProc"); - capture group default; - }; - - register NXCXAFIR_1_ACT0 - { - name "EN.NX.CXA1.CXA_XPT.XPT_SCOMFIR.FIR_ACTION0_REG"; - scomaddr 0x02013186; - capture type secondary; - capture req funccall("isNaplesProc"); - capture group default; - capture req nonzero("NXCXAFIR_1"); - }; - - register NXCXAFIR_1_ACT1 - { - name "EN.NX.CXA1.CXA_XPT.XPT_SCOMFIR.FIR_ACTION1_REG"; - scomaddr 0x02013187; - capture type secondary; - capture req funccall("isNaplesProc"); - capture group default; - capture req nonzero("NXCXAFIR_1"); - }; - - register NXCXAFIR_1_SNP_ERROR_REPORT - { - name "EN.NX.CXA1.CXA_SNPFE.SNP_REGS.CXA_SNP_ERROR_REPORT_REG"; - scomaddr 0x0201318A; - capture req funccall("isNaplesProc"); - capture group default; - capture group CerrRegs; - }; - - register NXCXAFIR_1_APC1_ERROR_REPORT - { - name "EN.NX.CXA1.CXA_APC1.ERRRPT"; - scomaddr 0x0201318B; - capture req funccall("isNaplesProc"); - capture group default; - capture group CerrRegs; - }; - - register NXCXAFIR_1_XPT_ERROR_REPORT - { - name "EN.NX.CXA1.XPT_ERROR_REPORT"; - scomaddr 0x0201318C; - capture req funccall("isNaplesProc"); - capture group default; - capture group CerrRegs; - }; - - register NXCXAFIR_1_TLBI_ERROR_REPORT - { - name "EN.NX.CXA1.CXA_XPT.XPT_SCOMFIR.TLBI_ERROR_REPORT"; - scomaddr 0x0201318D; - capture req funccall("isNaplesProc"); - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # PB Chiplet MCDFIR - ############################################################################ - - register MCDFIR - { - name "EH.PB.MCD.MCDCTL.FIR_REG"; - scomaddr 0x02013400; - reset (&, 0x02013401); - mask (|, 0x02013405); - capture group default; - }; - - register MCDFIR_MASK - { - name "EH.PB.MCD.MCDCTL.FIR_MASK_REG"; - scomaddr 0x02013403; - capture group default; - }; - - register MCDFIR_ACT0 - { - name "EH.PB.MCD.MCDCTL.FIR_ACTION0_REG"; - scomaddr 0x02013406; - capture type secondary; - capture group default; - capture req nonzero("MCDFIR"); - }; - - register MCDFIR_ACT1 - { - name "EH.PB.MCD.MCDCTL.FIR_ACTION1_REG"; - scomaddr 0x02013407; - capture type secondary; - capture group default; - capture req nonzero("MCDFIR"); - }; - - register MCDFIR_ERROR_REPORT - { - name "EH.PB.MCD.MCDCTL.MCD_ERPT"; - scomaddr 0x02013419; - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # PB Chiplet PBWESTFIR - ############################################################################ - - register PBWESTFIR - { - name "EH.PB.MISC.PB_WEST_FIR_REG"; - scomaddr 0x02010c00; - reset (&, 0x02010c01); - mask (|, 0x02010c05); - capture group default; - }; - - register PBWESTFIR_MASK - { - name "EH.PB.MISC.PB_WEST_FIR_MASK_REG"; - scomaddr 0x02010c03; - capture group default; - }; - - register PBWESTFIR_ACT0 - { - name "EH.PB.MISC.PB_WEST_FIR_ACTION0_REG"; - scomaddr 0x02010c06; - capture type secondary; - capture group default; - capture req nonzero("PBWESTFIR"); - }; - - register PBWESTFIR_ACT1 - { - name "EH.PB.MISC.PB_WEST_FIR_ACTION1_REG"; - scomaddr 0x02010c07; - capture type secondary; - capture group default; - capture req nonzero("PBWESTFIR"); - }; - - ############################################################################ - # PB Chiplet PBCENTFIR - ############################################################################ - - register PBCENTFIR - { - name "EH.PB.MISC.PB_CENT_FIR_REG"; - scomaddr 0x02010c40; - reset (&, 0x02010c41); - mask (|, 0x02010c45); - capture group default; - }; - - register PBCENTFIR_MASK - { - name "EH.PB.MISC.PB_CENT_FIR_MASK_REG"; - scomaddr 0x02010c43; - capture group default; - }; - - register PBCENTFIR_ACT1 - { - name "EH.PB.MISC.PB_CENT_FIR_ACTION1_REG"; - scomaddr 0x02010c47; - capture type secondary; - capture group default; - capture req nonzero("PBCENTFIR"); - }; - - register PBCENTFIR_ACT0 - { - name "EH.PB.MISC.PB_CENT_FIR_ACTION0_REG"; - scomaddr 0x02010c46; - capture type secondary; - capture group default; - capture req nonzero("PBCENTFIR"); - }; - - register PB_CENT_MODE - { - name "EH.PB.MISC.PB_CENT_MODE"; - scomaddr 0x02010C4A; - capture group PbCentMode; - }; - - ############################################################################ - # PB Chiplet PBEASTFIR - ############################################################################ - - register PBEASTFIR - { - name "EH.PB.MISC.PB_EAST_FIR_REG"; - scomaddr 0x02010c80; - reset (&, 0x02010c81); - mask (|, 0x02010c85); - capture group default; - }; - - register PBEASTFIR_MASK - { - name "EH.PB.MISC.PB_EAST_FIR_MASK_REG"; - scomaddr 0x02010c83; - capture group default; - }; - - register PBEASTFIR_ACT0 - { - name "EH.PB.MISC.PB_EAST_FIR_ACTION0_REG"; - scomaddr 0x02010c86; - capture type secondary; - capture group default; - capture req nonzero("PBEASTFIR"); - }; - - register PBEASTFIR_ACT1 - { - name "EH.PB.MISC.PB_EAST_FIR_ACTION1_REG"; - scomaddr 0x02010c87; - capture type secondary; - capture group default; - capture req nonzero("PBEASTFIR"); - }; - - # c_err_rpt for PBWESTFIR, PBCENTFIR, and PBEASTFIR - register PB_CENT_CR_ERROR - { - name "EH.PB.MISC.PB_CENT_CR_ERROR"; - scomaddr 0x02010c6c; - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # PB Chiplet PBEXTFIR - ############################################################################ - - # External checkstop register - Used for FFDC only - # Any attention generated from this FIR register indicates that there was a - # checkstop attention raised on another chip. Currently, we do not do any - # additional analysis in this FIR because we assume we will get an interrupt - # from the offending chip. This FIR will set PB_CHIPLET_FIR[2] which is - # currently ignored. - - register PBEXTFIR - { - name "EH.PB.MISC.EXTFIR_REG"; - scomaddr 0x02010c6e; - capture group default; - }; - - ############################################################################ - # PB Chiplet PSIHBFIR - ############################################################################ - - register PSIHBFIR - { - name "EN.TPC.PSIHB.PSIHB_FIR_REG"; - scomaddr 0x02010900; - reset (&, 0x02010901); - mask (|, 0x02010905); - capture group default; - }; - - register PSIHBFIR_MASK - { - name "EN.TPC.PSIHB.PSIHB_FIR_MASK_REG"; - scomaddr 0x02010903; - capture group default; - }; - - register PSIHBFIR_ACT0 - { - name "EN.TPC.PSIHB.PSIHB_FIR_ACTION0_REG"; - scomaddr 0x02010906; - capture type secondary; - capture group default; - capture req nonzero("PSIHBFIR"); - }; - - register PSIHBFIR_ACT1 - { - name "EN.TPC.PSIHB.PSIHB_FIR_ACTION1_REG"; - scomaddr 0x02010907; - capture type secondary; - capture group default; - capture req nonzero("PSIHBFIR"); - }; - - ############################################################################ - # PB Chiplet ICPFIR - ############################################################################ - - register ICPFIR - { - name "EN.TPC.INTP.SYNC_FIR_REG"; - scomaddr 0x020109c0; - reset (&, 0x020109c1); - mask (|, 0x020109c5); - capture group default; - }; - - register ICPFIR_MASK - { - name "EN.TPC.INTP.SYNC_FIR_MASK_REG"; - scomaddr 0x020109c3; - capture group default; - }; - - register ICPFIR_ACT0 - { - name "EN.TPC.INTP.SYNC_FIR_ACTION0_REG"; - scomaddr 0x020109c6; - capture type secondary; - capture group default; - capture req nonzero("ICPFIR"); - }; - - register ICPFIR_ACT1 - { - name "EN.TPC.INTP.SYNC_FIR_ACTION1_REG"; - scomaddr 0x020109c7; - capture type secondary; - capture group default; - capture req nonzero("ICPFIR"); - }; - - ############################################################################ - # PB Chiplet PBAFIR - ############################################################################ - - register PBAFIR - { - name "EN.TPC.PBA.PBAFIR"; - scomaddr 0x02010840; - reset (&, 0x02010841); - mask (|, 0x02010845); - capture group default; - }; - - register PBAFIR_MASK - { - name "EN.TPC.PBA.PBAFIRMASK"; - scomaddr 0x02010843; - capture group default; - }; - - register PBAFIR_ACT0 - { - name "EN.TPC.PBA.PBAFIRACT0"; - scomaddr 0x02010846; - capture type secondary; - capture group default; - capture req nonzero("PBAFIR"); - }; - - register PBAFIR_ACT1 - { - name "EN.TPC.PBA.PBAFIRACT1"; - scomaddr 0x02010847; - capture type secondary; - capture group default; - capture req nonzero("PBAFIR"); - }; - - register PBAFIR_ERROR_REPORT_0 - { - name "EN.TPC.PBA.PBAERRRPT0"; - scomaddr 0x0201084C; - capture group default; - capture group CerrRegs; - }; - - register PBAFIR_ERROR_REPORT_1 - { - name "EN.TPC.PBA.PBAERRRPT1"; - scomaddr 0x0201084D; - capture group default; - capture group CerrRegs; - }; - - register PBAFIR_ERROR_REPORT_2 - { - name "EN.TPC.PBA.PBAERRRPT2"; - scomaddr 0x0201084E; - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # PB Chiplet EHHCAFIR - ############################################################################ - - register EHHCAFIR - { - name "EH.TPC.HCA.EHHCA_FIR_REG"; - scomaddr 0x02010980; - reset (&, 0x02010981); - mask (|, 0x02010985); - capture group default; - }; - - register EHHCAFIR_MASK - { - name "EH.TPC.HCA.EHHCA_FIR_MASK_REG"; - scomaddr 0x02010983; - capture group default; - }; - - register EHHCAFIR_ACT0 - { - name "EH.TPC.HCA.EHHCA_FIR_ACTION0_REG"; - scomaddr 0x02010986; - capture type secondary; - capture group default; - capture req nonzero("EHHCAFIR"); - }; - - register EHHCAFIR_ACT1 - { - name "EH.TPC.HCA.EHHCA_FIR_ACTION1_REG"; - scomaddr 0x02010987; - capture type secondary; - capture group default; - capture req nonzero("EHHCAFIR"); - }; - - ############################################################################ - # PB Chiplet ENHCAFIR - ############################################################################ - - register ENHCAFIR - { - name "EN.TPC.BRIDGE.HCA.ENHCA_FIR_REG"; - scomaddr 0x02010940; - reset (&, 0x02010941); - mask (|, 0x02010945); - capture group default; - }; - - register ENHCAFIR_MASK - { - name "EN.TPC.BRIDGE.HCA.ENHCA_FIR_MASK_REG"; - scomaddr 0x02010943; - capture group default; - }; - - register ENHCAFIR_ACT0 - { - name "EN.TPC.BRIDGE.HCA.ENHCA_FIR_ACTION0_REG"; - scomaddr 0x02010946; - capture type secondary; - capture group default; - capture req nonzero("ENHCAFIR"); - }; - - register ENHCAFIR_ACT1 - { - name "EN.TPC.BRIDGE.HCA.ENHCA_FIR_ACTION1_REG"; - scomaddr 0x02010947; - capture type secondary; - capture group default; - capture req nonzero("ENHCAFIR"); - }; - - ############################################################################ - # PB Chiplet PCINESTFIR_0 - ############################################################################ - - register PCINESTFIR_0 - { - name "ES.PE_WRAP_TOP.PE0.PEPBCQ.PBCQ.FIR_REG"; - scomaddr 0x02012000; - reset (&, 0x02012001); - mask (|, 0x02012005); - capture group default; - }; - - register PCINESTFIR_0_MASK - { - name "ES.PE_WRAP_TOP.PE0.PEPBCQ.PBCQ.FIR_MASK_REG"; - scomaddr 0x02012003; - capture group default; - }; - - register PCINESTFIR_0_ACT0 - { - name "ES.PE_WRAP_TOP.PE0.PEPBCQ.PBCQ.FIR_ACTION0_REG"; - scomaddr 0x02012006; - capture type secondary; - capture group default; - capture req nonzero("PCINESTFIR_0"); - }; - - register PCINESTFIR_0_ACT1 - { - name "ES.PE_WRAP_TOP.PE0.PEPBCQ.PBCQ.FIR_ACTION1_REG"; - scomaddr 0x02012007; - capture type secondary; - capture group default; - capture req nonzero("PCINESTFIR_0"); - }; - - register PCINESTFIR0_ERROR_REPORT_0 - { - name "ES.PE_WRAP_TOP.PE0.PEPBCQ.PBCQ.CERR_RPT0_REG"; - scomaddr 0x0201201C; - capture group default; - capture group CerrRegs; - }; - - register PCINESTFIR0_ERROR_REPORT_1 - { - name "ES.PE_WRAP_TOP.PE0.PEPBCQ.PBCQ.CERR_RPT1_REG"; - scomaddr 0x0201201D; - capture group default; - capture group CerrRegs; - }; - - register PCINESTFIR0_ERROR_REPORT_2 - { - name "ES.PE_WRAP_TOP.PE0.PEPBCQ.PBCQ.CERR_RPT2_REG"; - scomaddr 0x0201201E; - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # PB Chiplet PCINESTFIR_1 - ############################################################################ - - register PCINESTFIR_1 - { - name "ES.PE_WRAP_TOP.PE1.PEPBCQ.PBCQ.FIR_REG"; - scomaddr 0x02012400; - reset (&, 0x02012401); - mask (|, 0x02012405); - capture group default; - }; - - register PCINESTFIR_1_MASK - { - name "ES.PE_WRAP_TOP.PE1.PEPBCQ.PBCQ.FIR_MASK_REG"; - scomaddr 0x02012403; - capture group default; - }; - - register PCINESTFIR_1_ACT0 - { - name "ES.PE_WRAP_TOP.PE1.PEPBCQ.PBCQ.FIR_ACTION0_REG"; - scomaddr 0x02012406; - capture type secondary; - capture group default; - capture req nonzero("PCINESTFIR_1"); - }; - - register PCINESTFIR_1_ACT1 - { - name "ES.PE_WRAP_TOP.PE1.PEPBCQ.PBCQ.FIR_ACTION1_REG"; - scomaddr 0x02012407; - capture type secondary; - capture group default; - capture req nonzero("PCINESTFIR_1"); - }; - - register PCINESTFIR1_ERROR_REPORT_0 - { - name "ES.PE_WRAP_TOP.PE1.PEPBCQ.PBCQ.CERR_RPT0_REG"; - scomaddr 0x0201241C; - capture group default; - capture group CerrRegs; - }; - - register PCINESTFIR1_ERROR_REPORT_1 - { - name "ES.PE_WRAP_TOP.PE1.PEPBCQ.PBCQ.CERR_RPT1_REG"; - scomaddr 0x0201241D; - capture group default; - capture group CerrRegs; - }; - - register PCINESTFIR1_ERROR_REPORT_2 - { - name "ES.PE_WRAP_TOP.PE1.PEPBCQ.PBCQ.CERR_RPT2_REG"; - scomaddr 0x0201241E; - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # PB Chiplet PCINESTFIR_2 - ############################################################################ - - register PCINESTFIR_2 - { - name "ES.PE_WRAP_TOP.PE2.PEPBCQ.PBCQ.FIR_REG"; - scomaddr 0x02012800; - reset (&, 0x02012801); - mask (|, 0x02012805); - capture group default; - }; - - register PCINESTFIR_2_MASK - { - name "ES.PE_WRAP_TOP.PE2.PEPBCQ.PBCQ.FIR_MASK_REG"; - scomaddr 0x02012803; - capture group default; - }; - - register PCINESTFIR_2_ACT0 - { - name "ES.PE_WRAP_TOP.PE2.PEPBCQ.PBCQ.FIR_ACTION0_REG"; - scomaddr 0x02012806; - capture type secondary; - capture group default; - capture req nonzero("PCINESTFIR_2"); - }; - - register PCINESTFIR_2_ACT1 - { - name "ES.PE_WRAP_TOP.PE2.PEPBCQ.PBCQ.FIR_ACTION1_REG"; - scomaddr 0x02012807; - capture type secondary; - capture group default; - capture req nonzero("PCINESTFIR_2"); - }; - - register PCINESTFIR2_ERROR_REPORT_0 - { - name "ES.PE_WRAP_TOP.PE2.PEPBCQ.PBCQ.CERR_RPT0_REG"; - scomaddr 0x0201281C; - capture group default; - capture group CerrRegs; - }; - - register PCINESTFIR2_ERROR_REPORT_1 - { - name "ES.PE_WRAP_TOP.PE2.PEPBCQ.PBCQ.CERR_RPT1_REG"; - scomaddr 0x0201281D; - capture group default; - capture group CerrRegs; - }; - - register PCINESTFIR2_ERROR_REPORT_2 - { - name "ES.PE_WRAP_TOP.PE2.PEPBCQ.PBCQ.CERR_RPT2_REG"; - scomaddr 0x0201281E; - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # PB Chiplet PCINESTFIR_3 - ############################################################################ - - # This FIR only exists on Naples. So we will have a conditional capture - # below, which is common on all P8/P8+ chips. - - register PCINESTFIR_3 - { - name "ES.PE_WRAP_TOP.PE3.PEPBCQ.PBCQ.FIR_REG"; - scomaddr 0x02012c00; - reset (&, 0x02012c01); - mask (|, 0x02012c05); - capture req funccall("isNaplesProc"); - capture group default; - }; - - register PCINESTFIR_3_MASK - { - name "ES.PE_WRAP_TOP.PE3.PEPBCQ.PBCQ.FIR_MASK_REG"; - scomaddr 0x02012c03; - capture req funccall("isNaplesProc"); - capture group default; - }; - - register PCINESTFIR_3_ACT0 - { - name "ES.PE_WRAP_TOP.PE3.PEPBCQ.PBCQ.FIR_ACTION0_REG"; - scomaddr 0x02012c06; - capture type secondary; - capture req funccall("isNaplesProc"); - capture group default; - capture req nonzero("PCINESTFIR_3"); - }; - - register PCINESTFIR_3_ACT1 - { - name "ES.PE_WRAP_TOP.PE3.PEPBCQ.PBCQ.FIR_ACTION1_REG"; - scomaddr 0x02012c07; - capture type secondary; - capture req funccall("isNaplesProc"); - capture group default; - capture req nonzero("PCINESTFIR_3"); - }; - - register PCINESTFIR3_ERROR_REPORT_0 - { - name "ES.PE_WRAP_TOP.PE3.PEPBCQ.PBCQ.CERR_RPT0_REG"; - scomaddr 0x02012c1C; - capture req funccall("isNaplesProc"); - capture group default; - capture group CerrRegs; - }; - - register PCINESTFIR3_ERROR_REPORT_1 - { - name "ES.PE_WRAP_TOP.PE3.PEPBCQ.PBCQ.CERR_RPT1_REG"; - scomaddr 0x02012c1D; - capture req funccall("isNaplesProc"); - capture group default; - capture group CerrRegs; - }; - - register PCINESTFIR3_ERROR_REPORT_2 - { - name "ES.PE_WRAP_TOP.PE3.PEPBCQ.PBCQ.CERR_RPT2_REG"; - scomaddr 0x02012c1E; - capture req funccall("isNaplesProc"); - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # PB Chiplet IOMCFIR_0 - ############################################################################ - - # This FIR does not exist on Murano, however, it is possible that the - # entire MCS block (0-3) may be disabled on Venice and Naples based on - # hardware availability. So we will have a conditional capture below, which - # is common on all P8/P8+ chips. - - register IOMCFIR_0 - { - name "IOMC0.BUSCTL.SCOM.FIR_REG"; - scomaddr 0x02011A00; - reset (&, 0x02011A01); - mask (|, 0x02011A05); - capture req funccall("mcsBlockConfigured_0"); - capture group default; - }; - - register IOMCFIR_0_MASK - { - name "IOMC0.BUSCTL.SCOM.FIR_MASK_REG"; - scomaddr 0x02011A03; - capture req funccall("mcsBlockConfigured_0"); - capture group default; - }; - - register IOMCFIR_0_MASK_OR - { - name "IOMC0.BUSCTL.SCOM.FIR_MASK_REG OR"; - scomaddr 0x02011A05; - access write_only; - capture group never; - }; - - register IOMCFIR_0_ACT0 - { - name "IOMC0.BUSCTL.SCOM.FIR_ACTION0_REG"; - scomaddr 0x02011A06; - capture type secondary; - capture group default; - capture req funccall("mcsBlockConfigured_0"); - capture req nonzero("IOMCFIR_0"); - }; - - register IOMCFIR_0_ACT1 - { - name "IOMC0.BUSCTL.SCOM.FIR_ACTION1_REG"; - scomaddr 0x02011A07; - capture type secondary; - capture group default; - capture req funccall("mcsBlockConfigured_0"); - capture req nonzero("IOMCFIR_0"); - }; - - ############################################################################ - # PB Chiplet IOMCFIR_1 - ############################################################################ - - # This FIR exists on all P8/P8+ processors, however, it is possible that the - # entire MCS block (4-7) may be disabled based on hardware availability. So - # we will have a conditional capture below, which is common on all P8/P8+ - # chips. - - register IOMCFIR_1 - { - name "IOMC1.BUSCTL.SCOM.FIR_REG"; - scomaddr 0x02011E00; - reset (&, 0x02011E01); - mask (|, 0x02011E05); - capture group default; - capture req funccall("mcsBlockConfigured_1"); - }; - - register IOMCFIR_1_MASK - { - name "IOMC1.BUSCTL.SCOM.FIR_MASK_REG"; - scomaddr 0x02011E03; - capture group default; - capture req funccall("mcsBlockConfigured_1"); - }; - - register IOMCFIR_1_MASK_OR - { - name "IOMC1.BUSCTL.SCOM.FIR_MASK_REG OR"; - scomaddr 0x02011E05; - access write_only; - capture group never; - }; - - register IOMCFIR_1_ACT0 - { - name "IOMC1.BUSCTL.SCOM.FIR_ACTION0_REG"; - scomaddr 0x02011E06; - capture type secondary; - capture group default; - capture req funccall("mcsBlockConfigured_1"); - capture req nonzero("IOMCFIR_1"); - }; - - register IOMCFIR_1_ACT1 - { - name "IOMC1.BUSCTL.SCOM.FIR_ACTION1_REG"; - scomaddr 0x02011E07; - capture type secondary; - capture group default; - capture req funccall("mcsBlockConfigured_1"); - capture req nonzero("IOMCFIR_1"); - }; - - ############################################################################ - # PB Chiplet PLL Registers - ############################################################################ - - register PB_ERROR_REG - { - name "EH.TPCHIP.NET.PCBSLNEST.ERROR_REG"; - scomaddr 0x020F001F; - capture group PllFIRs; - }; - - register PB_CONFIG_REG - { - name "EH.TPCHIP.NET.PCBSLNEST.SLAVE_CONFIG_REG"; - scomaddr 0x020F001E; - capture group PllFIRs; - }; - - ############################################################################ - # PB non-existent registers for capture - ############################################################################ - - register NXTRACE_ARRAY - { - name "Capture Data for NX Trace Array"; - capture group never; - }; - diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PCIE.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PCIE.rule deleted file mode 100755 index 3aa5dcd2c..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PCIE.rule +++ /dev/null @@ -1,346 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PCIE.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2015 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -################################################################################ -# -# Chiplet Register Adddresses Description -# ======= ======================= ============================================ -# PCIE 0x09000000 - 0x09FFFFFF PCIE pervasive logic -# -################################################################################ - - ############################################################################ - # PCIE Chiplet Registers - ############################################################################ - - register PCIE_CHIPLET_CS_FIR - { - name "ES.PE_WRAP_TOP.TPC.XFIR"; - scomaddr 0x09040000; - capture group default; - }; - - register PCIE_CHIPLET_RE_FIR - { - name "ES.PE_WRAP_TOP.TPC.RFIR"; - scomaddr 0x09040001; - capture group default; - }; - - register PCIE_CHIPLET_FIR_MASK - { - name "ES.PE_WRAP_TOP.TPC.FIR_MASK"; - scomaddr 0x09040002; - capture group default; - }; - - register PCIE_CHIPLET_SPA - { - name "ES.PE_WRAP_TOP.TPC.EPS.FIR.SPATTN"; - scomaddr 0x09040004; - capture group default; - }; - - register PCIE_CHIPLET_SPA_MASK - { - name "ES.PE_WRAP_TOP.TPC.EPS.FIR.SPA_MASK"; - scomaddr 0x09040007; - capture group default; - }; - - ############################################################################ - # PCIE Chiplet LFIR - ############################################################################ - - register PCIE_LFIR - { - name "ES.PE_WRAP_TOP.TPC.LOCAL_FIR"; - scomaddr 0x0904000a; - reset (&, 0x0904000b); - mask (|, 0x0904000f); - capture group default; - }; - - register PCIE_LFIR_MASK - { - name "ES.PE_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_MASK"; - scomaddr 0x0904000d; - capture group default; - }; - - register PCIE_LFIR_ACT0 - { - name "ES.PE_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_ACTION0"; - scomaddr 0x09040010; - capture type secondary; - capture group default; - capture req nonzero("PCIE_LFIR"); - }; - - register PCIE_LFIR_ACT1 - { - name "ES.PE_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_ACTION1"; - scomaddr 0x09040011; - capture type secondary; - capture group default; - capture req nonzero("PCIE_LFIR"); - }; - - ############################################################################ - # PCIE Chiplet PCICLOCKFIRs - # These FIRs are completely masked but they will be captured for FFDC. - ############################################################################ - - register PCICLOCKFIR_0 - { - name "PE0.ETU.RSB.PR_REGS.LEM.FIR_REG"; - scomaddr 0x09012000; - capture group default; - capture req funccall("phbConfigured_0"); - }; - - register PCICLOCKFIR_1 - { - name "PE1.ETU.RSB.PR_REGS.LEM.FIR_REG"; - scomaddr 0x09012400; - capture group default; - capture req funccall("phbConfigured_1"); - }; - - register PCICLOCKFIR_2 - { - name "PE2.ETU.RSB.PR_REGS.LEM.FIR_REG"; - scomaddr 0x09012800; - capture group default; - capture req funccall("phbConfigured_2"); - }; - - # This FIR only exist on Naples. So we will have a conditional capture - # below, which is common on all P8/P8+ chips. - - register PCICLOCKFIR_3 - { - name "PE3.ETU.RSB.PR_REGS.LEM.FIR_REG"; - scomaddr 0x09012C00; - capture group default; - capture req funccall("phbConfigured_3"); - }; - - register PCI_ETU_RESET_0 - { - name "ES.PE_WRAP_TOP.PE0.PBAIB.PEAIBREGS.PE_ETU_RESET_REG"; - scomaddr 0x0901200A; - capture group never; - }; - - register PCI_ETU_RESET_1 - { - name "ES.PE_WRAP_TOP.PE1.PBAIB.PEAIBREGS.PE_ETU_RESET_REG"; - scomaddr 0x0901240A; - capture group never; - }; - - register PCI_ETU_RESET_2 - { - name "ES.PE_WRAP_TOP.PE2.PBAIB.PEAIBREGS.PE_ETU_RESET_REG"; - scomaddr 0x0901280A; - capture group never; - }; - - register PCI_ETU_RESET_3 - { - name "ES.PE_WRAP_TOP.PE3.PBAIB.PEAIBREGS.PE_ETU_RESET_REG"; - scomaddr 0x09012C0A; - capture group never; - }; - - ############################################################################ - # PCIE Chiplet PBFFIR - ############################################################################ - - # Used for FFDC only. This FIR does not exist on Naples. So we will have a - # conditional capture below, which is common on all P8/P8+ chips. - - register PBFFIR - { - name "ES.PBES_WRAP_TOP.PBES_TOP.MISC_IOF.SCOM.PB_IOF_FIR_REG"; - scomaddr 0x09010800; - capture req funccall("isNotNaplesProc"); - capture group default; - }; - - register PBFIR_IOF0_ERROR_REPORT - { - name "ES.PBES_WRAP_TOP.PBES_TOP.IOF0.IOF.PCI_WRAP.PCI_BB.PB_IOF_ERR_STATUS"; - scomaddr 0x0901083A; - capture req funccall("isNotNaplesProc"); - capture group default; - capture group CerrRegs; - }; - - register PBFIR_IOF1_ERROR_REPORT - { - name "ES.PBES_WRAP_TOP.PBES_TOP.IOF1.IOF.PCI_WRAP.PCI_BB.PB_IOF_ERR_STATUS"; - scomaddr 0x0901083B; - capture req funccall("isNotNaplesProc"); - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # PCIE Chiplet IOPCIFIR_0 - ############################################################################ - - register IOPCIFIR_0 - { - name "IOP.IOP_X880.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_STATUS_REG"; - scomaddr 0x09011400; - reset (&, 0x09011401); - mask (|, 0x09011405); - capture group default; - }; - - register IOPCIFIR_0_MASK - { - name "IOP.IOP_X880.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_MASK_REG"; - scomaddr 0x09011403; - capture group default; - }; - - register IOPCIFIR_0_ACT0 - { - name "IOP.IOP_X880.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_ACTION0_REG"; - scomaddr 0x09011406; - capture type secondary; - capture group default; - capture req nonzero("IOPCIFIR_0"); - }; - - register IOPCIFIR_0_ACT1 - { - name "IOP.IOP_X880.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_ACTION1_REG"; - scomaddr 0x09011407; - capture type secondary; - capture group default; - capture req nonzero("IOPCIFIR_0"); - }; - - ############################################################################ - # PCIE Chiplet IOPCIFIR_1 - ############################################################################ - - register IOPCIFIR_1 - { - name "IOP.IOP_X881.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_STATUS_REG"; - scomaddr 0x09011840; - reset (&, 0x09011841); - mask (|, 0x09011845); - capture group default; - }; - - register IOPCIFIR_1_MASK - { - name "IOP.IOP_X881.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_MASK_REG"; - scomaddr 0x09011843; - capture group default; - }; - - register IOPCIFIR_1_ACT0 - { - name "IOP.IOP_X881.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_ACTION0_REG"; - scomaddr 0x09011846; - capture type secondary; - capture group default; - capture req nonzero("IOPCIFIR_1"); - }; - - register IOPCIFIR_1_ACT1 - { - name "IOP.IOP_X881.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_ACTION1_REG"; - scomaddr 0x09011847; - capture type secondary; - capture group default; - capture req nonzero("IOPCIFIR_1"); - }; - - ############################################################################ - # PCIE Chiplet IOPCIFIR_2 - ############################################################################ - - register IOPCIFIR_2 - { - name "IOP.IOP_X882.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_STATUS_REG"; - scomaddr 0x09011C40; - reset (&, 0x09011C41); - mask (|, 0x09011C45); - capture req funccall("isNaplesProc"); - capture group default; - }; - - register IOPCIFIR_2_MASK - { - name "IOP.IOP_X882.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_MASK_REG"; - scomaddr 0x09011C43; - capture req funccall("isNaplesProc"); - capture group default; - }; - - register IOPCIFIR_2_ACT0 - { - name "IOP.IOP_X882.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_ACTION0_REG"; - scomaddr 0x09011C46; - capture type secondary; - capture req funccall("isNaplesProc"); - capture group default; - capture req nonzero("IOPCIFIR_2"); - }; - - register IOPCIFIR_2_ACT1 - { - name "IOP.IOP_X882.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_ACTION1_REG"; - scomaddr 0x09011C47; - capture type secondary; - capture req funccall("isNaplesProc"); - capture group default; - capture req nonzero("IOPCIFIR_2"); - }; - - ############################################################################ - # PCIE Chiplet PLL Registers - ############################################################################ - - register PCI_ERROR_REG - { - name "EH.TPCHIP.NET.PCBSLPCI.ERROR_REG"; - scomaddr 0x090F001F; - capture group PllFIRs; - }; - - register PCI_CONFIG_REG - { - name "EH.TPCHIP.NET.PCBSLPCI.SLAVE_CONFIG_REG"; - scomaddr 0x090F001E; - capture group PllFIRs; - }; diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_TP.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_TP.rule deleted file mode 100755 index 44dcdbf47..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_TP.rule +++ /dev/null @@ -1,454 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc_regs_TP.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2015 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -################################################################################ -# -# Chiplet Register Adddresses Description -# ======= ======================= ============================================ -# TP 0x01000000 - 0x01FFFFFF TP pervasive logic -# -################################################################################ - - ############################################################################ - # TP Chiplet Registers - ############################################################################ - - register TP_CHIPLET_CS_FIR - { - name "EH.TPCHIP.TPC.XFIR"; - scomaddr 0x01040000; - capture group default; - }; - - register TP_CHIPLET_RE_FIR - { - name "EH.TPCHIP.TPC.RFIR"; - scomaddr 0x01040001; - capture group default; - }; - - register TP_CHIPLET_FIR_MASK - { - name "EH.TPCHIP.TPC.FIR_MASK"; - scomaddr 0x01040002; - capture group default; - }; - - register TP_CHIPLET_SPA - { - name "EH.TPCHIP.TPC.EPS.FIR.SPATTN"; - scomaddr 0x01040004; - capture group default; - }; - - register TP_CHIPLET_SPA_MASK - { - name "EH.TPCHIP.TPC.EPS.FIR.SPA_MASK"; - scomaddr 0x01040007; - capture group default; - }; - - ############################################################################ - # TP Chiplet LFIR - ############################################################################ - - register TP_LFIR - { - name "EH.TPCHIP.TPC.LOCAL_FIR"; - scomaddr 0x0104000a; - reset (&, 0x0104000b); - mask (|, 0x0104000f); - capture group default; - capture group PllFIRs; - }; - - register TP_LFIR_AND - { - name "EH.TPCHIP.TPC.LOCAL_FIR_AND"; - scomaddr 0x0104000b; - capture group never; - access write_only; - }; - - register TP_LFIR_MASK - { - name "EH.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_MASK"; - scomaddr 0x0104000d; - capture group default; - capture group PllFIRs; - }; - - register TP_LFIR_MASK_OR - { - name "EH.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_MASK_OR"; - scomaddr 0x0104000f; - capture group never; - access write_only; - }; - - register TP_LFIR_ACT0 - { - name "EH.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_ACTION0"; - scomaddr 0x01040010; - capture type secondary; - capture group never; - capture req nonzero("TP_LFIR"); - }; - - register TP_LFIR_ACT1 - { - name "EH.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_ACTION1"; - scomaddr 0x01040011; - capture type secondary; - capture group never; - capture req nonzero("TP_LFIR"); - }; - - ############################################################################ - # TP Chiplet OCCFIR - ############################################################################ - - register OCCFIR - { - name "EH.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIR"; - scomaddr 0x01010800; - reset (&, 0x01010801); - mask (|, 0x01010805); - capture group default; - }; - - register OCCFIR_MASK - { - name "EH.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIRMASK"; - scomaddr 0x01010803; - capture group default; - }; - - register OCCFIR_ACT0 - { - name "EH.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIRACT0"; - scomaddr 0x01010806; - capture type secondary; - capture group default; - capture req nonzero("OCCFIR"); - }; - - register OCCFIR_ACT1 - { - name "EH.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIRACT1"; - scomaddr 0x01010807; - capture type secondary; - capture group default; - capture req nonzero("OCCFIR"); - }; - - register OCCFIR_ERROR_REPORT - { - name "EH.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCERRRPT"; - scomaddr 0x0101080A; - capture group default; - capture group CerrRegs; - }; - - ############################################################################ - # TP Chiplet PBAMFIR - ############################################################################ - - register PBAMFIR - { - name "EH.TPCHIP.PIB.LPCM.LPC.SYNC_FIR_REG"; - scomaddr 0x01010c00; - reset (&, 0x01010c01); - mask (|, 0x01010c05); - capture group default; - }; - - register PBAMFIR_MASK - { - name "EH.TPCHIP.PIB.LPCM.LPC.SYNC_FIR_MASK_REG"; - scomaddr 0x01010c03; - capture group default; - }; - - register PBAMFIR_ACT0 - { - name "EH.TPCHIP.PIB.LPCM.LPC.SYNC_FIR_ACTION0_REG"; - scomaddr 0x01010c06; - capture type secondary; - capture group default; - capture req nonzero("PBAMFIR"); - }; - - register PBAMFIR_ACT1 - { - name "EH.TPCHIP.PIB.LPCM.LPC.SYNC_FIR_ACTION1_REG"; - scomaddr 0x01010c07; - capture type secondary; - capture group default; - capture req nonzero("PBAMFIR"); - }; - - ############################################################################ - # TP Chiplet PMCFIR - ############################################################################ - - register PMCFIR - { - name "EH.TPCHIP.OCC.PMC.PMC_LFIR_ERR_REG"; - scomaddr 0x01010840; - reset (&, 0x01010841); - mask (|, 0x01010845); - capture group default; - }; - - register PMCFIR_MASK - { - name "EH.TPCHIP.OCC.PMC.PMC_LFIR_ERR_MASK_REG"; - scomaddr 0x01010843; - capture group default; - }; - - register PMCFIR_ACT0 - { - name "EH.TPCHIP.OCC.PMC.PMC_LFIR_ACTION0_REG"; - scomaddr 0x01010846; - capture type secondary; - capture group default; - capture req nonzero("PMCFIR"); - }; - - register PMCFIR_ACT1 - { - name "EH.TPCHIP.OCC.PMC.PMC_LFIR_ACTION1_REG"; - scomaddr 0x01010847; - capture type secondary; - capture group default; - capture req nonzero("PMCFIR"); - }; - - ############################################################################ - # TOD Registers - ############################################################################ - - register TOD_MPCR - { - name "EH.TPCHIP.PIB.TOD.TOD_M_PATH_CTRL_REG"; - scomaddr 0x00040000; - capture group TODReg; - }; - - register TOD_PCRP0 - { - name "EH.TPCHIP.PIB.TOD.TOD_PRI_PORT_0_CTRL_REG"; - scomaddr 0x00040001; - capture group TODReg; - }; - - register TOD_PCRP1 - { - name "EH.TPCHIP.PIB.TOD.TOD_PRI_PORT_1_CTRL_REG"; - scomaddr 0x00040002; - capture group TODReg; - }; - - register TOD_SCRP0 - { - name "EH.TPCHIP.PIB.TOD.TOD_SEC_PORT_0_CTRL_REG"; - scomaddr 0x00040003; - capture group TODReg; - }; - - register TOD_SCRP1 - { - name "EH.TPCHIP.PIB.TOD.TOD_SEC_PORT_1_CTRL_REG"; - scomaddr 0x00040004; - capture group TODReg; - }; - - register TOD_SPCR - { - name "EH.TPCHIP.PIB.TOD.TOD_S_PATH_CTRL_REG"; - scomaddr 0x00040005; - capture group TODReg; - }; - - register TOD_IPCR - { - name "EH.TPCHIP.PIB.TOD.TOD_I_PATH_CTRL_REG"; - scomaddr 0x00040006; - capture group TODReg; - }; - - register TOD_PSMSCR - { - name "EH.TPCHIP.PIB.TOD.TOD_PSS_MSS_CTRL_REG"; - scomaddr 0x00040007; - capture group TODReg; - }; - - register TOD_STATUSREGISTER - { - name "EH.TPCHIP.PIB.TOD.TOD_PSS_MSS_STATUS_REG"; - scomaddr 0x00040008; - capture group TODReg; - }; - - register TOD_MPSR - { - name "EH.TPCHIP.PIB.TOD.TOD_M_PATH_STATUS_REG"; - scomaddr 0x00040009; - capture group TODReg; - }; - - register TOD_SPSR - { - name "EH.TPCHIP.PIB.TOD.TOD_S_PATH_STATUS_REG"; - scomaddr 0x0004000A; - capture group TODReg; - }; - - register TOD_CCR - { - name "EH.TPCHIP.PIB.TOD.TOD_CHIP_CTRL_REG"; - scomaddr 0x00040010; - capture group TODReg; - }; - - register TOD_TRACEDATA_SET_1 - { - name "EH.TPCHIP.PIB.TOD.TOD_TRACE_DATA_1_REG"; - scomaddr 0x0004001D; - capture group TODReg; - }; - - register TOD_TRACEDATA_SET_2 - { - name "EH.TPCHIP.PIB.TOD.TOD_TRACE_DATA_2_REG"; - scomaddr 0x0004001E; - capture group TODReg; - }; - - register TOD_TRACEDATA_SET_3 - { - name "EH.TPCHIP.PIB.TOD.TOD_TRACE_DATA_3_REG"; - scomaddr 0x0004001F; - capture group TODReg; - }; - - register TOD_FSM - { - name "EH.TPCHIP.PIB.TOD.TOD_FSM_REG"; - scomaddr 0x00040024; - capture group TODReg; - }; - - register TOD_TX_TTYPE - { - name "EH.TPCHIP.PIB.TOD.TOD_TX_TTYPE_CTRL_REG"; - scomaddr 0x00040027; - capture group TODReg; - }; - - register TOD_RX_TTYPE - { - name "EH.TPCHIP.PIB.TOD.TOD_RX_TTYPE_CTRL_REG"; - scomaddr 0x00040029; - capture group TODReg; - }; - - register TOD_ERRORREGISTER - { - name "EH.TPCHIP.PIB.TOD.TOD_ERROR_REG"; - scomaddr 0x00040030; - capture group TODReg; - reset (^, 0x40030); - }; - - register TOD_ERRORMASK - { - name "EH.TPCHIP.PIB.TOD.TOD_ERROR_MASK_REG"; - scomaddr 0x40032; - capture group TODReg; - }; - - register TOD_ERRORACTION - { - name "EH.TPCHIP.PIB.TOD.TOD_ERROR_ROUTING_REG"; - scomaddr 0x00040033; - capture group TODReg; - }; - - ############################################################################ - # Registers for FFDC only - ############################################################################ - - register PMC_SPIV_STATUS_REG - { - name "PMC_SPIV_STATUS_REG"; - scomaddr 0x00062046; - access read_only; - capture group default; - }; - - register PMC_PSTATE_MONITOR_AND_CTRL_REG - { - name "PMC_PSTATE_MONITOR_AND_CTRL_REG"; - scomaddr 0x00062002; - access read_only; - capture group default; - }; - - register GLOBAL_ACTUAL_VOLTAGE_REG - { - name "GLOBAL_ACTUAL_VOLTAGE_REG"; - scomaddr 0x00062008; - access read_only; - capture group default; - }; - - register PMC_O2S_STATUS_REG - { - name "PMC_O2S_STATUS_REG"; - scomaddr 0x00062056; - access read_only; - capture group default; - }; - - register PMC_O2S_WDATA_REG - { - name "PMC_O2S_WDATA_REG"; - scomaddr 0x00062058; - access read_only; - capture group default; - }; - - register PMC_O2S_RDATA_REG - { - name "PMC_O2S_RDATA_REG"; - scomaddr 0x00062059; - access read_only; - capture group default; - }; - diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_XBUS.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_XBUS.rule deleted file mode 100755 index 52e3d609b..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_XBUS.rule +++ /dev/null @@ -1,337 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc_regs_XBUS.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -################################################################################ -# -# Chiplet Register Adddresses Description -# ======= ======================= ============================================ -# XBUS 0x04000000 - 0x0400FFFF XBUS pervasive logic -# -################################################################################ - - ############################################################################ - # XBUS Chiplet Registers - ############################################################################ - - register XBUS_CHIPLET_CS_FIR - { - name "EN.PB.TPC.XFIR"; - scomaddr 0x04040000; - capture group default; - capture req funccall("isXBusEnabled"); - }; - - register XBUS_CHIPLET_RE_FIR - { - name "EN.PB.TPC.RFIR"; - scomaddr 0x04040001; - capture group default; - capture req funccall("isXBusEnabled"); - }; - - register XBUS_CHIPLET_FIR_MASK - { - name "EN.PB.TPC.FIR_MASK"; - scomaddr 0x04040002; - capture group default; - capture req funccall("isXBusEnabled"); - }; - - ############################################################################ - # XBUS Chiplet LFIR - ############################################################################ - - register XBUS_LFIR - { - name "EN.PB.TPC.LOCAL_FIR"; - scomaddr 0x0404000a; - reset (&, 0x0404000b); - mask (|, 0x0404000f); - capture group default; - capture req funccall("isXBusEnabled"); - }; - - register XBUS_LFIR_MASK - { - name "EN.PB.TPC.EPS.FIR.LOCAL_FIR_MASK"; - scomaddr 0x0404000d; - capture group default; - capture req funccall("isXBusEnabled"); - }; - - register XBUS_LFIR_ACT0 - { - name "EN.PB.TPC.EPS.FIR.LOCAL_FIR_ACTION0"; - scomaddr 0x04040010; - capture type secondary; - capture group default; - capture req nonzero("XBUS_LFIR"); - capture req funccall("isXBusEnabled"); - }; - - register XBUS_LFIR_ACT1 - { - name "EN.PB.TPC.EPS.FIR.LOCAL_FIR_ACTION1"; - scomaddr 0x04040011; - capture type secondary; - capture group default; - capture req nonzero("XBUS_LFIR"); - capture req funccall("isXBusEnabled"); - }; - - ############################################################################ - # XBUS Chiplet PBENFIR - ############################################################################ - - register PBENFIR - { - name "EN.PB.PBEN.MISC_IO.SCOM.FIR_REG"; - scomaddr 0x04010c00; - reset (&, 0x04010c01); - mask (|, 0x04010c05); - capture group default; - capture req funccall("isXBusEnabled"); - }; - - register PBENFIR_MASK - { - name "EN.PB.PBEN.MISC_IO.SCOM.FIR_MASK_REG"; - scomaddr 0x04010c03; - capture group default; - capture req funccall("isXBusEnabled"); - }; - - register PBENFIR_ACT0 - { - name "EN.PB.PBEN.MISC_IO.SCOM.FIR_REG_ACTION0"; - scomaddr 0x04010c06; - capture type secondary; - capture group default; - capture req nonzero("PBENFIR"); - capture req funccall("isXBusEnabled"); - }; - - register PBENFIR_ACT1 - { - name "EN.PB.PBEN.MISC_IO.SCOM.FIR_REG_ACTION1"; - scomaddr 0x04010c07; - capture type secondary; - capture group default; - capture req nonzero("PBENFIR"); - capture req funccall("isXBusEnabled"); - }; - - ############################################################################ - # XBUS Chiplet IOXFIR_0 (Venice only) - ############################################################################ - - # This FIR does not exist on Murano. So we will have a conditional capture - # below, which is common on all P8/P8+ chips. - - register IOXFIR_0 - { - name "XBUS01.X0.BUSCTL.SCOM.FIR_REG"; - scomaddr 0x04011000; - reset (&, 0x04011001); - mask (|, 0x04011005); - capture req funccall("notMuranoAndXbEnabled"); - capture group default; - }; - - register IOXFIR_0_MASK - { - name "XBUS01.X0.BUSCTL.SCOM.FIR_MASK_REG"; - scomaddr 0x04011003; - capture req funccall("notMuranoAndXbEnabled"); - capture group default; - }; - - register IOXFIR_0_ACT0 - { - name "XBUS01.X0.BUSCTL.SCOM.FIR_ACTION0_REG"; - scomaddr 0x04011006; - capture type secondary; - capture req funccall("notMuranoAndXbEnabled"); - capture req nonzero("IOXFIR_0"); - capture group default; - }; - - register IOXFIR_0_ACT1 - { - name "XBUS01.X0.BUSCTL.SCOM.FIR_ACTION1_REG"; - scomaddr 0x04011007; - capture type secondary; - capture req funccall("notMuranoAndXbEnabled"); - capture req nonzero("IOXFIR_0"); - capture group default; - }; - - ############################################################################ - # XBUS Chiplet IOXFIR_1 - ############################################################################ - - register IOXFIR_1 - { - name "XBUS01.X1.BUSCTL.SCOM.FIR_REG"; - scomaddr 0x04011400; - reset (&, 0x04011401); - mask (|, 0x04011405); - capture group default; - capture req funccall("isXBusEnabled"); - }; - - register IOXFIR_1_MASK - { - name "XBUS01.X1.BUSCTL.SCOM.FIR_MASK_REG"; - scomaddr 0x04011403; - capture group default; - capture req funccall("isXBusEnabled"); - }; - - register IOXFIR_1_ACT0 - { - name "XBUS01.X1.BUSCTL.SCOM.FIR_ACTION0_REG"; - scomaddr 0x04011406; - capture type secondary; - capture group default; - capture req nonzero("IOXFIR_1"); - capture req funccall("isXBusEnabled"); - }; - - register IOXFIR_1_ACT1 - { - name "XBUS01.X1.BUSCTL.SCOM.FIR_ACTION1_REG"; - scomaddr 0x04011407; - capture type secondary; - capture group default; - capture req nonzero("IOXFIR_1"); - capture req funccall("isXBusEnabled"); - }; - - ############################################################################ - # XBUS Chiplet IOXFIR_2 (Venice only) - ############################################################################ - - # This FIR does not exist on Murano. So we will have a conditional capture - # below, which is common on all P8/P8+ chips. - - register IOXFIR_2 - { - name "XBUS23.X1.BUSCTL.SCOM.FIR_REG"; - scomaddr 0x04011C00; - reset (&, 0x04011C01); - mask (|, 0x04011C05); - capture req funccall("notMuranoAndXbEnabled"); - capture group default; - }; - - register IOXFIR_2_MASK - { - name "XBUS23.X1.BUSCTL.SCOM.FIR_MASK_REG"; - scomaddr 0x04011C03; - capture req funccall("notMuranoAndXbEnabled"); - capture group default; - }; - - register IOXFIR_2_ACT0 - { - name "XBUS23.X1.BUSCTL.SCOM.FIR_ACTION0_REG"; - scomaddr 0x04011C06; - capture type secondary; - capture req funccall("notMuranoAndXbEnabled"); - capture req nonzero("IOXFIR_2"); - capture group default; - }; - - register IOXFIR_2_ACT1 - { - name "XBUS23.X1.BUSCTL.SCOM.FIR_ACTION1_REG"; - scomaddr 0x04011C07; - capture type secondary; - capture req funccall("notMuranoAndXbEnabled"); - capture req nonzero("IOXFIR_2"); - capture group default; - }; - - ############################################################################ - # XBUS Chiplet IOXFIR_3 (Venice only) - ############################################################################ - - # This FIR does not exist on Murano. So we will have a conditional capture - # below, which is common on all P8/P8+ chips. - - register IOXFIR_3 - { - name "XBUS23.X0.BUSCTL.SCOM.FIR_REG"; - scomaddr 0x04011800; - reset (&, 0x04011801); - mask (|, 0x04011805); - capture req funccall("notMuranoAndXbEnabled"); - capture group default; - }; - - register IOXFIR_3_MASK - { - name "XBUS23.X0.XBUS1.BUSCTL.SCOM.FIR_MASK_REG"; - scomaddr 0x04011803; - capture req funccall("notMuranoAndXbEnabled"); - capture group default; - }; - - register IOXFIR_3_ACT0 - { - name "XBUS23.X0.XBUS1.BUSCTL.SCOM.FIR_ACTION0_REG"; - scomaddr 0x04011806; - capture type secondary; - capture req funccall("notMuranoAndXbEnabled"); - capture req nonzero("IOXFIR_3"); - capture group default; - }; - - register IOXFIR_3_ACT1 - { - name "XBUS23.X0.XBUS1.BUSCTL.SCOM.FIR_ACTION1_REG"; - scomaddr 0x04011807; - capture type secondary; - capture req funccall("notMuranoAndXbEnabled"); - capture req nonzero("IOXFIR_3"); - capture group default; - }; - - ############################################################################ - # XBUS Chiplet PSIXBUSFIR - ############################################################################ - - # All bits in this FIR are reserved so PRD is not expected to analyze this - # FIR. Capture the FIR for FFDC, just in case. - - register PSIXBUSFIR - { - name "PSI.PSI_MAC.PSI_SCOM.FIR_REG"; - scomaddr 0x04012400; - capture group default; - capture req funccall("isXBusEnabled"); - }; - diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_common.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_common.rule deleted file mode 100755 index 8b6c5a275..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_common.rule +++ /dev/null @@ -1,173 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc_regs_common.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2015 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -################################################################################ -# -# Scope: -# Registers for the following chiplets: -# -# Chiplet Register Adddresses Description -# ======= ======================= ============================================ -# TP 0x01000000 - 0x01FFFFFF TP pervasive logic -# PB 0x02000000 - 0x02FFFFFF PB pervasive logic, note that this does -# include the SCOM addresses characterized by -# the MCS target. See Mcs.rule for those -# address ranges. -# XBUS 0x04000000 - 0x0400FFFF XBUS pervasive logic -# PCIE 0x09000000 - 0x09FFFFFF PCIE pervasive logic -# -################################################################################ - - ############################################################################# - # # - # ###### # - # # # ###### #### ### #### ##### ###### ##### #### # - # # # # # # # # # # # # # # - # ###### ##### # # #### # ##### # # #### # - # # # # # ### # # # # ##### # # - # # # # # # # # # # # # # # # # - # # # ###### #### ### #### # ###### # # #### # - # # - ############################################################################# - - ############################################################################ - # Global Broadcast Registers - ############################################################################ - - register GLOBAL_CS_FIR - { - name "Global Checkstop Attention FIR"; - scomaddr 0x570F001C; - capture group default; - }; - - register GLOBAL_RE_FIR - { - name "Global Recoverable Attention FIR"; - scomaddr 0x570F001B; - capture group default; - }; - - register GLOBAL_SPA - { - name "Global Special Attention FIR"; - scomaddr 0x570F001A; - capture group default; - }; - - register GLOBALUNITXSTPFIR - { - name "Virtual Global Unit Checkstop FIR"; - scomaddr 0x51040001; - capture group default; - capture req funccall("CoreConfiguredAndNotHostboot"); - }; - - ######################################################################## - # Non-existent Registers for Capture - ######################################################################## - register VPD_FAILED_LANES_0TO63 - { - name "Bit map 0-63 of failed lanes read from VPD"; - scomaddr 0xFFFF0001; - access no_access; - capture group never; - }; - - register VPD_FAILED_LANES_64TO127 - { - name "Bit map 64-127 of failed lanes read from VPD"; - scomaddr 0xFFFF0002; - access no_access; - capture group never; - }; - - register ALL_FAILED_LANES_0TO63 - { - name "Bit map 0-63 of failed lanes from io_read_erepair"; - scomaddr 0xFFFF0003; - access no_access; - capture group never; - }; - - register ALL_FAILED_LANES_64TO127 - { - name "Bit map 64-127 of failed lanes from io_read_erepair"; - scomaddr 0xFFFF0004; - access no_access; - capture group never; - }; - - ############################################################################ - # Non-FIR Registers - ############################################################################ - - register TODWOF - { - name "Time of Day / WOF Counter"; - scomaddr 0x00040020; - capture group default; - }; - - ############################################################################ - # PLL Registers - ############################################################################ - - register CFAM_FSI_STATUS - { - name "TPC.FSI.FSI2PIB.STATUS"; - scomaddr 0x00001007; - capture group never; - }; - - register CFAM_FSI_GP7 - { - name "TPC.FSI.FSI_MAILBOX.FSXCOMP.FSXLOG.FSIGP7"; - scomaddr 0x00002816; - capture group never; - }; - - register PCIE_OSC_SWITCH - { - name "TPC.FSI.FSI_MAILBOX.FSXCOMP.FSXLOG.SNS1LTH"; - scomaddr 0x00050019; - capture group PllFIRs; - }; - - register OSCERR - { - name "EH.TPCHIP.TPC.ITR.OSCERR.OSCERR_HOLD"; - scomaddr 0x01020019; - capture group PllFIRs; - }; - - register OSCERR_MASK - { - name "EH.TPCHIP.TPC.ITR.OSCERR.OSCERR_MASK"; - scomaddr 0x0102001A; - capture group PllFIRs; - }; - - diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaDynMemDealloc_rt.C b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaDynMemDealloc_rt.C deleted file mode 100755 index ba3c22e1c..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaDynMemDealloc_rt.C +++ /dev/null @@ -1,823 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaDynMemDealloc_rt.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include <prdfExtensibleChip.H> -#include <prdfCenMbaDynMemDealloc_rt.H> -#include <prdfTrace.H> -#include <prdfPlatServices.H> -#include <prdfCenMbaDataBundle.H> -#include <prdfCenMembufDataBundle.H> -#include <prdfCenAddress.H> - - -//------------------------------------------------------------------------------ -// Function Definitions -//------------------------------------------------------------------------------ - -using namespace TARGETING; - -namespace PRDF -{ -using namespace PlatServices; - -namespace DEALLOC -{ - -enum -{ - DDR3 = fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3, - DDR4 = fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4, - - HASH_MODE_128B = 0, - HASH_MODE_256B, -}; - -/** @brief Combines the rank and bank together. Note that the rank/bank will be - * split in two to make room for the row and column. This function will - * return the rank/bank in both parts (right justified). - * @param i_ds DIMM select (D). - * @param i_mrnk Master rank (M0-M2). - * @param i_srnk Slave rank (S0-S2). - * @param i_numDs Number of configured DIMM select bits. - * @param i_numMrnk Number of configured master rank bits. - * @param i_numSrnk Number of configured slave rank bits. - * @param i_bnk Bank (DDR3: B2-B0, DDR4: BG1-BG0,B1-B0). - * @param i_ddrVer DDR version (DDR3 or DDR4). - * @param i_hash Hash value (0, 1, or 2). - * @param o_upperRnkBnk Upper rank/bank bits (right justified). - * @param o_numUpperRnkBnk Number of configured upper rank/bank bits. - * @param o_lowerRnkBnk Lower rank/bank bits (right justified). - * @param o_numLowerRnkBnk Number of configured lower rank/bank bits. - */ -void getRankBank( uint64_t i_ds, uint64_t i_mrnk, uint64_t i_srnk, - uint64_t i_numDs, uint64_t i_numMrnk, uint64_t i_numSrnk, - uint64_t i_bnk, uint64_t i_ddrVer, uint64_t i_hash, - uint64_t & o_upperRnkBnk, uint64_t & o_numUpperRnkBnk, - uint64_t & o_lowerRnkBnk, uint64_t & o_numLowerRnkBnk ) -{ - // The number of bank bits can be determined from the DDR version. - uint64_t numBnk = (DDR3 == i_ddrVer) ? 3 : 4; - - // Calculate the number of combined rank/bank bits. - uint64_t numRnkBnk = i_numDs + i_numMrnk + i_numSrnk + numBnk; - - // Build the rank (D,M0-M2,S0-S2) - uint64_t rnk = i_ds; - rnk <<= i_numMrnk; rnk |= i_mrnk; - rnk <<= i_numSrnk; rnk |= i_srnk; - - // Get the rank components - uint64_t upperRnk = (rnk & ~0x1) << numBnk; - uint64_t lowerRnk = (rnk & 0x1) << numBnk; - - // Get the bank components - uint64_t upperBnk = 0, lowerBnk = 0; - if ( DDR3 == i_ddrVer ) - { - upperBnk = i_bnk & 0x4; // B2 - lowerBnk = i_bnk & 0x3; // B1-B0 - } - else // DDR4 - { - upperBnk = (i_bnk & 0x3) << 2; // B1-B0 - lowerBnk = (i_bnk & 0xC) >> 2; // BG1-BG0 - } - - // The last bit of the rank and the upper part of the bank will be swapped - // in certain conditions. - bool swap = ( (0 != i_hash) || // Normal case: hash is non-zero - (0 != i_numSrnk) || // Special case: any slave ranks - (3 == i_numMrnk) ); // Special case: 8 master ranks (3 bits) - - // Combine rank and bank. - uint64_t rnkBnk = upperRnk | - lowerRnk >> (swap ? (numBnk - 2) : 0) | - upperBnk << (swap ? 1 : 0) | - lowerBnk; - - // The combined rank/bank will need to be split to insert the column and - // row bits. - uint64_t shift = numBnk + i_hash; - if ( 0 != i_numSrnk ) shift += i_numSrnk; // Special case: any slave ranks - if ( 3 == i_numMrnk ) shift += i_numMrnk; // Special case: 8 master ranks - - uint64_t mask = (0xffffffffffffffffull >> shift) << shift; - - o_upperRnkBnk = (rnkBnk & mask) >> shift; - o_lowerRnkBnk = rnkBnk & ~mask; - - o_numUpperRnkBnk = numRnkBnk - shift; - o_numLowerRnkBnk = shift; -} - -/** @brief Takes the combined rank/bank and adds the row and column. This will - * give us bits 0:32 of the Centaur address as described in sections - * 5.6 and 5.7 of Centaur chip spec. - * @param i_upperRnkBnk Upper rank/bank bits (right justified). - * @param i_numUpperRnkBnk Number of configured upper rank/bank bits. - * @param i_lowerRnkBnk Lower rank/bank bits (right justified). - * @param i_numLowerRnkBnk Number of configured lower rank/bank bits. - * @param i_row Row (R18-R0) - * @param i_numRow Number of configured row bits. - * @param i_col Column (C13,C11,C9-C3) - * @param i_numCol Number of configured column bits. - * @param i_ddrVer DDR version (DDR3 or DDR4). - * @param i_mbaIlMode MBA interleave mode. (from MBAXCR[12]) - * @return Bits 0-34 of the Centaur address (right justified). - */ -uint64_t combineComponents( uint64_t i_upperRnkBnk, uint64_t i_numUpperRnkBnk, - uint64_t i_lowerRnkBnk, uint64_t i_numLowerRnkBnk, - uint64_t i_row, uint64_t i_numRow, - uint64_t i_col, uint64_t i_numCol, - uint64_t i_ddrVer, uint64_t i_mbaIlMode ) -{ - // Get the row components. - uint64_t r17 = 0; // DDR4 only - uint64_t upperRow = 0, numUpperRow = 0; - uint64_t lowerRow = 0, numLowerRow = 0; - if ( DDR3 == i_ddrVer ) - { - // upper:r16-r15 lower:r14-r0 - upperRow = (i_row & 0x18000) >> 15; numUpperRow = i_numRow - 15; - lowerRow = i_row & 0x07fff; numLowerRow = 15; - } - else // DDR4 - { - // upper:r16-r14 lower:r13-r0 - r17 = (i_row & 0x20000) >> 17; - upperRow = (i_row & 0x1c000) >> 14; numUpperRow = i_numRow - 14; - lowerRow = i_row & 0x03fff; numLowerRow = 14; - - if ( 18 == i_numRow ) numUpperRow -= 1; // r17 is not in numUpperRow - } - - // Get the column components. - uint64_t upperCol = i_col & 0x1fe; - uint64_t c3 = i_col & 0x001; - - uint64_t numUpperCol = i_numCol - 1; - uint64_t numC3 = 1; - - // Start building the address. - uint64_t addr = r17; - addr <<= i_numUpperRnkBnk; addr |= i_upperRnkBnk; - addr <<= numUpperRow; addr |= upperRow; - addr <<= numUpperCol; addr |= upperCol; - - if ( HASH_MODE_128B == i_mbaIlMode ) - { - addr <<= numC3; addr |= c3; - addr <<= i_numLowerRnkBnk; addr |= i_lowerRnkBnk; - - } - else // HASH_MODE_256B - { - addr <<= i_numLowerRnkBnk; addr |= i_lowerRnkBnk; - addr <<= numC3; addr |= c3; - } - - // Insert the fixed row bits. - addr = (addr & 0xfffffffffffffc00ull) << numLowerRow | - lowerRow << 10 | - (addr & 0x00000000000003ffull); - - return addr; -} - -/** @brief Translates a physical address (rank, bank, row, col) to a 40 bit - * Centaur address. The algorithm is derived from Sections 5.4, 5.6, - * and 5.7 of Centaur chip spec. - * @param i_ds DIMM select (D). - * @param i_mrnk Master rank (M0-M2). - * @param i_srnk Slave rank (S0-S2). - * @param i_numMrnk Number of configured master rank bits. - * @param i_numSrnk Number of configured slave rank bits. - * @param i_row Row (R18-R0) - * @param i_numRow Number of configured row bits. - * @param i_col Column (C13,C11,C9-C3) - * @param i_numCol Number of configured column bits. - * @param i_bnk Bank (DDR3: B2-B0, DDR4: BG1-BG0,B1-B0). - * @param i_mba MBA position (0 or 1) - * @param i_ddrVer DDR version (DDR3 or DDR4). - * @param i_cenIlMode Centaur interleave mode. (from MBSXCR[0:4]) - * @param i_mbaIlMode MBA interleave mode. (from MBAXCR[12]) - * @param i_hash Rank hash. (from MBAXCR[10:11]) - * @param i_cfg Rank config. (from MBAXCR[8]) - * @return The returned 40-bit Cenaur address. - */ -uint64_t transPhysToCenAddr( uint64_t i_ds, uint64_t i_mrnk, uint64_t i_srnk, - uint64_t i_numMrnk, uint64_t i_numSrnk, - uint64_t i_row, uint64_t i_numRow, - uint64_t i_col, uint64_t i_numCol, - uint64_t i_bnk, uint64_t i_mba, - uint64_t i_ddrVer, - uint64_t i_cenIlMode, uint64_t i_mbaIlMode, - uint64_t i_hash, uint64_t i_cfg ) -{ - // Get the combine rank/bank. - uint64_t upperRnkBnk, numUpperRnkBnk; - uint64_t lowerRnkBnk, numLowerRnkBnk; - getRankBank( i_ds, i_mrnk, i_srnk, - i_cfg, i_numMrnk, i_numSrnk, - i_bnk, i_ddrVer, i_hash, - upperRnkBnk, numUpperRnkBnk, - lowerRnkBnk, numLowerRnkBnk ); - - // Get bits 0:32 as described in sections 5.6 and 5.7 of the Centaur spec. - uint64_t addr = combineComponents( upperRnkBnk, numUpperRnkBnk, - lowerRnkBnk, numLowerRnkBnk, - i_row, i_numRow, i_col, i_numCol, - i_ddrVer, i_mbaIlMode ); - - // Adjust for Centaur interleave mode as described in sections 5.4.1 of the - // Centaur spec. - if ( 0 != i_cenIlMode ) - { - // MBSXCR[0] just indicates there is interleaving so that can be - // ignored and we'll just use MBSXCR[1:4]. - i_cenIlMode &= 0xf; - - // Now, a value of 0 indicates bit 23 is interleaved and a value of 9 - // indicates bit 32 is interleaved. So we should be able to invert it to - // give us the shift value. - uint64_t shift = 9 - i_cenIlMode; - uint64_t mask = (0xffffffffffffffffull >> shift) << shift; - - // Insert the MBA bit. - addr = (addr & mask) << 1 | i_mba << shift | (addr & ~mask); - } - - // Bits 33:39 are zero. - addr <<= 7; - - return addr; -} - -// Given the number of configured ranks, return the number of configured rank -// bits (i.e. 1 rank=0 bits, 2 ranks=1 bit, 4 ranks=2 bits, 8 ranks=3 bits). -// This could be achieved with log2() from math.h, but we don't want to mess -// with floating point numbers (FSP uses C++ standard). -uint64_t ranks2bits( uint64_t i_numRnks ) -{ - switch ( i_numRnks ) - { - case 1: return 0; - case 2: return 1; - case 4: return 2; - case 8: return 3; - } - - return 0; -} - -// The code in this function is based on section 5.4.1 and 5.6 of Centaur -// chip spec. -int32_t getCenPhyAddr( ExtensibleChip * i_mbaChip, ExtensibleChip * i_mbChip, - CenAddr i_addr, uint64_t & o_addr ) -{ - #define PRDF_FUNC "[DEALLOC::getCenPhyAddr] " - - int32_t o_rc = SUCCESS; - - o_addr = 0; - - TargetHandle_t mba = i_mbaChip->GetChipHandle(); - uint64_t mbaPos = getTargetPosition( mba ); - - uint64_t ds = i_addr.getRank().getDimmSlct(); // D - uint64_t mrnk = i_addr.getRank().getRankSlct(); // M0-M2 - uint64_t srnk = i_addr.getRank().getSlave(); // S0-S2 - - uint64_t row = i_addr.getRow(); // R18-R0 - uint64_t col = i_addr.getCol(); // C13,C11,C9-C3 - uint64_t bnk = i_addr.getBank(); // DDR3: B2-B0, DDR4: BG1-BG0,B1-B0 - - do - { - // Get the number of configured address bits for the master and slave - // ranks. - uint64_t num_mrnk = getMasterRanksPerDimm( mba, ds ); - if ( 0 == num_mrnk ) - { - PRDF_ERR( PRDF_FUNC "getMasterRanksPerDimm() failed. HUID:0X%08X", - i_mbChip->GetId() ); - break; - } - - uint64_t num_srnk = getRanksPerDimm( mba, ds ) / num_mrnk; - if ( 0 == num_srnk ) - { - PRDF_ERR( PRDF_FUNC "getRanksPerDimm() failed. HUID:0X%08X", - i_mbChip->GetId() ); - break; - } - - uint64_t mrnkBits = ranks2bits( num_mrnk ); - uint64_t srnkBits = ranks2bits( num_srnk ); - - // Get the number of configured address bits for the row and column. - uint8_t rowBits, colBits; - o_rc = getDimmRowCol( mba, rowBits, colBits ); - if ( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "getDimmConfig() failed. HUID:0x%08X", - i_mbaChip->GetId()); - break; - } - - // The attribute used in getDimmRowCol() returns a value for colBits - // which includes c2-c0. Those bits are tied to zero and are not - // included in col. Therefore, we need to subtract 3 to get the real - // value. - colBits = colBits - 3; - - // Get the DDR verion of the DIMM (DDR3, DDR4, etc...) - uint8_t ddrVer = getDramGen<TYPE_MBA>( mba ); - - // Get the Centaur interleave mode (MBSXCR[0:4]). - SCAN_COMM_REGISTER_CLASS * mbsxcr = i_mbChip->getRegister("MBSXCR"); - o_rc = mbsxcr->Read(); - if ( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "Read() failed on MBSXCR. HUID:0x%08X", - i_mbChip->GetId() ) ; - break; - } - - uint64_t cenIlMode = mbsxcr->GetBitFieldJustified( 0, 5 ); - - // Get the rank config (MBAXCR[8]), rank hash (MBAXCR[10:11]), and - // MBA interleave mode (MBAXCR[12]). - const char * reg_str = ( 0 == mbaPos ) ? "MBA0_MBAXCR" : "MBA1_MBAXCR"; - SCAN_COMM_REGISTER_CLASS * mbaxcr = i_mbChip->getRegister( reg_str ); - o_rc = mbaxcr->Read(); - if ( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "Read() failed on %s. HUID:0X%08X", - reg_str, i_mbChip->GetId() ); - break; - } - - uint8_t cfg = mbaxcr->GetBitFieldJustified( 8, 1 ); - uint8_t hash = mbaxcr->GetBitFieldJustified( 10, 2 ); - uint8_t mbaIlMode = mbaxcr->GetBitFieldJustified( 12, 1 ); - - // Form the address from info gathered above - o_addr = transPhysToCenAddr( ds, mrnk, srnk, - mrnkBits, srnkBits, - row, rowBits, col, colBits, - bnk, mbaPos, - ddrVer, - cenIlMode, mbaIlMode, - hash, cfg ); - - } while(0); - - return o_rc; - - #undef PRDF_FUNC -} - -//------------------------------------------------------------------------------ - -// The code in this function is based on section 2.1.3 of MC workbook. - -int32_t getSystemAddr( ExtensibleChip * i_mbaChip, CenAddr i_addr, - uint64_t & o_addr ) -{ - #define PRDF_FUNC "[DEALLOC::getSystemAddr] " - - int32_t o_rc = SUCCESS; - - o_addr = 0; - - do - { - // Get the MEMBUF chip. - CenMbaDataBundle * mbadb = getMbaDataBundle( i_mbaChip ); - ExtensibleChip * mbChip = mbadb->getMembChip(); - if ( NULL == mbChip ) - { - PRDF_ERR( PRDF_FUNC "getMembChip() returned NULL. MBA:0x%08X", - i_mbaChip->GetId() ); - o_rc = FAIL; break; - } - - // Get the MCS chip. - CenMembufDataBundle * mbdb = getMembufDataBundle( mbChip ); - ExtensibleChip * mcsChip = mbdb->getMcsChip(); - if ( NULL == mbChip ) - { - PRDF_ERR( PRDF_FUNC "getMcsChip() returned NULL. MEMBUF:0x%08X", - mbChip->GetId() ); - o_rc = FAIL; break; - } - - // Get the physical Centaur address. - uint64_t cenAddr = 0; - o_rc = getCenPhyAddr( i_mbaChip, mbChip, i_addr, cenAddr ); - if ( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "getCenPhyAddr() failed. MBA:0x%08X " - "MEMBUF:0x%08X", i_mbaChip->GetId(), mbChip->GetId()); - break; - } - - // Get the MCS group information. - SCAN_COMM_REGISTER_CLASS * mcgfp = mcsChip->getRegister( "MCFGP" ); - o_rc = mcgfp->Read(); - if ( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "Read() failed on MCFGP. MCS:0x%08X", - mcsChip->GetId() ) ; - break; - } - - // Get the MCS per group - // 000 - 1, 001 - 2, 010 - 4, 100 - 8 - uint8_t mcsPerGrp = mcgfp->GetBitFieldJustified( 1,3 ); - uint8_t grpShift = 0; - - // Get the number of bits required to accomondate mcsPos - while ( 0 != ( mcsPerGrp >> grpShift ) ) { grpShift++; } - - // Get the MCS position within group. Though it is 5 bit field, - // two bits are not used. - uint64_t grpSlct = mcgfp->GetBitFieldJustified( 4, 5 ) << 7; - // Get the base address for MCS - uint64_t baseAddr = mcgfp->GetBitFieldJustified( 26, 18 ) << 32; - - // Split the Centaur address to make room for the group select. - uint64_t cenUpper33 = (cenAddr & 0xFFFFFFFF80ull) << grpShift; - uint64_t cenLower7 = cenAddr & 0x000000007full; - - // Put the whole address together - o_addr = baseAddr | cenUpper33 | grpSlct | cenLower7; - - } while( 0 ); - - return o_rc; - - #undef PRDF_FUNC -} - -//------------------------------------------------------------------------------ - -int32_t rankGard( ExtensibleChip * i_mbaChip, CenRank i_rank ) -{ - #define PRDF_FUNC "[DEALLOC::rankGard] " - - int32_t o_rc = SUCCESS; - do - { - CenAddr startAddr, endAddr; - TargetHandle_t mba = i_mbaChip->GetChipHandle(); - o_rc = getMemAddrRange( mba, i_rank, startAddr, endAddr ); - if ( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "getMemAddrRange() Failed. HUID:0x%08X", - i_mbaChip->GetId() ); - break; - } - - // Get the system addresses - uint64_t ssAddr = 0; - uint64_t seAddr = 0; - o_rc = getSystemAddr( i_mbaChip, startAddr, ssAddr); - o_rc |= getSystemAddr( i_mbaChip, endAddr, seAddr ); - if ( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "getSystemAddr() failed. HUID:0x%08X", - i_mbaChip->GetId() ); - break; - } - // Send the address range to HV - sendDynMemDeallocRequest( ssAddr, seAddr ); - PRDF_TRAC( PRDF_FUNC "Rank gard for Start Addr: 0x%016llx " - "End Addr: 0x%016llX", ssAddr, seAddr ); - - } while( 0 ); - - return o_rc; - #undef PRDF_FUNC -} - -//------------------------------------------------------------------------------ - -bool isEnabled() -{ - return ( isHyprRunning() && (isHyprConfigPhyp() || isHyprConfigOpal()) && - !isMfgAvpEnabled() && !isMfgHdatAvpEnabled() ); -} - -//------------------------------------------------------------------------------ - -int32_t pageGard( ExtensibleChip * i_mbaChip, CenAddr i_addr ) -{ - #define PRDF_FUNC "[DEALLOC::pageGard] " - - uint64_t sysAddr = 0; - int32_t o_rc = SUCCESS; - do - { - if ( !isEnabled() ) break; // nothing to do - - o_rc = getSystemAddr( i_mbaChip, i_addr, sysAddr); - if( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "getSystemAddr() failed. HUID:0x%08X", - i_mbaChip->GetId() ); - break; - } - - sendPageGardRequest( sysAddr ); - PRDF_TRAC( PRDF_FUNC "Page gard for address: 0x%016llX", sysAddr ); - - } while( 0 ); - - return o_rc; - #undef PRDF_FUNC -} - -//------------------------------------------------------------------------------ - -int32_t lmbGard( ExtensibleChip * i_mbaChip, CenAddr i_addr, bool i_isFetch ) -{ - #define PRDF_FUNC "[DEALLOC::lmbGard] " - - uint64_t sysAddr = 0; - int32_t o_rc = SUCCESS; - do - { - if ( !isEnabled() ) break; // nothing to do - - if( isHyprConfigOpal() ) - { - o_rc = rankGard( i_mbaChip, i_addr.getRank() ); - if( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "rankGard() failed. HUID:0x%08X", - i_mbaChip->GetId() ); - break; - } - } - else - { - o_rc = getSystemAddr( i_mbaChip, i_addr, sysAddr); - if( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "getSystemAddr() failed. HUID:0x%08X", - i_mbaChip->GetId() ); - break; - } - - sendLmbGardRequest( sysAddr, i_isFetch ); - PRDF_TRAC( PRDF_FUNC "LMB gard for address: 0x%016llX", sysAddr ); - } - - } while( 0 ); - - return o_rc; - #undef PRDF_FUNC -} - -//------------------------------------------------------------------------------ - -int32_t mbaGard( ExtensibleChip * i_mbaChip ) -{ - #define PRDF_FUNC "[DEALLOC::mbaGard] " - int32_t o_rc = SUCCESS; - - do - { - if ( !isEnabled() ) break; // nothing to do - - CenAddr startAddr, endAddr; - TargetHandle_t mba = i_mbaChip->GetChipHandle(); - o_rc = getMemAddrRange( mba, startAddr, endAddr ); - if ( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "getMemAddrRange() Failed. HUID:0x%08X", - i_mbaChip->GetId() ); - break; - } - - // Get the system addresses - uint64_t ssAddr = 0; - uint64_t seAddr = 0; - o_rc = getSystemAddr( i_mbaChip, startAddr, ssAddr); - o_rc |= getSystemAddr( i_mbaChip, endAddr, seAddr ); - if ( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "getSystemAddr() failed. HUID:0x%08X", - i_mbaChip->GetId() ); - break; - } - - // Send the address range to PHYP - sendDynMemDeallocRequest( ssAddr, seAddr ); - PRDF_TRAC( PRDF_FUNC "MBA gard for Start Addr: 0x%016llx " - "End Addr: 0x%016llX", ssAddr, seAddr ); - - } while (0); - - return o_rc; - #undef PRDF_FUNC -} - -//------------------------------------------------------------------------------ - -int32_t dimmSlctGard( TargetHandle_t i_dimm ) -{ - #define PRDF_FUNC "[DEALLOC::dimmSlctGard] " - int32_t o_rc = SUCCESS; - - do - { - if ( !isEnabled() ) break; // nothing to do - - TargetHandle_t mba = getConnectedParent( i_dimm, TYPE_MBA ); - - ExtensibleChip * mbaChip = (ExtensibleChip *)systemPtr->GetChip( mba ); - if ( NULL == mbaChip ) - { - PRDF_ERR( PRDF_FUNC "No MBA chip behind DIMM" ); - o_rc = FAIL; break; - } - // Find the largest address range - uint64_t smallestAddr = 0xffffffffffffffffll; - uint64_t largestAddr = 0; - CenAddr startAddr, endAddr; - std::vector<CenRank> masterRanks; - uint8_t dimmSlct = 0; - - o_rc = getMbaDimm( i_dimm, dimmSlct ); - if ( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "getMbaDimm() failed" ); - break; - } - - o_rc = getMasterRanks( mba, masterRanks, dimmSlct ); - if ( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "getMasterRanks() failed" ); - break; - } - - // Iterate all ranks to get start and end address. - for ( std::vector<CenRank>::iterator it = masterRanks.begin(); - it != masterRanks.end(); it++ ) - { - o_rc = getMemAddrRange( mba, *it, startAddr, endAddr ); - if ( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "getMemAddrRange() Failed. HUID:0x%08X", - mbaChip->GetId() ); - break; - } - - // Get the system addresses - uint64_t ssAddr = 0; - uint64_t seAddr = 0; - o_rc = getSystemAddr( mbaChip, startAddr, ssAddr); - o_rc |= getSystemAddr( mbaChip, endAddr, seAddr ); - if ( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "getSystemAddr() failed. HUID:0x%08X", - mbaChip->GetId() ); - break; - } - if ( ssAddr < smallestAddr ) smallestAddr = ssAddr; - if ( seAddr > largestAddr ) largestAddr = seAddr; - } - if( SUCCESS != o_rc ) break; - - // Send the address range to PHYP - sendDynMemDeallocRequest( smallestAddr, largestAddr ); - PRDF_TRAC( PRDF_FUNC "DIMM Slct gard for Start Addr: 0x%016llx " - "End Addr: 0x%016llX", smallestAddr, largestAddr ); - - } while (0); - - if( FAIL == o_rc ) - { - PRDF_ERR( PRDF_FUNC "failed. DIMM:0x%08X", getHuid( i_dimm ) ); - } - - return o_rc; - #undef PRDF_FUNC -} - -//------------------------------------------------------------------------------ - -bool isDimmPair( TargetHandle_t i_dimm1, TargetHandle_t i_dimm2 ) -{ - #define PRDF_FUNC "[DEALLOC::isDimmPair] " - bool isDimmPair = false; - do - { - uint8_t dimm1Slct = 0; - uint8_t dimm2Slct = 0; - - int32_t rc = getMbaDimm( i_dimm1, dimm1Slct ); - rc |= getMbaDimm( i_dimm2, dimm2Slct ); - - if( SUCCESS != rc ) - { - PRDF_ERR( PRDF_FUNC " getMbaDimm() failed" ); - break; - } - isDimmPair = ( ( dimm1Slct == dimm2Slct ) && - ( getConnectedParent( i_dimm1, TYPE_MBA ) == - getConnectedParent( i_dimm2, TYPE_MBA ))); - } while(0); - return isDimmPair; - #undef PRDF_FUNC -} - -//------------------------------------------------------------------------------ - -// This function is used for sorting dimms in a list. -bool compareDimms( TargetHandle_t i_dimm1, TargetHandle_t i_dimm2 ) -{ - #define PRDF_FUNC "[DEALLOC::compareDimms] " - bool isSmall = false; - do - { - uint8_t dimm1Slct = 0; - uint8_t dimm2Slct = 0; - - int32_t rc = getMbaDimm( i_dimm1, dimm1Slct ); - rc |= getMbaDimm( i_dimm2, dimm2Slct ); - - if( SUCCESS != rc ) - { - PRDF_ERR( PRDF_FUNC " getMbaDimm() failed" ); - break; - } - TargetHandle_t mba1 = getConnectedParent( i_dimm1, TYPE_MBA ); - TargetHandle_t mba2 = getConnectedParent( i_dimm2, TYPE_MBA ); - - isSmall = ( ( mba1 < mba2 ) || - ( ( mba1 == mba2) && ( dimm1Slct < dimm2Slct ))); - - } while(0); - - return isSmall; - #undef PRDF_FUNC -} - -//------------------------------------------------------------------------------ - -int32_t dimmListGard( TargetHandleList & i_dimmList ) -{ - #define PRDF_FUNC "[DEALLOC::dimmListGard] " - int32_t o_rc = SUCCESS; - - // Find unique dimm slct. - std::sort( i_dimmList.begin(), i_dimmList.end(), compareDimms ); - TargetHandleList::iterator uniqueDimmEndIt = - std::unique( i_dimmList.begin(), i_dimmList.end(), isDimmPair ); - - for( TargetHandleList::iterator it = i_dimmList.begin(); - it != uniqueDimmEndIt; it++ ) - { - int32_t l_rc = dimmSlctGard( *it ); - if( SUCCESS != l_rc ) - { - PRDF_ERR(PRDF_FUNC "Failed for DIMM 0x:%08X", getHuid( *it ) ); - o_rc |= l_rc; - } - } - return o_rc; - #undef PRDF_FUNC -} -} //namespace DEALLOC -} // namespace PRDF diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaDynMemDealloc_rt.H b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaDynMemDealloc_rt.H deleted file mode 100755 index 5622ff188..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaDynMemDealloc_rt.H +++ /dev/null @@ -1,93 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/diag/prdf/common/plat/pegasus/prdfCenMbaDynMemDealloc_rt.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -#ifndef __prdfCenMbaDynMemDealloc_rt_H -#define __prdfCenMbaDynMemDealloc_rt_H - -/** @file prdfCenMbaDynMemDealloc_rt.H - * @brief Support functions for Dynamic Memory Deallocation - */ - -namespace PRDF -{ - -class ExtensibleChip; -class CenAddr; - -namespace DEALLOC -{ - -/** - * @return True, if Dynamic Memory Deallocation is enabled. False, otherwise. - */ -bool isEnabled(); - -/** - * @brief Sends a page gard message to PHYP. - * @param i_mbaChip MBA chip - * @param i_addr The address to page gard. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ -int32_t pageGard( ExtensibleChip * i_mbaChip, CenAddr i_addr ); - -/** - * @brief Sends a LMB gard message to PHYP. - * @param i_mbaChip MBA chip - * @param i_addr The address to lmb gard. - * @param i_isFetch TRUE if we are calling this because of FETCH UE, - * FALSE otherwise. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ -int32_t lmbGard( ExtensibleChip * i_mbaChip, CenAddr i_addr, - bool i_isFetch = true); - -/** - * @brief Sends a message to PHYP to gard all memory behind MBA. - * @param i_mbaChip MBA chip - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ -int32_t mbaGard( ExtensibleChip * i_mbaChip ); - -/** - * @brief Sends a message to PHYP to gard all memory behind dimm List. - * @param i_dimmList DIMM list - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ -int32_t dimmListGard( TARGETING::TargetHandleList & i_dimmList ); - -/** - * @brief Sends a message to PHYP to gard all memory behind dimm slct. - * @param i_dimm Memory DIMM. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ -int32_t dimmSlctGard( TARGETING::TargetHandle_t i_dimm ); - -} //namespace DEALLOC -} // namespace PRDF -//------------------------------------------------------------------------------ - - -#endif /* __prdfCenMbaDynMemDealloc_rt_H */ - diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfExDomain.H b/src/usr/diag/prdf/common/plat/pegasus/prdfExDomain.H deleted file mode 100644 index 44d445ab9..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfExDomain.H +++ /dev/null @@ -1,62 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/diag/prdf/common/plat/pegasus/prdfExDomain.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -#ifndef __PRDFEXDOMAIN_H -#define __PRDFEXDOMAIN_H - -#include <prdfRuleChipDomain.H> - -namespace PRDF -{ - -class ExDomain : public RuleChipDomain -{ - public: - - /** - * @brief Constructor - * @param i_did The domain ID - * @param i_size The projected size of the domain - */ - ExDomain( DOMAIN_ID i_did, uint32_t i_size = EX_DOMAIN_SIZE ) : - RuleChipDomain( i_did, i_size ) - {} - - /** - * @brief Query for an attention of a specific type in this domain - * @param i_attnType [MACHINE_CHECK | RECOVERABLE | SPECIAL] - * @return false - * @note This function will always return false. That way PRD will look - * for the attention via the processor chip. - */ - virtual bool Query( ATTENTION_TYPE i_attnType ) - { return false; } - -}; - -} // end namespace PRDF - -#endif /* __PRDFEXDOMAIN_H */ - diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfLaneRepair.C b/src/usr/diag/prdf/common/plat/pegasus/prdfLaneRepair.C deleted file mode 100644 index 8be057233..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfLaneRepair.C +++ /dev/null @@ -1,325 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/diag/prdf/common/plat/pegasus/prdfLaneRepair.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ -/* [+] Google Inc. */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/** @file prdfLaneRepair.C */ - -#include <prdfLaneRepair.H> - -// Framework includes -#include <prdfPlatServices.H> -#include <iipconst.h> -#include <prdfGlobal.H> -#include <iipSystem.h> -#include <iipServiceDataCollector.h> -#include <prdfExtensibleChip.H> -#include <UtilHash.H> - -// Pegasus includes -#include <prdfCalloutUtil.H> -#include <prdfCenMembufDataBundle.H> -#include <prdfP8McsDataBundle.H> -#include <prdfP8ProcMbCommonExtraSig.H> - -using namespace TARGETING; - -namespace PRDF -{ -using namespace PlatServices; - -namespace LaneRepair -{ - -int32_t handleLaneRepairEvent( ExtensibleChip * i_chip, - TYPE i_busType, - uint32_t i_busPos, - STEP_CODE_DATA_STRUCT & i_sc, - bool i_spareDeployed ) -{ - #define PRDF_FUNC "[LaneRepair::handleLaneRepairEvent] " - - int32_t l_rc = SUCCESS; - TargetHandle_t rxBusTgt = NULL; - TargetHandle_t txBusTgt = NULL; - bool thrExceeded = true; - std::vector<uint8_t> rx_lanes; - std::vector<uint8_t> rx_vpdLanes; - std::vector<uint8_t> tx_vpdLanes; - BitStringBuffer l_vpdLaneMap0to63(64); - BitStringBuffer l_vpdLaneMap64to127(64); - BitStringBuffer l_newLaneMap0to63(64); - BitStringBuffer l_newLaneMap64to127(64); - - do - { - #ifdef __HOSTBOOT_MODULE - if ( CHECK_STOP == i_sc.service_data->getPrimaryAttnType() ) - { - // This would only happen on OpenPOWER machines when we are doing - // the post IPL analysis. In this case, we do not have the FFDC to - // query the IO registers so simply set service call and skip - // everything else. - i_sc.service_data->setServiceCall(); - return SUCCESS; - } - #endif - - // Get the RX and TX targets. - l_rc = CalloutUtil::getBusEndpoints( i_chip, rxBusTgt, txBusTgt, - i_busType, i_busPos ); - if ( SUCCESS != l_rc ) - { - PRDF_ERR( PRDF_FUNC "getBusEndpoints() failed" ); - break; - } - - // Call io_read_erepair - l_rc = readErepair(rxBusTgt, rx_lanes); - if (SUCCESS != l_rc) - { - PRDF_ERR( PRDF_FUNC "readErepair() failed: rxBusTgt=0x%08x", - getHuid(rxBusTgt) ); - break; - } - - // Add newly failed lanes to capture data - for (std::vector<uint8_t>::iterator lane = rx_lanes.begin(); - lane != rx_lanes.end(); ++lane) - { - PRDF_INF( PRDF_FUNC "New failed lane on RX HUID 0x%08x: %d", - getHuid(rxBusTgt), *lane); - if (*lane < 64) - l_newLaneMap0to63.setBit(*lane); - else if (*lane < 127) - l_newLaneMap64to127.setBit(*lane - 64); - else - { - PRDF_ERR( PRDF_FUNC "Invalid lane number %d: rxBusTgt=0x%08x", - *lane, getHuid(rxBusTgt) ); - l_rc = FAIL; break; - } - } - if ( SUCCESS != l_rc ) break; - - // Add failed lane capture data to errorlog - i_sc.service_data->GetCaptureData().Add(i_chip->GetChipHandle(), - ( Util::hashString("ALL_FAILED_LANES_0TO63") ^ - i_chip->getSignatureOffset() ), - l_newLaneMap0to63); - i_sc.service_data->GetCaptureData().Add(i_chip->GetChipHandle(), - ( Util::hashString("ALL_FAILED_LANES_64TO127") ^ - i_chip->getSignatureOffset() ), - l_newLaneMap64to127); - - // Don't read/write VPD in mfg mode if erepair is disabled - if ( !(((i_busType == TYPE_ABUS || i_busType == TYPE_XBUS) - && isFabeRepairDisabled()) - || ((i_busType == TYPE_MCS || i_busType == TYPE_MEMBUF) - && isMemeRepairDisabled())) ) - { - // Read Failed Lanes from VPD - l_rc = getVpdFailedLanes(rxBusTgt, rx_vpdLanes, tx_vpdLanes); - if (SUCCESS != l_rc) - { - PRDF_ERR( PRDF_FUNC "getVpdFailedLanes() failed: " - "rxBusTgt=0x%08x", getHuid(rxBusTgt) ); - break; - } - - // Add VPD lanes to capture data - for (std::vector<uint8_t>::iterator lane = rx_vpdLanes.begin(); - lane != rx_vpdLanes.end(); ++lane) - { - if (*lane < 64) - l_vpdLaneMap0to63.setBit(*lane); - else if (*lane < 127) - l_vpdLaneMap64to127.setBit(*lane - 64); - else - { - PRDF_ERR( PRDF_FUNC "Invalid VPD lane number %d: " - "rxBusTgt=0x%08x", *lane, getHuid(rxBusTgt) ); - l_rc = FAIL; break; - } - } - if ( SUCCESS != l_rc ) break; - - // Add failed lane capture data to errorlog - i_sc.service_data->GetCaptureData().Add(i_chip->GetChipHandle(), - ( Util::hashString("VPD_FAILED_LANES_0TO63") ^ - i_chip->getSignatureOffset() ), - l_vpdLaneMap0to63); - i_sc.service_data->GetCaptureData().Add(i_chip->GetChipHandle(), - ( Util::hashString("VPD_FAILED_LANES_64TO127") ^ - i_chip->getSignatureOffset() ), - l_vpdLaneMap64to127); - - if (i_spareDeployed) - { - // Call Erepair to update VPD - l_rc = setVpdFailedLanes(rxBusTgt, txBusTgt, - rx_lanes, thrExceeded); - if (SUCCESS != l_rc) - { - PRDF_ERR( PRDF_FUNC "setVpdFailedLanes() failed: " - "rxBusTgt=0x%08x txBusTgt=0x%08x", - getHuid(rxBusTgt), getHuid(txBusTgt) ); - break; - } - if( thrExceeded ) - { - i_sc.service_data->SetErrorSig( - PRDFSIG_ERepair_FWThrExceeded ); - } - } - } - - if (i_spareDeployed && !thrExceeded) - { - // Update lists of lanes from VPD - rx_vpdLanes.clear(); tx_vpdLanes.clear(); - l_rc = getVpdFailedLanes(rxBusTgt, rx_vpdLanes, tx_vpdLanes); - if (SUCCESS != l_rc) - { - PRDF_ERR( PRDF_FUNC "getVpdFailedLanes() before power down " - "failed: rxBusTgt=0x%08x", getHuid(rxBusTgt) ); - break; - } - - // Power down all lanes that have been saved in VPD - l_rc = powerDownLanes(rxBusTgt, rx_vpdLanes, tx_vpdLanes); - if (SUCCESS != l_rc) - { - PRDF_ERR( PRDF_FUNC "powerDownLanes() failed: rxBusTgt=0x%08x", - getHuid(rxBusTgt) ); - break; - } - } - else - { - // Make predictive - i_sc.service_data->setServiceCall(); - } - } while (0); - - // Clear FIRs - if (rxBusTgt) - { - l_rc |= erepairFirIsolation(rxBusTgt); - l_rc |= clearIOFirs(rxBusTgt); - } - - if ( i_spareDeployed ) - { - l_rc |= cleanupSecondaryFirBits( i_chip, i_busType, i_busPos ); - } - - // This return code gets returned by the plugin code back to the rule code. - // So, we do not want to give a return code that the rule code does not - // understand. So far, there is no need return a special code, so always - // return SUCCESS. - if ( SUCCESS != l_rc ) - { - PRDF_ERR( PRDF_FUNC "i_chip: 0x%08x i_busType:%d i_busPos:%d", - i_chip->GetId(), i_busType, i_busPos ); - - i_sc.service_data->SetErrorSig( PRDFSIG_ERepair_ERROR ); - CalloutUtil::defaultError( i_sc ); - } - - return SUCCESS; - - #undef PRDF_FUNC -} - -//----------------------------------------------------------------------------- - -int32_t cleanupSecondaryFirBits( ExtensibleChip * i_chip, - TYPE i_busType, - uint32_t i_busPos ) -{ - int32_t l_rc = SUCCESS; - TargetHandle_t mcsTgt = NULL; - TargetHandle_t mbTgt = NULL; - ExtensibleChip * mcsChip = NULL; - ExtensibleChip * mbChip = NULL; - - //In case of spare deployed attention for DMI bus, we need to clear - // secondary MBIFIR[10] and MCIFIR[10] bits. - do - { - if ( i_busType == TYPE_MCS ) - { - mcsTgt = getConnectedChild( i_chip->GetChipHandle(), - TYPE_MCS, - i_busPos); - if (!mcsTgt) break; - mcsChip = ( ExtensibleChip * )systemPtr->GetChip( mcsTgt ); - if (!mcsChip) break; - mbChip = getMcsDataBundle( mcsChip )->getMembChip(); - if (!mbChip) break; - mbTgt = mbChip->GetChipHandle(); - if (!mbTgt) break; - } - else if ( i_busType == TYPE_MEMBUF ) - { - mbTgt = i_chip->GetChipHandle(); - if (!mbTgt) break; - mcsChip = getMembufDataBundle( i_chip )->getMcsChip(); - if (!mcsChip) break; - mcsTgt = mcsChip->GetChipHandle(); - if (!mcsTgt) break; - mbChip = i_chip; - } - else - { - // We only need to clean secondary FIR bits for DMI bus - l_rc = SUCCESS; - break; - } - - SCAN_COMM_REGISTER_CLASS * mciAnd = mcsChip->getRegister("MCIFIR_AND"); - SCAN_COMM_REGISTER_CLASS * mbiAnd = mbChip->getRegister( "MBIFIR_AND"); - - mciAnd->setAllBits(); mciAnd->ClearBit(10); - mbiAnd->setAllBits(); mbiAnd->ClearBit(10); - - l_rc = mciAnd->Write(); - l_rc |= mbiAnd->Write(); - - if ( SUCCESS != l_rc ) - { - PRDF_ERR( "[cleanupSecondaryFirBits] Write() failed on " - "MCIFIR/MBIFIR: MCS=0x%08x MEMB=0x%08x", - mcsChip->GetId(), mbChip->GetId() ); - break; - } - - } while (0); - - return l_rc; -} - -} // end namespace LaneRepair -} // end namespace PRDF diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfLaneRepair.H b/src/usr/diag/prdf/common/plat/pegasus/prdfLaneRepair.H deleted file mode 100644 index cdae757ce..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfLaneRepair.H +++ /dev/null @@ -1,79 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/diag/prdf/common/plat/pegasus/prdfLaneRepair.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2018 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -#ifndef _PRDFLANEREPAIR_H -#define _PRDFLANEREPAIR_H - -/** @file prdfLaneRepair.H - * @brief Common Lane Repair code for Lane Spared, Spares Exceeded, and - * Too Many Bus Errors conditions. - */ - -#include<iipconst.h> -#include <targeting/common/target.H> - -namespace PRDF -{ - -class ExtensibleChip; -struct STEP_CODE_DATA_STRUCT; - -namespace LaneRepair -{ - /** - * @brief Handles a Lane Repair Event - * @param i_chip Chip that detected the lane repair event - * @param i_busType Bus connection type (X,A, MEMBUF, or MCS) - * @param i_busPos Bus position - * @param i_sc The step code data struct. - * @param i_spareDeployed True if FIR bit indicates a spare was deployed - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - int32_t handleLaneRepairEvent (ExtensibleChip * i_chip, - TARGETING::TYPE i_busType, - uint32_t i_busPos, - STEP_CODE_DATA_STRUCT & i_sc, - bool i_spareDeployed); - - // Utility functions for secondary FIR bits - - /** - * @brief clean up secondary FIR bits ( MBI/MCIFIR bit 10 ) - * @param i_chip Chip that detected the lane repair event - * @param i_busType Bus connection type (X,A, MEMBUF, or MCS) - * @param i_busPos Bus position - * @note This will only clear FIR bits if spare deploy attention is present - * on DMI bus. It does not check for spare deployed attention type - * Calling function should make ensure that. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - int32_t cleanupSecondaryFirBits( ExtensibleChip * i_chip, - TARGETING::TYPE i_busType, - uint32_t i_busPos ); - -} // end namespace LaneRepair -} // end namespace PRDF - -#endif /* _PRDFLANEREPAIR_H */ diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfP8DataBundle.H b/src/usr/diag/prdf/common/plat/pegasus/prdfP8DataBundle.H deleted file mode 100644 index cd0922cdb..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfP8DataBundle.H +++ /dev/null @@ -1,139 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/diag/prdf/common/plat/pegasus/prdfP8DataBundle.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -#ifndef __prdfP8DataBundle_H -#define __prdfP8DataBundle_H - -/** @file prdfP8DataBundle.H - * @brief Contains the data bundle for a P8 MCS object. - */ - -#include <iipSystem.h> -#include <prdfExtensibleChip.H> -#include <prdfGlobal.H> -#include <prdfPlatServices.H> -#include <prdfThresholdUtils.H> - -namespace PRDF -{ - -/** - * @brief The P8 data bundle. - */ -class P8DataBundle : public DataBundle -{ - public: // functions - - /* - * @brief Proc PLL chiplet types - */ - enum ChipletType - { - ABUS, - EX, - PB, - NV, - }; - - /* - * @brief Proc PLL Error Reg data structure - */ - struct PllErrReg - { - ExtensibleChip * chip; - ChipletType type; - SCAN_COMM_REGISTER_CLASS * errReg; - SCAN_COMM_REGISTER_CLASS * configReg; - PllErrReg() : chip(NULL), errReg(NULL), configReg(NULL) {} - }; - - typedef std::vector<PllErrReg> ProcPllErrRegList; - typedef ProcPllErrRegList::iterator ProcPllErrRegListIter; - - - /** - * @brief Constructor. - * @param i_chip The P8 chip. - */ - explicit P8DataBundle( ExtensibleChip * i_chip ) : - iv_todIgnoreAnalysisThr( TimeBasedThreshold( - 32, ThresholdResolution::ONE_DAY) ) - {} - - /** - * @brief Destructor. - */ - ~P8DataBundle() {} - - /** - * @brief get a list of Proc PLL Error reg data - * @return returns a list of Proc PLL Error reg data - */ - ProcPllErrRegList & getProcPllErrRegList() - { - return iv_procPllErrRegList; - } - - /** - * @return get instance of TimeBasedThreshold meant for TOD error. - * @note This instance is meant to threshold all the TOD errors for an - * FSP based OPAL system. Once threshold is met, these errors - * are masked. - */ - TimeBasedThreshold & getTodErrorIgnoreThr() - { - return iv_todIgnoreAnalysisThr; - } - - private: // functions - - P8DataBundle( const P8DataBundle & ); - const P8DataBundle & operator=( const P8DataBundle & ); - - private: // instance variables - - ProcPllErrRegList iv_procPllErrRegList; - TimeBasedThreshold iv_todIgnoreAnalysisThr; ///< policy for masking TOD Err - - - -}; - -//------------------------------------------------------------------------------ - -/** - * @brief Wrapper function for the P8DataBundle. - * @param i_chip The P8 chip. - * @return This P8's data bundle. - */ -inline P8DataBundle * getDataBundle( ExtensibleChip * i_chip ) -{ - return static_cast<P8DataBundle *>(i_chip->getDataBundle()); -} - -} // end namespace PRDF - -#endif // __prdfP8DataBundle_H - diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfP8ExExtraSig.H b/src/usr/diag/prdf/common/plat/pegasus/prdfP8ExExtraSig.H deleted file mode 100755 index 5c30bb571..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfP8ExExtraSig.H +++ /dev/null @@ -1,57 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/diag/prdf/common/plat/pegasus/prdfP8ExExtraSig.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -#ifndef __prdfP8ExExtraSig_H -#define __prdfP8ExExtraSig_H - -#include <prdrSignatures.H> - -PRDR_ERROR_SIGNATURE( P8EX_L2CE_LD_ISSUED, 0x0fff0000, "L2FIR[0]", - "L2 Cache Read CE, Line Delete Issued"); -PRDR_ERROR_SIGNATURE( P8EX_L2CE_LD_FAILURE, 0x0fff0001, "L2FIR[0]", - "L2 Cache Read CE, Line Delete Failed"); -PRDR_ERROR_SIGNATURE( P8EX_L2_ARRAY_REPAIR_COMPLETE, 0x0fff0002, "L2FIR[0]", - "L2 Array Repair Complete"); -PRDR_ERROR_SIGNATURE( P8EX_L2_ARRAY_REPAIR_FAILURE, 0x0fff0003, "L2FIR[0]", - "L2 Array Repair Failure"); -PRDR_ERROR_SIGNATURE( P8EX_L2_ARRAY_REPAIR_OUT_OF, 0x0fff0004, "L2FIR[0]", - "No L2 Array Repairs Left"); -PRDR_ERROR_SIGNATURE( P8EX_L2_ARRAY_REPAIR_HW_OUT_OF, 0x0fff000a, "L2FIR[0]", - "No L2 Array Repairs Left in HW"); - -PRDR_ERROR_SIGNATURE( P8EX_L3CE_LD_ISSUED, 0x0fff0005, "L3FIR[4]", - "L3 Cache Read CE, Line Delete Issued"); -PRDR_ERROR_SIGNATURE( P8EX_L3CE_LD_FAILURE, 0x0fff0006, "L3FIR[4]", - "L3 Cache Read CE, Line Delete Failed"); -PRDR_ERROR_SIGNATURE( P8EX_L3_ARRAY_REPAIR_COMPLETE, 0x0fff0007, "L3FIR[4]", - "L3 Array Repair Complete"); -PRDR_ERROR_SIGNATURE( P8EX_L3_ARRAY_REPAIR_FAILURE, 0x0fff0008, "L3FIR[4]", - "L3 Array Repair Failure"); -PRDR_ERROR_SIGNATURE( P8EX_L3_ARRAY_REPAIR_OUT_OF, 0x0fff0009, "L3FIR[4]", - "No L3 Array Repairs Left"); -PRDR_ERROR_SIGNATURE( P8EX_L3_ARRAY_REPAIR_HW_OUT_OF, 0x0fff000b, "L3FIR[4]", - "No L3 Array Repairs Left in HW"); - -#endif // __prdfP8ExExtraSig_H diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfP8Proc.C b/src/usr/diag/prdf/common/plat/pegasus/prdfP8Proc.C deleted file mode 100755 index d435aac3b..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfP8Proc.C +++ /dev/null @@ -1,1035 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/diag/prdf/common/plat/pegasus/prdfP8Proc.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/** @file prdfP8Proc.C - * @brief Contains all the plugin code for the PRD P8 Proc - */ -#include <prdfPluginDef.H> -#include <iipServiceDataCollector.h> -#include <prdfExtensibleChip.H> -#include <prdfPlatServices.H> -#include <prdfPluginMap.H> -#include <prdfLaneRepair.H> -#include <prdfPhbUtils.H> -#include <prdfP8DataBundle.H> -#include <prdfP8McsDataBundle.H> -#include <prdfCalloutUtil.H> -#include <prdfCenMemUtils.H> - -using namespace TARGETING; - -namespace PRDF -{ - -using namespace PlatServices; -using namespace LaneRepair; - -namespace Proc -{ - -//############################################################################## -// -// Special plugins -// -//############################################################################## - -/** - * @brief Plugin that initializes the P8 Mba data bundle. - * @param i_chip P8 chip. - * @return SUCCESS - */ -int32_t Initialize( ExtensibleChip * i_chip ) -{ - i_chip->getDataBundle() = new P8DataBundle( i_chip ); - return SUCCESS; -} -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, Initialize ); -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, Initialize ); - -/** - * @brief Checks the Global Broadcast register. - * @param i_reg - the global recoverable register - * @param i_tpReg - the TP chiplet recoverable register - * @return true if only MC bits are on. - */ -static inline bool OnlyMcRec (SCAN_COMM_REGISTER_CLASS * i_reg, - SCAN_COMM_REGISTER_CLASS * i_tpReg) -{ - bool rc = false; - - if ( (0 == i_reg->GetBitFieldJustified(2,23)) && - (0 == i_tpReg->GetBitFieldJustified(1,2)) && - (0 != i_tpReg->GetBitFieldJustified(3,8)) && - (0 == i_tpReg->GetBitFieldJustified(11,8)) ) - { - rc = true; - } - return rc; -} - -/** - * @brief Checks the GLobal CS Brodacast register and - * the PBXSTP Chiplet register - * @param i_glcs - the Global CS Broadcast register - * @param i_tpcs - the TPXSTP register - * @param i_pbcs - the PBXSTP register - * @return true if only mem bits are on in CS, or, - * if the only other CS is External CS. - */ -static inline bool OnlyMcOrExtCS (SCAN_COMM_REGISTER_CLASS * i_glcs, - SCAN_COMM_REGISTER_CLASS * i_tpCs, - SCAN_COMM_REGISTER_CLASS * i_pbcs) -{ - bool rc = false; - - if (((0 == i_glcs->GetBitFieldJustified(3,22)) && //No CS besides TP and PB - (0 == i_tpCs->GetBitFieldJustified(3,2 )) && //No CS in TP besides MCs - (0 == i_tpCs->GetBitFieldJustified(13,8))) //No CS in TP besides MCs - && //and - (((!i_glcs->IsBitSet(2)) && // if its not from PB - (0 != i_tpCs->GetBitFieldJustified(5,8))) // and it is from a MC - || // or - ((i_glcs->IsBitSet(2)) && // it is from PB - (i_pbcs->IsBitSet(2)) && // and its external - (0 == i_pbcs->GetBitFieldJustified(3,18)))))// and nothing else in PB - { - rc = true; - } - - return rc; -} - -/** - * @brief Used when the chip has a CHECK_STOP attention to check for the - * presence of recovered errors. - * @param i_chip - P8 chip. - * @param o_hasRecovered - true if chip has a recovered that we want to analyze - * @return SUCCESS - */ -int32_t CheckForRecovered(ExtensibleChip * i_chip, - bool & o_hasRecovered) -{ - o_hasRecovered = false; - int32_t o_rc = SUCCESS; - - SCAN_COMM_REGISTER_CLASS * l_rer = - i_chip->getRegister("GLOBAL_RE_FIR"); - o_rc |= l_rer->Read(); - - SCAN_COMM_REGISTER_CLASS * l_TPrer = - i_chip->getRegister("TP_CHIPLET_RE_FIR"); - o_rc |= l_TPrer->Read(); - - SCAN_COMM_REGISTER_CLASS * l_TPxstp = - i_chip->getRegister("TP_CHIPLET_CS_FIR"); - o_rc |= l_TPxstp->Read(); - - SCAN_COMM_REGISTER_CLASS * l_xstop = - i_chip->getRegister("GLOBAL_CS_FIR"); - o_rc |= l_xstop->Read(); - - SCAN_COMM_REGISTER_CLASS * l_pbXstpFir = - i_chip->getRegister("PB_CHIPLET_CS_FIR"); - o_rc |= l_pbXstpFir->Read(); - - if (o_rc) - { - PRDF_ERR( "[CheckForRecovered] SCOM fail on 0x%08x rc=%x", - i_chip->GetId(), o_rc); - return o_rc; - } - - if ( 0 != l_rer->GetBitFieldJustified(0,32) ) - { - if ( 0 == l_TPrer->GetBitFieldJustified(3,8) ) - { //No MC Recov - o_hasRecovered = true; - } - else if ( 0 != l_TPxstp->GetBitFieldJustified(5,8) ) - { - // There is Mc Recov and Mc xstop - if ( OnlyMcRec(l_rer, l_TPrer) && - OnlyMcOrExtCS(l_xstop, l_TPxstp, l_pbXstpFir) ) - { - // Ignore the Mc Recoverable if only the Mc bits are - // on in Global Recoverable reg, and, either the only - // Global CS bits are Mc or there is an External CS. - } - else - { - o_hasRecovered = true; - } - } - else - { - // MC Recov does not match MC Xstop - o_hasRecovered = true; - } - } - - return SUCCESS; -} -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, CheckForRecovered ); -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, CheckForRecovered ); - -//------------------------------------------------------------------------------ -/** - * @brief Used when the chip is queried, by the fabric domain, for RECOVERED - * attentions to assign a severity to the attention for sorting. - * @param[in] i_chip - P8 chip - * @param[out] o_sev - Priority order (lowest to highest): - * 1 - Core chiplet checkstop - * 2 - Core chiplet error - * 3 - PCB chiplet error (TOD logic) - * 4 - Other error - * 5 - Memory controller chiplet - * - * @return SUCCESS - * - */ -int32_t CheckForRecoveredSev(ExtensibleChip * i_chip, - uint32_t & o_sev) -{ - int32_t o_rc = SUCCESS; - bool l_runtime = atRuntime(); - - SCAN_COMM_REGISTER_CLASS * l_rer = NULL; - SCAN_COMM_REGISTER_CLASS * l_TPrer = NULL; - - SCAN_COMM_REGISTER_CLASS * l_unitxstp = NULL; - if ( l_runtime ) - { - l_unitxstp = i_chip->getRegister("GLOBALUNITXSTPFIR"); - o_rc |= l_unitxstp->Read(); - } - - l_rer = i_chip->getRegister("GLOBAL_RE_FIR"); - o_rc |= l_rer->Read(); - l_TPrer = i_chip->getRegister("TP_CHIPLET_RE_FIR"); - o_rc |= l_TPrer->Read(); - - if (o_rc) - { - PRDF_ERR( "[CheckForRecoveredSev] SCOM fail on 0x%08x rc=%x", - i_chip->GetId(), o_rc); - return o_rc; - } - - if (l_TPrer->GetBitFieldJustified(3,8) != 0) - { - // errors from MCS chiplets - o_sev = 5; - } - else if(l_rer->IsBitSet(2) || l_rer->IsBitSet(4) || l_rer->IsBitSet(8)) - { - // errors from PB, X, or A bus chiplets - o_sev = 4; - } - else if(l_rer->IsBitSet(1)) - { - // error from TP (other than MCS chiplets) - o_sev = 3; - } - else if(l_runtime && - (l_rer->GetBitFieldJustified(16,16) & - l_unitxstp->GetBitFieldJustified(16,16)) == 0 ) - { - // core recoverable - o_sev = 2; - } - else - { - // core checkstop - o_sev = 1; - } - - return SUCCESS; - -} -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, CheckForRecoveredSev ); -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, CheckForRecoveredSev ); - -/** @func GetCheckstopInfo - * To be called from the fabric domain to gather Checkstop information. This - * information is used in a sorting algorithm. - * - * This is a plugin function: GetCheckstopInfo - * - * @param i_chip - The chip. - * @param o_wasInternal - True if this chip has an internal checkstop. - * @param o_externalChips - List of external fabrics driving checkstop. - * @param o_wofValue - Current WOF value (unused for now). - */ -int32_t GetCheckstopInfo( ExtensibleChip * i_chip, - bool & o_wasInternal, - TargetHandleList & o_externalChips, - uint64_t & o_wofValue ) -{ - // Clear parameters. - o_wasInternal = false; - o_externalChips.erase(o_externalChips.begin(), o_externalChips.end()); - o_wofValue = 0; - - SCAN_COMM_REGISTER_CLASS * l_globalFir = - i_chip->getRegister("GLOBAL_CS_FIR"); - - SCAN_COMM_REGISTER_CLASS * l_pbXstpFir = - i_chip->getRegister("PB_CHIPLET_CS_FIR"); - - SCAN_COMM_REGISTER_CLASS * l_extXstpFir = - i_chip->getRegister("PBEXTFIR"); - - int32_t o_rc = SUCCESS; - o_rc |= l_globalFir->Read(); - o_rc |= l_pbXstpFir->Read(); - o_rc |= l_extXstpFir->Read(); - - if(o_rc) - { - PRDF_ERR( "[GetCheckstopInfo] SCOM fail on 0x%08x rc=%x", - i_chip->GetId(), o_rc); - return o_rc; - } - - if ((0 != l_globalFir->GetBitFieldJustified(0,32)) && - (!l_globalFir->IsBitSet(2) || - !l_pbXstpFir->IsBitSet(2))) - o_wasInternal = true; - - // Get connected chips. - uint32_t l_connectedXstps = l_extXstpFir->GetBitFieldJustified(0,7); - uint32_t l_positions[] = - { - 0, // bit 0 - XBUS 0 - 1, // bit 1 - XBUS 1 - 2, // bit 2 - XBUS 2 - 3, // bit 3 - XBUS 3 - 0, // bit 4 - ABUS 0 - 1, // bit 5 - ABUS 1 - 2 // bit 6 - ABUS 2 - }; - - for (int i = 0, j = 0x40; i < 7; i++, j >>= 1) - { - if (0 != (j & l_connectedXstps)) - { - TargetHandle_t l_connectedFab = - getConnectedPeerProc(i_chip->GetChipHandle(), - i<4 ? TYPE_XBUS : TYPE_ABUS, - l_positions[i]); - - if (NULL != l_connectedFab) - { - o_externalChips.push_back(l_connectedFab); - } - } - } - - // Read WOF value. - SCAN_COMM_REGISTER_CLASS * l_wof = i_chip->getRegister("TODWOF"); - o_rc |= l_wof->Read(); - - if(o_rc) - { - PRDF_ERR( "[GetCheckstopInfo] SCOM fail on 0x%08x rc=%x", - i_chip->GetId(), o_rc); - return o_rc; - } - - o_wofValue = l_wof->GetBitFieldJustified(0,64); - - return SUCCESS; - -} -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, GetCheckstopInfo ); -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, GetCheckstopInfo ); - -int32_t CoreConfiguredAndNotHostboot(ExtensibleChip * i_chip, - bool & o_isCoreConfigured) -{ - o_isCoreConfigured = false; - - // if at not at runtime just return o_isCoreConfigured = false to prevent - // the default reg capture - if (atRuntime()) - { - // make sure this chip has config'd cores - TargetHandleList l_coreList = - PlatServices::getConnected(i_chip->GetChipHandle(), TYPE_EX); - - if (l_coreList.size() > 0) - o_isCoreConfigured = true; - } - - return SUCCESS; -} -PRDF_PLUGIN_DEFINE_NS(NaplesProc, Proc, CoreConfiguredAndNotHostboot); -PRDF_PLUGIN_DEFINE_NS(MuranoVeniceProc, Proc, CoreConfiguredAndNotHostboot); - -//------------------------------------------------------------------------------ -// Lane Repair plugins -//------------------------------------------------------------------------------ - -/** - * @brief Handles Max Spares Exceeded attentions on the MCS. - * - * This function will first check for channel fail conditions on the MCS side of - * the bus, handle the attention, then do channel fail cleanup if needed. It - * would be preferred that the channel fail handling would be done in a more - * generic way, like it is done on the MCS and MEMBUF pre/post analysis - * functions. Unfortunately, the IOMCFIRs are not on the MCS chiplet, which - * complicates things. Fortunately, the only attentions on the IOMCFIRs that are - * hardwired to channel fail are the Max Spares Exceeded attentions. Therefore, - * we can deal with the channel fail handling within this attention. - * - * @param i_procChip A PROC chip. - * @param i_sc The step code data struct. - * @param i_mcsPos The MCS position. - * @return SUCCESS always. - */ -int32_t maxSparesExceeded_MCS( ExtensibleChip * i_procChip, - STEP_CODE_DATA_STRUCT & i_sc, - uint32_t i_mcsPos ) -{ - #define PRDF_FUNC "[Proc::maxSparesExceeded_MCS] " - - int32_t l_rc = SUCCESS; - - TargetHandle_t procTrgt = i_procChip->GetChipHandle(); - TargetHandle_t mcsTrgt = NULL; - ExtensibleChip * mcsChip = NULL; - ExtensibleChip * membChip = NULL; - - do - { - // Get the connected MCS chip - mcsTrgt = getConnectedChild( procTrgt, TYPE_MCS, i_mcsPos ); - if ( NULL == mcsTrgt ) - { - PRDF_ERR( PRDF_FUNC "getConnectedChild() returned NULL" ); - l_rc = FAIL; break; - } - - mcsChip = (ExtensibleChip *)systemPtr->GetChip( mcsTrgt ); - if ( NULL == mcsChip ) - { - PRDF_ERR( PRDF_FUNC "GetChip() returned NULL" ); - l_rc = FAIL; break; - } - - // Do additional bus analysis. - l_rc = handleLaneRepairEvent( i_procChip, TYPE_MCS, i_mcsPos, i_sc, - false ); - if ( SUCCESS != l_rc ) - { - PRDF_ERR( PRDF_FUNC "handleLaneRepairEvent() failed" ); - break; - } - - // Get the connected MEMBUF chip. - P8McsDataBundle * mcsdb = getMcsDataBundle( mcsChip ); - membChip = mcsdb->getMembChip(); - if ( NULL == membChip ) - { - PRDF_ERR( PRDF_FUNC "getMembChip() returned NULL" ); - l_rc = FAIL; break; - } - - } while (0); - - if ( SUCCESS != l_rc ) - { - PRDF_ERR( PRDF_FUNC "Failed: i_procChip=0x%08x i_mcsPos=%d", - i_procChip->GetId(), i_mcsPos ); - CalloutUtil::defaultError( i_sc ); - } - - return SUCCESS; // Always return SUCCESS - - #undef PRDF_FUNC -} - -//------------------------------------------------------------------------------ - -#define PLUGIN_LANE_REPAIR( BUS, TYPE, POS ) \ -int32_t spareDeployed_##BUS##POS( ExtensibleChip * i_chip, \ - STEP_CODE_DATA_STRUCT & i_sc ) \ -{ return handleLaneRepairEvent(i_chip, TYPE, POS, i_sc, true); } \ -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, spareDeployed_##BUS##POS ); \ -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, spareDeployed_##BUS##POS ); \ - \ -int32_t maxSparesExceeded_##BUS##POS( ExtensibleChip * i_chip, \ - STEP_CODE_DATA_STRUCT & i_sc ) \ -{ return handleLaneRepairEvent(i_chip, TYPE, POS, i_sc, false); } \ -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, maxSparesExceeded_##BUS##POS ); \ -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, maxSparesExceeded_##BUS##POS ); \ -\ -int32_t tooManyBusErrors_##BUS##POS( ExtensibleChip * i_chip, \ - STEP_CODE_DATA_STRUCT & i_sc ) \ -{ return handleLaneRepairEvent(i_chip, TYPE, POS, i_sc, false); } \ -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, tooManyBusErrors_##BUS##POS ); \ -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, tooManyBusErrors_##BUS##POS ); - -PLUGIN_LANE_REPAIR( xbus, TYPE_XBUS, 0 ) -PLUGIN_LANE_REPAIR( xbus, TYPE_XBUS, 1 ) -PLUGIN_LANE_REPAIR( xbus, TYPE_XBUS, 2 ) -PLUGIN_LANE_REPAIR( xbus, TYPE_XBUS, 3 ) - -PLUGIN_LANE_REPAIR( abus, TYPE_ABUS, 0 ) -PLUGIN_LANE_REPAIR( abus, TYPE_ABUS, 1 ) -PLUGIN_LANE_REPAIR( abus, TYPE_ABUS, 2 ) - -#undef PLUGIN_LANE_REPAIR - -#define PLUGIN_LANE_REPAIR( POS ) \ -int32_t spareDeployed_dmiBus##POS( ExtensibleChip * i_chip, \ - STEP_CODE_DATA_STRUCT & i_sc ) \ -{ return handleLaneRepairEvent(i_chip, TYPE_MCS, POS, i_sc, true); } \ -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, spareDeployed_dmiBus##POS ); \ -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, spareDeployed_dmiBus##POS ); \ - \ -int32_t maxSparesExceeded_dmiBus##POS( ExtensibleChip * i_chip, \ - STEP_CODE_DATA_STRUCT & i_sc ) \ -{ return maxSparesExceeded_MCS(i_chip, i_sc, POS); } \ -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, maxSparesExceeded_dmiBus##POS ); \ -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, maxSparesExceeded_dmiBus##POS ); - -// Too Many Bus Error attentions not handled on DMI bus. - -PLUGIN_LANE_REPAIR( 0 ) -PLUGIN_LANE_REPAIR( 1 ) -PLUGIN_LANE_REPAIR( 2 ) -PLUGIN_LANE_REPAIR( 3 ) -PLUGIN_LANE_REPAIR( 4 ) -PLUGIN_LANE_REPAIR( 5 ) -PLUGIN_LANE_REPAIR( 6 ) -PLUGIN_LANE_REPAIR( 7 ) - -#undef PLUGIN_LANE_REPAIR - -/** - * @brief checks if MCS block is configured. - * @param i_chip P8 chip. - * @param i_mcsBlk MCS block ( 0 : ( 0- 3 MCS) ), ( 1 :( 4-7 MCS )) - * @param o_isMcsBlkConfigured TRUE if block is configured false otherwise. - * @return SUCCESS - */ -int32_t mcsBlockConfigured( ExtensibleChip * i_chip, - uint8_t i_mcsBlk, - bool & o_isMcsBlkConfigured ) -{ - o_isMcsBlkConfigured = false; - - // Starting MCS position for MCS block - uint8_t firstMcsPos[ 2 ] = { 0, 4 }; - - // Get functional MCS list - TargetHandleList l_mcsList = - PlatServices::getConnected(i_chip->GetChipHandle(), TYPE_MCS); - - for ( TargetHandleList::iterator i = l_mcsList.begin(); - i != l_mcsList.end(); ++i ) - { - uint8_t pos = getTargetPosition(*i); - if( ( pos >= firstMcsPos[ i_mcsBlk ] ) && - ( pos <= ( firstMcsPos[ i_mcsBlk ] + 3) ) ) - { - o_isMcsBlkConfigured = true; - break; - } - } - - return SUCCESS; -} - -#define PLUGIN_MCS_BLOCK_CONFIGURED( POS ) \ -int32_t mcsBlockConfigured_##POS( ExtensibleChip * i_chip, \ - bool & o_isMcsBlkConfigured ) \ -{ return mcsBlockConfigured( i_chip, POS, o_isMcsBlkConfigured ); } \ -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, mcsBlockConfigured_##POS ); \ -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, mcsBlockConfigured_##POS ); - -PLUGIN_MCS_BLOCK_CONFIGURED( 0 ) -PLUGIN_MCS_BLOCK_CONFIGURED( 1 ) - -#undef PLUGIN_MCS_BLOCK_CONFIGURED - -//------------------------------------------------------------------------------ -// Callout plugins -//------------------------------------------------------------------------------ - -/** - * @brief Call to check for configured PHB (before capturing FFDC) - * @param i_chip P8 chip - * @param i_phbPos PHB position - * @param o_isPhbConfigured set to true if the PHB configured - * @returns Success - */ -int32_t phbConfigured( ExtensibleChip * i_chip, uint32_t i_phbPos, - bool & o_isPhbConfigured ) -{ - #define PRDF_FUNC "[Proc::phbConfigured] " - - o_isPhbConfigured = false; - - uint32_t maxPhbs = 3; // Murano/Venice - if ( MODEL_NAPLES == getProcModel(i_chip->GetChipHandle()) ) - maxPhbs = 4; - - do - { - if ( maxPhbs <= i_phbPos ) - { - // This PHB doesn't exist, return false - break; - } - - char reg_str[64]; - snprintf( reg_str, 64, "PCI_ETU_RESET_%d", i_phbPos ); - - SCAN_COMM_REGISTER_CLASS * reg = i_chip->getRegister( reg_str ); - if ( NULL == reg ) - { - PRDF_ERR( PRDF_FUNC"getRegister() failed for %s", reg_str ); - break; - } - - int32_t l_rc = reg->Read(); - if ( SUCCESS != l_rc ) - { - PRDF_ERR( PRDF_FUNC"Read() failed for %s: target=0x%08x", - reg_str, i_chip->GetId() ); - break; - } - - // If bit 0 is cleared then the PHB is configured - if ( !reg->IsBitSet(0) ) - { - o_isPhbConfigured = true; - } - - } while(0); - - return SUCCESS; - - #undef PRDF_FUNC -} - -#define PLUGIN_PHB_CONFIGURED( POS ) \ -int32_t phbConfigured_##POS( ExtensibleChip * i_chip, \ - bool & o_isPhbConfigured ) \ -{ return phbConfigured( i_chip, POS, o_isPhbConfigured ); } \ -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, phbConfigured_##POS ); \ -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, phbConfigured_##POS ); - -PLUGIN_PHB_CONFIGURED( 0 ) -PLUGIN_PHB_CONFIGURED( 1 ) -PLUGIN_PHB_CONFIGURED( 2 ) -PLUGIN_PHB_CONFIGURED( 3 ) - -#undef PLUGIN_PHB_CONFIGURED - -//------------------------------------------------------------------------------ - -/** - * @brief calls out master Ex of the node and SBE FFDC - * @param i_chip P8 chip - * @param i_sc service data collector - * @returns Success - */ -int32_t deadManTimerCalloutAndFFDC( ExtensibleChip * i_chip, - STEP_CODE_DATA_STRUCT & io_sc ) -{ - #define PRDF_FUNC "[deadManTimerCalloutAndFFDC] " - - TargetHandle_t l_procTgt = i_chip->GetChipHandle(); - - TargetHandle_t l_masterCore = PlatServices::getMasterCore( l_procTgt ); - if( NULL == l_masterCore ) - { - PRDF_ERR( PRDF_FUNC "Failed to get master core: PROC = 0x%08x", - i_chip->GetId() ); - } - else - io_sc.service_data->SetCallout( l_masterCore ); - - // Call proc_extract_sbe_rc here to see what went wrong - PlatServices::collectSBE_FFDC(l_procTgt); - - return SUCCESS; - - #undef PRDF_FUNC -} -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, deadManTimerCalloutAndFFDC ); -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, deadManTimerCalloutAndFFDC ); - -//------------------------------------------------------------------------------ - -/** - * @brief Calls out the EX chiplet (MRU_LOW), if possible. Otherwise, calls - * out the PROC (MRU_LOW) - * @param i_chip P8 chip - * @param io_sc service data collector - * @returns SUCCESS - */ -int32_t combinedResponseCallout( ExtensibleChip * i_chip, - STEP_CODE_DATA_STRUCT & io_sc ) -{ - #define PRDF_FUNC "[Proc::combinedResponseCallout] " - - int32_t l_rc = SUCCESS; - - TargetHandle_t procTrgt = i_chip->GetChipHandle(); - - SCAN_COMM_REGISTER_CLASS * reg = i_chip->getRegister("PB_CENT_CR_ERROR"); - - do - { - l_rc = reg->Read(); - if ( SUCCESS != l_rc ) - { - PRDF_ERR( PRDF_FUNC "Read() failed on PB_CENT_CR_ERROR" ); - break; - } - - uint32_t tmp = reg->GetBitFieldJustified(0,3); - if ( 0x02 != tmp ) // Must be 0b010 to continue - { - PRDF_ERR( PRDF_FUNC "Unsupported reason code: 0x%02x", tmp ); - l_rc = FAIL; break; - } - - tmp = reg->GetBitFieldJustified(38,5); - if ( 0x00 != tmp ) // Must be 0b00000 to continue - { - PRDF_ERR( PRDF_FUNC "Unsupported combined response encoding: 0x%02x", - tmp ); - l_rc = FAIL; break; - } - - if ( reg->IsBitSet(22) ) // Must be 0b0 to continue - { - PRDF_ERR( PRDF_FUNC "Operation not sourced by an EX chiplet" ); - l_rc = FAIL; break; - } - - // Get the EX target - tmp = reg->GetBitFieldJustified(23,4); - TargetHandle_t exTrgt = getConnectedChild( procTrgt, TYPE_EX, tmp ); - if ( NULL == exTrgt ) - { - PRDF_ERR( PRDF_FUNC "No connected EX chiplet at position %d", tmp ); - l_rc = FAIL; break; - } - - // Callout the EX target - io_sc.service_data->SetCallout( exTrgt, MRU_LOW ); - - } while (0); - - if ( SUCCESS != l_rc ) - { - PRDF_ERR( PRDF_FUNC "Unable to isolate to an EX chiplet. Calling out " - "PROC 0x%08x instead.", i_chip->GetId() ); - - io_sc.service_data->SetCallout( procTrgt, MRU_LOW ); - } - - return SUCCESS; - - #undef PRDF_FUNC -} -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, combinedResponseCallout ); -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, combinedResponseCallout ); - -//------------------------------------------------------------------------------ - -#define PLUGIN_BUS_INTERFACE_CALLOUT( BUS, TYPE, POS ) \ -int32_t calloutInterface_##BUS##POS( ExtensibleChip * i_chip, \ - STEP_CODE_DATA_STRUCT & io_sc ) \ -{ \ - CalloutUtil::calloutBusInterface(i_chip, MRU_LOW, TYPE, POS); \ - return SUCCESS; \ -} \ -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, calloutInterface_##BUS##POS ); \ -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, calloutInterface_##BUS##POS ); - -PLUGIN_BUS_INTERFACE_CALLOUT( abus, TYPE_ABUS, 0 ) -PLUGIN_BUS_INTERFACE_CALLOUT( abus, TYPE_ABUS, 1 ) -PLUGIN_BUS_INTERFACE_CALLOUT( abus, TYPE_ABUS, 2 ) - -PLUGIN_BUS_INTERFACE_CALLOUT( xbus, TYPE_XBUS, 0 ) -PLUGIN_BUS_INTERFACE_CALLOUT( xbus, TYPE_XBUS, 1 ) -PLUGIN_BUS_INTERFACE_CALLOUT( xbus, TYPE_XBUS, 2 ) -PLUGIN_BUS_INTERFACE_CALLOUT( xbus, TYPE_XBUS, 3 ) - -PLUGIN_BUS_INTERFACE_CALLOUT( dmi, TYPE_MCS, 0 ) -PLUGIN_BUS_INTERFACE_CALLOUT( dmi, TYPE_MCS, 1 ) -PLUGIN_BUS_INTERFACE_CALLOUT( dmi, TYPE_MCS, 2 ) -PLUGIN_BUS_INTERFACE_CALLOUT( dmi, TYPE_MCS, 3 ) -PLUGIN_BUS_INTERFACE_CALLOUT( dmi, TYPE_MCS, 4 ) -PLUGIN_BUS_INTERFACE_CALLOUT( dmi, TYPE_MCS, 5 ) -PLUGIN_BUS_INTERFACE_CALLOUT( dmi, TYPE_MCS, 6 ) -PLUGIN_BUS_INTERFACE_CALLOUT( dmi, TYPE_MCS, 7 ) - -#undef PLUGIN_BUS_INTERFACE_CALLOUT - -//------------------------------------------------------------------------------ -// PHB Plugins for IOPCIFIR_x -//------------------------------------------------------------------------------ - -/** - * @brief Calls out PHB targets associated with given processor. - * @param i_procChip Chip reporting attention. - * @param io_sc The step code data struct. - * @param i_iopciIdx IOPCIFIR instance number (0,1) - * @param i_calloutPhbA True if error is from clock A, false otherwise. - * @param i_calloutPhbB True if error is from clock B, false otherwise. - * @return Always SUCCESS. - */ -int32_t calloutPhb( ExtensibleChip * i_procChip, STEP_CODE_DATA_STRUCT & io_sc, - uint32_t i_iopciIdx, bool i_calloutPhbA, bool i_calloutPhbB) -{ - #define PRDF_FUNC "[Proc::calloutPhb] " - - uint32_t l_rc = SUCCESS; - - TargetHandle_t procTrgt = i_procChip->GetChipHandle(); - TargetHandle_t phbATrgt = NULL; - TargetHandle_t phbBTrgt = NULL; - - // Callout clock A - if ( i_calloutPhbA ) - { - if ( SUCCESS != getConfiguredPHB(procTrgt, i_iopciIdx, 0, phbATrgt) ) - { - PRDF_ERR( PRDF_FUNC "getConfiguredPHB(0) failed: i_procChip=0x%08x " - "i_iopciIdx=%d", i_procChip->GetId(), i_iopciIdx ); - l_rc = FAIL; - } - else if ( NULL != phbATrgt ) - { - io_sc.service_data->SetCallout( phbATrgt, MRU_MED, PRDF::NO_GARD ); - } - } - - // Callout clock B - if ( i_calloutPhbB ) - { - if ( SUCCESS != getConfiguredPHB(procTrgt, i_iopciIdx, 1, phbBTrgt) ) - { - PRDF_ERR( PRDF_FUNC "getConfiguredPHB(1) failed: i_procChip=0x%08x " - "i_iopciIdx=%d", i_procChip->GetId(), i_iopciIdx ); - l_rc = FAIL; - } - else if ( (NULL != phbBTrgt) && (phbATrgt != phbBTrgt) ) - { - io_sc.service_data->SetCallout( phbBTrgt, MRU_MED, PRDF::NO_GARD ); - } - } - - // If no PHBs called out, callout 2nd level support. - if ( (SUCCESS != l_rc) || (0 == io_sc.service_data->getMruListSize()) ) - io_sc.service_data->SetCallout( LEVEL2_SUPPORT, MRU_MED, NO_GARD ); - - return SUCCESS; // Intentionally returns SUCCESS so rule code does not get - // confused by undefined error code. - - #undef PRDF_FUNC -} - -#define PLUGIN_CALLOUT_PHB( CLK,IOPCI,ERRA,ERRB ) \ -int32_t calloutPhbClk##CLK##_##IOPCI( ExtensibleChip * i_chip, \ - STEP_CODE_DATA_STRUCT & i_sc ) \ -{ \ - return calloutPhb( i_chip, i_sc, IOPCI, ERRA, ERRB ); \ -}\ -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, calloutPhbClk##CLK##_##IOPCI ); \ -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, calloutPhbClk##CLK##_##IOPCI ); - -PLUGIN_CALLOUT_PHB( A, 0, true, false ) -PLUGIN_CALLOUT_PHB( B, 0, false, true ) -PLUGIN_CALLOUT_PHB( A, 1, true, false ) -PLUGIN_CALLOUT_PHB( B, 1, false, true ) -PLUGIN_CALLOUT_PHB( A, 2, true, false ) -PLUGIN_CALLOUT_PHB( B, 2, false, true ) - -#undef PLUGIN_CALLOUT_PHB - -#define PLUGIN_CALLOUT_PHB( IOPCI ) \ -int32_t calloutPhbBothClks_##IOPCI( ExtensibleChip * i_chip, \ - STEP_CODE_DATA_STRUCT & i_sc ) \ -{ \ - return calloutPhb( i_chip, i_sc, IOPCI, true, true ); \ -}\ -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, calloutPhbBothClks_##IOPCI ); \ -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, calloutPhbBothClks_##IOPCI ); - -PLUGIN_CALLOUT_PHB( 0 ) -PLUGIN_CALLOUT_PHB( 1 ) -PLUGIN_CALLOUT_PHB( 2 ) - -#undef PLUGIN_CALLOUT_PHB - -//------------------------------------------------------------------------------ -// Misc plugins -//------------------------------------------------------------------------------ - -/** - * @brief Checks if this PROC is NOT a Murano chip. - * @param i_chip P8/P8+ chip. - * @param o_isNotMurano TRUE if this PROC is NOT a Murano chip, FALSE - * otherwise. - * @return SUCCESS - */ -int32_t isNotMuranoProc( ExtensibleChip * i_chip, bool & o_isNotMurano ) -{ - o_isNotMurano = false; - if ( MODEL_MURANO != getProcModel( i_chip->GetChipHandle() ) ) - o_isNotMurano = true; - - return SUCCESS; -} -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, isNotMuranoProc ); -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, isNotMuranoProc ); - -/** - * @brief Checks if this PROC is a Naples chip. - * @param i_chip P8/P8+ chip. - * @param o_isNaples TRUE if this PROC is a Naples chip, FALSE otherwise. - * @return SUCCESS - */ -int32_t isNaplesProc( ExtensibleChip * i_chip, bool & o_isNaples ) -{ - o_isNaples = false; - if ( MODEL_NAPLES == getProcModel( i_chip->GetChipHandle() ) ) - o_isNaples = true; - - return SUCCESS; -} -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, isNaplesProc ); -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, isNaplesProc ); - -/** - * * @brief Checks if this PROC is a Naples chip. - * @param i_chip P8/P8+ chip. - * @return FAIL if not naples, SUCCESS if naples -*/ -int32_t failIfNaples( ExtensibleChip * i_chip ) -{ - if ( MODEL_NAPLES == getProcModel( i_chip->GetChipHandle() ) ) - return FAIL; - - return SUCCESS; -} -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, failIfNaples ); -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, failIfNaples ); - - -/** - * @brief Checks if this PROC is NOT a Naples chip. - * @param i_chip P8/P8+ chip. - * @param o_isNotNaples TRUE if this PROC is NOT a Naples chip, FALSE - * otherwise. - * @return SUCCESS - */ -int32_t isNotNaplesProc( ExtensibleChip * i_chip, bool & o_isNotNaples ) -{ - o_isNotNaples = false; - if ( MODEL_NAPLES != getProcModel( i_chip->GetChipHandle() ) ) - o_isNotNaples = true; - - return SUCCESS; -} -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, isNotNaplesProc ); -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, isNotNaplesProc ); - -/** - * @brief Checks if this PROC is a Naples chip. - * @param i_chip P8/P8+ chip. - * @return SUCCESS if not naples, FAIL if naples -*/ -int32_t failIfNotNaples( ExtensibleChip * i_chip ) -{ - if ( MODEL_NAPLES != getProcModel( i_chip->GetChipHandle() ) ) - return FAIL; - - return SUCCESS; -} -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, failIfNotNaples ); -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, failIfNotNaples ); - - -/** - * @brief checks if proc is Murano chip and is at DD1.x level. - * @param i_chip P8 chip. - * @param o_isMuranoDD1 TRUE if chip is murano DD1.x FALSE otherwise. - * @return SUCCESS - */ -int32_t isMuranoDD1( ExtensibleChip * i_chip, bool & o_isMuranoDD1 ) -{ - o_isMuranoDD1 = false; - if( ( MODEL_MURANO == getProcModel( i_chip->GetChipHandle() ) ) && - ( 0x20 > getChipLevel( i_chip->GetChipHandle() ) ) ) - o_isMuranoDD1 = true; - - return SUCCESS; -} -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, isMuranoDD1 ); -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, isMuranoDD1 ); - -/** - * @brief Checks if XBUS is enabled - * @param i_chip P8 chip - * @param o_xbusEnabled TRUE if xbus enabled - */ -int32_t isXBusEnabled( ExtensibleChip * i_chip, bool & o_xbusEnabled ) -{ - o_xbusEnabled = PlatServices::isXBusEnabled(i_chip->GetChipHandle()); - return SUCCESS; -} -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, isXBusEnabled ); -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, isXBusEnabled ); - -/** - * @brief Checks if not murano chip and XBUS is enabled - * @param i_chip P8 chip - * @param o_captureAllowed TRUE if not murano and xbus enabled - */ -int32_t notMuranoAndXbEnabled( ExtensibleChip * i_chip, - bool & o_captureAllowed ) -{ - o_captureAllowed = - ( ( MODEL_MURANO != getProcModel( i_chip->GetChipHandle() ) ) && - PlatServices::isXBusEnabled(i_chip->GetChipHandle()) ); - - return SUCCESS; -} -PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, notMuranoAndXbEnabled ); -PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, notMuranoAndXbEnabled ); - -} // end namespace Proc - -} // end namespace PRDF diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfP8ProcExtraSig.H b/src/usr/diag/prdf/common/plat/pegasus/prdfP8ProcExtraSig.H deleted file mode 100644 index 279aab400..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfP8ProcExtraSig.H +++ /dev/null @@ -1,44 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/diag/prdf/common/plat/pegasus/prdfP8ProcExtraSig.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -#ifndef __prdfP8ProcExtraSig_H -#define __prdfP8ProcExtraSig_H - -#include <prdrSignatures.H> - -PRDR_ERROR_SIGNATURE( PCI_OSC0_FAILOVER, 0x00ed0001, "","PCI Osc0 Failed" ); -PRDR_ERROR_SIGNATURE( PCI_OSC1_FAILOVER, 0x00ed0002, "","PCI Osc1 Failed" ); -PRDR_ERROR_SIGNATURE( MULTI_PROC_PCI_OSC0_FAILOVER, 0x00ed0003, "", - "PCI Osc0 Failed: Multiple Proc" ); -PRDR_ERROR_SIGNATURE( MULTI_PROC_PCI_OSC1_FAILOVER, 0x00ed0004, "", - "PCI Osc1 Failed: Multiple Proc" ); -PRDR_ERROR_SIGNATURE( PCI_OSC_FALSE_ALARM,0x00ed0005, "", - "PCI Osc Failed: False Alarm" ); -PRDR_ERROR_SIGNATURE( PCI_OSC_ANL_FAILED, 0x00ed0006, "", - "PCI Osc Switch Over: Analysis failed" ); -PRDR_ERROR_SIGNATURE( PCI_MULTIPLE_OSC_FO, 0x00ed0007, "", - "PCI Osc Failed: Multiple Osc" ); - -#endif // __prdfP8ProcExtraSig.H diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfPciOscSwitchDomain.C b/src/usr/diag/prdf/common/plat/pegasus/prdfPciOscSwitchDomain.C deleted file mode 100755 index 0495b47c1..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfPciOscSwitchDomain.C +++ /dev/null @@ -1,418 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/diag/prdf/common/plat/pegasus/prdfPciOscSwitchDomain.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/** @file PciOscSwitchDomain.C - * @brief Definition of PllDomain class - */ - -#include <iipscr.h> -#include <iipsdbug.h> -#include <iipServiceDataCollector.h> -#include <prdfErrorSignature.H> -#include <iipResolution.h> -#include <prdfPlatServices.H> -#include <prdfPluginDef.H> -#include <prdfGlobal.H> -#include <iipSystem.h> -#include <UtilHash.H> -#include <prdfPciOscSwitchDomain.H> -#include <prdfP8ProcExtraSig.H> - -#ifndef __HOSTBOOT_MODULE -#include <hdctContent.H> -#include <prdfSdcFileControl.H> -#endif - -using namespace TARGETING; - -namespace PRDF -{ - -using namespace PlatServices; - -//------------------------------------------------------------------------------ - -int32_t PciOscSwitchDomain::Initialize(void) -{ - return SUCCESS; -} - -//------------------------------------------------------------------------------ - -bool PciOscSwitchDomain::Query(ATTENTION_TYPE attentionType) -{ - #define PRDF_FUNC "PciOscSwitchDomain::Query " - bool errorFound = false; - - // Only check for PCI osc switchover on redundant clock systems - // System always checks for RE's first, even if there is an XSTOP - // So we only need to check for PLL errors on RECOVERABLE type - if( hasRedundantClocks() && ( attentionType == RECOVERABLE ) ) - { - // check sysdbug for attention first - SYSTEM_DEBUG_CLASS sysdbug; - for( unsigned int index = 0; - (index < GetSize()) && (errorFound == false); ++index ) - { - ExtensibleChip * l_chip = LookUp( index ); - TARGETING::TargetHandle_t l_chipTgt = l_chip->GetChipHandle(); - bool l_analysisPending = - sysdbug.isActiveAttentionPending( l_chipTgt, RECOVERABLE ); - - if( l_analysisPending ) - { - ExtensibleChipFunction * l_query = - l_chip->getExtensibleFunction("queryPciOscErr"); - int32_t rc = (*l_query)(l_chip, - PluginDef::bindParm< bool &>(errorFound) ); - - // if rc then scom read failed - Error log has already - // been generated. - - if( PRD_POWER_FAULT == rc ) - { - PRDF_ERR( PRDF_FUNC "Power Fault detected!" ); - break; - } - - if( SUCCESS != rc ) - { - PRDF_ERR( PRDF_FUNC "SCOM fail. RC=%x", rc ); - } - } - } - } - - #undef PRDF_FUNC - return errorFound; -} - -//------------------------------------------------------------------------------ -int32_t PciOscSwitchDomain::Analyze( STEP_CODE_DATA_STRUCT & i_sc, - ATTENTION_TYPE i_attentionType ) -{ - #define PRDF_FUNC "PciOscSwitchDomain::Analyze " - - int32_t o_rc = SUCCESS; - bool foundAttn = false; - - for( uint32_t index = 0; index < GetSize(); ++index ) - { - ExtensibleChip * l_chip = LookUp( index ); - ExtensibleChipFunction * l_query = - l_chip->getExtensibleFunction( "queryPciOscErr" ); - - if( NULL == l_query ) - { - continue; - } - - o_rc = (*l_query)(l_chip, - PluginDef::bindParm< bool &>(foundAttn) ); - - if( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "Query failed HUID: 0x%08x", l_chip->GetId() ); - break; - } - - if( foundAttn ) - { - // Set Signature - i_sc.service_data->GetErrorSignature()->setChipId( - l_chip->GetId()); - - PciOscConnList l_pciOscData; - o_rc = analyzePciOscSwitch( l_chip, i_sc, l_pciOscData ); - - if( SUCCESS != o_rc ) - { - PRDF_ERR(PRDF_FUNC " PCI CLK Switch over analysis failed" ); - break; - } - - addHwCalloutAndSignature( i_sc, l_pciOscData ); - - // Set dump flag - i_sc.service_data->SetDump( CONTENT_HW, - l_chip->GetChipHandle() ); - break; - } - }//end of for loop - - #undef PRDF_FUNC - return o_rc; -} - -//------------------------------------------------------------------------------ - -int32_t PciOscSwitchDomain::analyzePciOscSwitch( - ExtensibleChip * i_chip, - STEP_CODE_DATA_STRUCT & i_sc, - PciOscConnList & o_pciOscSwitchData ) -{ - #define PRDF_FUNC "PciOscSwitchDomain::analyzePciOscSwitch " - int32_t o_rc = SUCCESS; - - do - { - - TargetHandle_t l_chipTgt = i_chip->GetChipHandle(); - ExtensibleChipFunction * l_anlzPci = - i_chip->getExtensibleFunction( "analyzePciClkFailover" ); - - if( NULL == l_anlzPci ) - { - o_rc = FAIL; - break; - } - - TargetHandle_t nodeTgt = getConnectedParent( l_chipTgt, TYPE_NODE ); - - if( NULL == nodeTgt ) - { - PRDF_ERR( PRDF_FUNC "unable to get node HUID: 0x%08x ", - i_chip->GetId() ); - o_rc = FAIL; - break; - } - - TargetHandleList pciConProcList = getConnected( nodeTgt, TYPE_PROC ); - - for( TargetHandleList::iterator it = pciConProcList.begin(); - it != pciConProcList.end(); it++ ) - { - ExtensibleChip * l_procChip = findChip( *it ); - - if( NULL == l_procChip ) - { - PRDF_ERR( PRDF_FUNC " could not find chip 0x%08x", - getHuid(*it) ); - continue; - } - - // Capture PllFIRs group - l_procChip->CaptureErrorData( - i_sc.service_data->GetCaptureData(), - Util::hashString("PllFIRs")); - - // Call this chip's capturePllFfdc plugin if it exists. - ExtensibleChipFunction * l_captureFfdc = - l_procChip->getExtensibleFunction("capturePllFfdcIo", true); - - if ( NULL != l_captureFfdc ) - { - (*l_captureFfdc)( l_procChip, - PluginDef::bindParm<STEP_CODE_DATA_STRUCT &> - (i_sc) ); - } - - o_rc = (*l_anlzPci)( l_procChip, - PluginDef::bindParm< PciOscConnList& > - ( o_pciOscSwitchData )); - if( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "analysis failed HUID: 0x%08x", - l_procChip->GetId() ); - break; - } - } - - #ifndef __HOSTBOOT_MODULE - ServiceDataCollector & sdc = *(i_sc.service_data); - SyncAnalysis (sdc); //Add call to Sync SDC - #endif - - o_rc = clearPciSwitchError( o_pciOscSwitchData ); - - if( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC " Failed to clear PCI Osc error" ); - break; - } - - }while(0); - - #undef PRDF_FUNC - - return o_rc; -} - -//------------------------------------------------------------------------------ - -bool PciOscSwitchDomain::checkMultiOscFailure( PciOscConnList & i_pciOscData ) -{ - bool o_multipleOscFail = false; - do - { - if( 0 == i_pciOscData.size() ) - { - break; - } - - PciOscConnList::iterator it = i_pciOscData.begin(); - uint32_t firstOscPos = it->pciOscPosition; - - for( ; it != i_pciOscData.end(); it++ ) - { - if( firstOscPos != it->pciOscPosition ) - { - o_multipleOscFail = true; - break; - } - } - - }while(0); - - return o_multipleOscFail; -} - -//------------------------------------------------------------------------------ - -void PciOscSwitchDomain::addHwCalloutAndSignature( STEP_CODE_DATA_STRUCT & i_sc, - PciOscConnList & i_pciOscSwitchData ) -{ - #define PRDF_FUNC "PciOscSwitchDomain::addHwCalloutAndSignature " - ErrorSignature * esig = i_sc.service_data->GetErrorSignature(); - uint32_t signature = esig->getSigId(); - - do - { - uint32_t listSize = i_pciOscSwitchData.size(); - - if( 0 == listSize ) - { - PRDF_ERR( PRDF_FUNC "PCI Osc Switch Over: Analysis failed"); - i_sc.service_data->SetCallout( LEVEL2_SUPPORT, MRU_MED, NO_GARD ); - signature = PRDFSIG_PCI_OSC_ANL_FAILED; - break; - } - - PciOscConnList::iterator it = i_pciOscSwitchData.begin(); - TargetHandle_t procTgt = it->pciParentProc->GetChipHandle(); - TargetHandle_t l_nodeTgt = - getConnectedParent( procTgt, TYPE_NODE ); - - if( 1 < listSize ) - { - if( 0 == it->pciOscPosition ) - { - signature = PRDFSIG_MULTI_PROC_PCI_OSC0_FAILOVER; - } - else - { - signature = PRDFSIG_MULTI_PROC_PCI_OSC1_FAILOVER; - } - - if( checkMultiOscFailure( i_pciOscSwitchData ) ) - { - PRDF_ERR( PRDF_FUNC "Multiple pci Osc failures detected"); - signature = PRDFSIG_PCI_MULTIPLE_OSC_FO; - i_sc.service_data->SetCallout(LEVEL2_SUPPORT, MRU_MED, NO_GARD); - } - - i_sc.service_data->SetCallout( it->pciOscCard, MRU_HIGH ); - i_sc.service_data->SetCallout( l_nodeTgt, MRU_LOW, NO_GARD ); - } - else - { - // Pci Osc endpoints are not supported as gardable - // so instead, we'll need to callout/gard the source PCI OSC - i_sc.service_data->SetCallout( procTgt, MRU_MED, NO_GARD); - i_sc.service_data->SetCallout( l_nodeTgt, MRU_LOW , NO_GARD ); - i_sc.service_data->SetCallout( it->pciOscCard, MRU_HIGH ); - //i_sc.service_data->SetCallout( it->procPciEndPoint, MRU_MEDA ); - //i_sc.service_data->SetCallout( it->oscPciEndPoint, MRU_MEDA ); - - if( 0 == it->pciOscPosition ) - { - signature = PRDFSIG_PCI_OSC0_FAILOVER; - } - else - { - signature = PRDFSIG_PCI_OSC1_FAILOVER; - } - } - }while(0); - - i_sc.service_data->SetErrorSig( signature ); - i_sc.service_data->setServiceCall(); - #undef PRDF_FUNC -} - -//------------------------------------------------------------------------------ - -int32_t PciOscSwitchDomain::clearPciSwitchError( - PciOscConnList & io_oscSwitchData ) -{ - #define PRDF_FUNC "PciOscSwitchDomain::clearPciSwitchError " - uint32_t o_rc = SUCCESS; - - for( PciOscConnList::iterator it = io_oscSwitchData.begin(); - it != io_oscSwitchData.end(); it++ ) - { - ExtensibleChipFunction * l_clrPci = - it->pciParentProc->getExtensibleFunction("clearPciOscFailOver"); - - o_rc = (* l_clrPci )( it->pciParentProc, - PluginDef::bindParm< uint32_t &> ( it->pciOscPosition )); - - if( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC " Failed to clear PCI clk error bits" - "HUID: 0x%08x", it->pciParentProc->GetId() ); - break; - } - - } - - #undef PRDF_FUNC - return o_rc; -} - -void PciOscSwitchDomain::Order( ATTENTION_TYPE i_attentionType ) -{ - //Order is not relevant. -} - -ExtensibleChip * PciOscSwitchDomain::findChip( TargetHandle_t i_chipTgt ) -{ - ExtensibleChip * l_procChip = NULL; - for( uint32_t i = 0; i < GetSize(); i++ ) - { - l_procChip = LookUp( i ); - if( i_chipTgt == l_procChip->GetChipHandle() ) - { - break; - } - - l_procChip = NULL; - } - - return l_procChip; -} - -} // end namespace PRDF - diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfPciOscSwitchDomain.H b/src/usr/diag/prdf/common/plat/pegasus/prdfPciOscSwitchDomain.H deleted file mode 100644 index 8438988dc..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfPciOscSwitchDomain.H +++ /dev/null @@ -1,150 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/diag/prdf/common/plat/pegasus/prdfPciOscSwitchDomain.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -#ifndef prdfPciOscDomain_H -#define prdfPciOscDomain_H - -#include <iipDomain.h> -#include <prdfExtensibleDomain.H> -#include <prdfParentDomain.H> -#include <prdfRuleChipDomain.H> - - -namespace PRDF -{ -struct PciOscSwitchDetails -{ - ExtensibleChip * pciParentProc; - TARGETING::TargetHandle_t pciOscCard; - uint32_t pciOscPosition; - TARGETING::TargetHandle_t procPciEndPoint; - TARGETING::TargetHandle_t oscPciEndPoint; - bool pciOscSwitchDone; -}; - -typedef std::vector <PciOscSwitchDetails> PciOscConnList; - -//------------------------------------------------------------------------------ - -class PciOscSwitchDomain : public RuleChipDomain, public ExtensibleDomain, - public ParentDomain<ExtensibleDomain> -{ - public: - - /** - * @brief Constructor - * @param DOMAIN_ID the domain ID - */ - PciOscSwitchDomain( DOMAIN_ID domain_id ); - - /** - * @brief Perform any initialization required by the hardware - * @returns error code - */ - virtual int32_t Initialize(void); - - /** - * @brief Query if anything in this domain is reporting given attention. - * @param Attention type to query for. (@see iipsdbug.h) - * @returns [true|false] - * @pre Initialize() - */ - virtual bool Query(ATTENTION_TYPE attentionType); - - /** - * @brief Analyze errors within the domain - * @param service data collector - * @param attentiont type (@see iipsdbug.h) - * @return return code - * @pre Initialize(); Query() == true - * @post domain element order may be modified. - */ - virtual int32_t Analyze( STEP_CODE_DATA_STRUCT & i_sc, - ATTENTION_TYPE attentionType ); -protected: - - /** - * @brief Order the domain - with detecting element at the top - * @param Attention type (@see iipsdbug.h) - * @post domain elemenet order may be altered - * @note this is called by Analyze() - */ - virtual void Order( ATTENTION_TYPE i_attentionType ); - - private: // function - - /** - * @brief analyzes all the procs reporting switchover from a given pci osc. - * @param i_chip A P8 chip. - * @param i_sc The step code data struct. - * @param o_pciOscSwitchData contains pci osc switch over data. - * @note this is called by Analyze() - */ - int32_t analyzePciOscSwitch( ExtensibleChip * i_chip, - STEP_CODE_DATA_STRUCT & i_sc, - PciOscConnList & o_pciOscSwitchData ); - /** - * @brief clears few bits to reset PCI Osc switch over bit. - * @param io_oscSwitchData list of procs connected to faulty PCI OSC. - * @return SUCCESS if clearing of bit is success, FAIL otherwise. - */ - int32_t clearPciSwitchError( PciOscConnList & io_oscSwitchData ); - - /** - * @brief callout hardware parts and add signature based analysis data. - * @param i_sc The step code data struct. - * @param i_pciOscSwitchData contains PCI osc failover data. - */ - void addHwCalloutAndSignature( STEP_CODE_DATA_STRUCT & i_sc, - PciOscConnList & i_pciOscSwitchData ); - /** - * @brief checks if there is multiple PCI Osc failure. - * @param pciOscSwitchData PCI Osc fault data. - * @return True if there is multiple PCI Osc failure, false otherwise. - */ - bool checkMultiOscFailure( PciOscConnList & i_pciOscSwitchData ); - - /** - * @brief finds Rulechip associated with proc target. - * @param i_chipTgt target associated with proc Rulechip. - * @return Rulechip associated with proc target - */ - ExtensibleChip * findChip( TARGETING::TargetHandle_t i_chipTgt ); - - private: // Data - enum { CONTAINER_SIZE = 16 }; - - -}; - -inline PciOscSwitchDomain::PciOscSwitchDomain( DOMAIN_ID i_domainId ) : - RuleChipDomain( i_domainId, PciOscSwitchDomain::CONTAINER_SIZE ), - ExtensibleDomain( "PciOscSwitchDomain") -{} - -} // end namespace PRDF - -#endif /* prdfPciOscDomain_H */ - diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfPhbUtils.C b/src/usr/diag/prdf/common/plat/pegasus/prdfPhbUtils.C deleted file mode 100644 index d2cfe4882..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfPhbUtils.C +++ /dev/null @@ -1,207 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/diag/prdf/common/plat/pegasus/prdfPhbUtils.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/** @file prdfPhbUtils.C */ - -#include <prdfPhbUtils.H> - -#include <prdfPlatServices.H> -#include <prdfTrace.H> - -using namespace TARGETING; - -namespace PRDF -{ - -using namespace PlatServices; - -namespace Proc -{ - -int32_t getConfiguredPHB( TargetHandle_t i_procTrgt, uint32_t i_iopciIdx, - uint32_t i_clkIdx, TargetHandle_t & o_phbTrgt ) -{ - #define PRDF_FUNC "[Proc::getConfiguredPHB] " - - int32_t o_rc = SUCCESS; - - o_phbTrgt = NULL; - - // Reference PCI Express Controller Functional Spec - // (pe_P8spec_master104.pdf). Tables in chapter 6: IO Operation Modes - enum TableBounds - { - MAX_CONFIGS = 14, - MAX_FIRS = 3, - MAX_CLOCKS = 2, - - // Array index for the processor models. - MURANO_IDX = 0, - VENICE_IDX, - NAPLES_IDX, - MAX_MODELS, - }; - - enum TableValues - { - // These PHB enums must match the PHB position number. - PHB0 = 0, - PHB1, - PHB2, - PHB3, - - // The dSMP connections are not used but we will still list them in the - // table just in case the are needed later. - NONE = MAX_PHB_PER_PROC, - SMP0 = MAX_PHB_PER_PROC, - SMP1 = MAX_PHB_PER_PROC, - }; - - static const uint8_t table[MAX_MODELS][MAX_CONFIGS][MAX_FIRS][MAX_CLOCKS] = - { - { - //-------------------Murano------------------| - //--IOPCIFIR-0-||-IOPCIFIR-1--||-IOPCIFIR-2--| - //---A--|--B---||---A--|--B---||---A--|--B---| - { {PHB0, PHB0}, {PHB1,NONE}, {NONE, NONE} }, // 0x0 - { {PHB0, PHB0}, {PHB1,NONE}, {NONE, NONE} }, // 0x1 - { {PHB0, NONE}, {PHB1,NONE}, {NONE, NONE} }, // 0x2 - { {PHB0, PHB2}, {PHB1,NONE}, {NONE, NONE} }, // 0x3 - { {PHB0, SMP0}, {PHB1,NONE}, {NONE, NONE} }, // 0x4 - { {PHB0, SMP0}, {PHB1,NONE}, {NONE, NONE} }, // 0x5 - { {PHB1, PHB1}, {SMP1,NONE}, {NONE, NONE} }, // 0x6 - { {PHB1, PHB2}, {SMP1,NONE}, {NONE, NONE} }, // 0x7 - { {SMP1, SMP0}, {PHB1,NONE}, {NONE, NONE} }, // 0x8 - { {SMP1, SMP0}, {PHB1,NONE}, {NONE, NONE} }, // 0x9 - { {SMP1, PHB2}, {SMP0,NONE}, {NONE, NONE} }, // 0xA - { {PHB1, SMP0}, {SMP1,NONE}, {NONE, NONE} }, // 0xB - { {SMP1, PHB2}, {PHB1,NONE}, {NONE, NONE} }, // 0xC - }, - - { - //------------------Venice-------------------| - //--IOPCIFIR-0-||-IOPCIFIR-1--||-IOPCIFIR-2--| - //---A--|--B---||---A--|--B---||---A--|--B---| - { {PHB0, PHB0}, {PHB1, PHB1}, {NONE, NONE} }, // 0x0 - { {PHB0, PHB0}, {PHB1, PHB2}, {NONE, NONE} }, // 0x1 - { {PHB0, NONE}, {PHB1, PHB1}, {NONE, NONE} }, // 0x2 - { {PHB0, NONE}, {PHB1, PHB2}, {NONE, NONE} }, // 0x3 - { {PHB0, SMP0}, {PHB1, PHB1}, {NONE, NONE} }, // 0x4 - { {PHB0, SMP0}, {PHB1, PHB2}, {NONE, NONE} }, // 0x5 - { {SMP1, PHB0}, {PHB1, PHB1}, {NONE, NONE} }, // 0x6 - { {SMP1, PHB0}, {PHB1, PHB2}, {NONE, NONE} }, // 0x7 - { {SMP1, SMP0}, {PHB1, PHB1}, {NONE, NONE} }, // 0x8 - { {SMP1, SMP0}, {PHB1, PHB2}, {NONE, NONE} }, // 0x9 - { {SMP1, SMP0}, {PHB1, PHB2}, {NONE, NONE} }, // 0xA - { {SMP1, SMP0}, {PHB1, PHB2}, {NONE, NONE} }, // 0xB - { {SMP1, PHB0}, {PHB1, PHB2}, {NONE, NONE} }, // 0xC - }, - - { - //------------------Naples-------------------| - //--IOPCIFIR-0-||-IOPCIFIR-1--||-IOPCIFIR-2--| - //---A--|--B---||---A--|--B---||---A--|--B---| - { {PHB0, PHB0}, {PHB1, PHB1}, {PHB3, NONE} }, // 0x0 - { {PHB0, PHB0}, {PHB1, PHB2}, {PHB3, NONE} }, // 0x1 - { {PHB0, NONE}, {PHB1, PHB1}, {PHB3, NONE} }, // 0x2 - { {PHB0, NONE}, {PHB1, PHB2}, {PHB3, NONE} }, // 0x3 - { {PHB0, NONE}, {PHB1, PHB1}, {PHB3, NONE} }, // 0x4 - { {PHB0, NONE}, {PHB1, PHB2}, {PHB3, NONE} }, // 0x5 - { {NONE, PHB0}, {PHB1, PHB1}, {PHB3, NONE} }, // 0x6 - { {NONE, PHB0}, {PHB1, PHB2}, {PHB3, NONE} }, // 0x7 - { {NONE, NONE}, {PHB1, PHB1}, {PHB3, NONE} }, // 0x8 - { {NONE, NONE}, {PHB1, PHB2}, {PHB3, NONE} }, // 0x9 - { {NONE, NONE}, {PHB1, PHB2}, {PHB3, NONE} }, // 0xA - { {NONE, NONE}, {PHB1, PHB2}, {PHB3, NONE} }, // 0xB - { {NONE, PHB0}, {PHB1, PHB2}, {PHB3, NONE} }, // 0xC - }, - }; - - do - { - // Check parameters - if ( MAX_FIRS <= i_iopciIdx ) - { - PRDF_ERR( PRDF_FUNC "i_iopciIdx is unsupported: %d", i_iopciIdx ); - o_rc = FAIL; break; - } - - if ( MAX_CLOCKS <= i_clkIdx ) - { - PRDF_ERR( PRDF_FUNC "i_clkIdx is unsupported: %d", i_clkIdx ); - o_rc = FAIL; break; - } - - // Get the processor model and config table. - MODEL model = getProcModel( i_procTrgt ); - uint32_t modelIdx = MAX_MODELS; - switch ( model ) - { - case MODEL_MURANO: modelIdx = MURANO_IDX; break; - case MODEL_VENICE: modelIdx = VENICE_IDX; break; - case MODEL_NAPLES: modelIdx = NAPLES_IDX; break; - default: - PRDF_ERR( PRDF_FUNC "unsupported processor model: %d", model ); - o_rc = FAIL; - } - if ( SUCCESS != o_rc ) break; - - // Get the PHB configuration. - uint32_t phbConfig = getPhbConfig( i_procTrgt ); - if ( MAX_CONFIGS <= phbConfig ) - { - PRDF_ERR( PRDF_FUNC "unsupportd PHB config: %d", phbConfig ); - o_rc = FAIL; break; - } - - // Get the PHB target, if it exists. - uint8_t phbPos = table[modelIdx][phbConfig][i_iopciIdx][i_clkIdx]; - if ( MAX_PHB_PER_PROC > phbPos ) - { - o_phbTrgt = getConnectedChild( i_procTrgt, TYPE_PCI, phbPos ); - if ( NULL == o_phbTrgt ) // Target should exist. - { - PRDF_ERR( PRDF_FUNC "getConnectedChild(%d) failed", phbPos ); - o_rc = FAIL; break; - } - } - - } while (0); - - if ( SUCCESS != o_rc ) - { - PRDF_ERR( PRDF_FUNC "Failed: i_procTrgt=0x%08x i_iopciIdx=%d " - "i_clkIdx=%d", getHuid(i_procTrgt), i_iopciIdx, i_clkIdx ); - } - - return o_rc; - - #undef PRDF_FUNC -} - -} // end namespace Proc - -} // end namespace PRDF - diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfPhbUtils.H b/src/usr/diag/prdf/common/plat/pegasus/prdfPhbUtils.H deleted file mode 100644 index cec6a338f..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfPhbUtils.H +++ /dev/null @@ -1,57 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/diag/prdf/common/plat/pegasus/prdfPhbUtils.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -#ifndef PHB_CONFIG_H -#define PHB_CONFIG_H - -/** @file prdfPhbUtils.H - * @brief Utility functions to determine PHB Configuration. - */ - -#include <prdfPlatServices.H> - -namespace PRDF -{ - -namespace Proc -{ - -/** - * @brief Returns PHB target associated with given IOPCIFR and clock. - * @param i_procTrgt The target processor. - * @param i_iopciIdx IOPCIFIR instance number (0-2) - * @param i_clkIdx The target clock within the IOPCIFIR (0-1) - * @param o_phbTrgt NULL if the PHB does not exist. Otherwise the PHB target. - * @return NULL if no configured PHB found, otherwise the target PHB. - */ -int32_t getConfiguredPHB( TARGETING::TargetHandle_t i_procTrgt, - uint32_t i_iopciIdx, uint32_t i_clkIdx, - TARGETING::TargetHandle_t & o_phbTrgt ); - -} // end namespace Proc - -} // end namespace PRDF - -#endif // PHB_CONFIG_H diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfPlatUtil.C b/src/usr/diag/prdf/common/plat/pegasus/prdfPlatUtil.C deleted file mode 100644 index 315ecf326..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfPlatUtil.C +++ /dev/null @@ -1,79 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/diag/prdf/common/plat/pegasus/prdfPlatUtil.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/** @file prdfPlatUtil.C */ - -#include <prdfPlatServices.H> -#include <iipServiceDataCollector.h> - -using namespace TARGETING; - -namespace PRDF -{ - -using namespace PlatServices; -namespace PlatUtil -{ - -bool ignoreErrorForSapphire( STEP_CODE_DATA_STRUCT & i_stepcode ) -{ - bool ignoreError = false; - - // First of all ensure that we are not in AVP mode. Hypervisor becomes - // irrelevant in that case. - if( !isMfgAvpEnabled() && !isMfgHdatAvpEnabled() && !mfgMode() ) - { - if( isHyprConfigOpal() ) - { - // For an OPAL based system, analysis for certain errors is either - // not supported or shall be added later. We need to simply - // threshold and mask these errors. There should not be any service - // action. However, there are some scenarios to consider: - // 1. manufacturing or AVP mode - threshold and predictive callout - // 2. SP less system - mask error on first instance. - // 3. SP based Tuleta-L - mask error once threshold is met (say 32 - // per Day ). - - if( !isSpConfigFsp() ) - { - //Mask the error on first instance for FSP less systems. - i_stepcode.service_data->setFlag( - ServiceDataCollector::AT_THRESHOLD ); - } - - //Prevent predictive callout of the chip. - i_stepcode.service_data->clearServiceCall(); - - ignoreError = true; - } - } - - return ignoreError; -} - -} // end namespace PlatUtil - -} // end namespace PRDF - diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfPlatUtil.H b/src/usr/diag/prdf/common/plat/pegasus/prdfPlatUtil.H deleted file mode 100644 index a22f221c1..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfPlatUtil.H +++ /dev/null @@ -1,50 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/diag/prdf/common/plat/pegasus/prdfPlatUtil.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -#ifndef PRDF_PLATUTIL_H -#define PRDF_PLATUTIL_H - -/** - * @file prdfPlatUtil.H - * @brief Intended for util functions common between all platforms. - */ - -namespace PRDF -{ - -struct STEP_CODE_DATA_STRUCT; -namespace PlatUtil -{ - -/** - * @return True, if it is an OPAL based system in field environment, false - * otherwise. - */ -bool ignoreErrorForSapphire( STEP_CODE_DATA_STRUCT & i_stepcode ); - -} // namespace PlatUtil - -} // namespace PRDF -#endif diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfTOD.H b/src/usr/diag/prdf/common/plat/pegasus/prdfTOD.H deleted file mode 100755 index 38ad4dc5e..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfTOD.H +++ /dev/null @@ -1,54 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/diag/prdf/common/plat/pegasus/prdfTOD.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -#ifndef PRDFTOD_H -#define PRDFTOD_H - -namespace PRDF -{ - -/** @struct PrdfTodFaultData - * TOD Fault isolation information from a chip. - */ -struct PrdfTodFaultData -{ - TARGETING::TargetHandle_t source_chipHandle; - bool phyp_fault; - bool topo_fault[2]; // 0 is active, 1 is backup - bool topo_fault_clock[2]; - TARGETING::TargetHandle_t topo_fault_chip[2]; -}; - -int32_t prdfP7_TodCaptureRegisters(STEP_CODE_DATA_STRUCT & i_stepcode); -int32_t prdfP7_TodCleanUpErrors(STEP_CODE_DATA_STRUCT & i_stepcode); -int32_t prdfP7_TodCollectFaultDataSys(vector<PrdfTodFaultData> & o_faults, - STEP_CODE_DATA_STRUCT & i_stepcode); -int32_t prdfP7_TodCollectFaultDataChip(ExtensibleChip * i_chip, - vector<PrdfTodFaultData> & o_faults, - STEP_CODE_DATA_STRUCT & i_stepcode); - -} // end namespace PRDF - -#endif //PRDFTOD_H diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdf_plat_p8.mk b/src/usr/diag/prdf/common/plat/pegasus/prdf_plat_p8.mk deleted file mode 100644 index ebd4f5430..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/prdf_plat_p8.mk +++ /dev/null @@ -1,73 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/prdf_plat_p8.mk $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -# NOTE: PRD_SRC_PATH must be defined before including this file. - -################################################################################ -# Paths common to both FSP and Hostboot -################################################################################ - -prd_vpath += ${PRD_SRC_PATH}/common/plat/pegasus - -prd_incpath += ${PRD_SRC_PATH}/common/plat/pegasus - -################################################################################ -# Object files common to both FSP and Hostboot -################################################################################ - -# common/plat/pegasus/ (non-rule plugin related) -prd_obj += prdfCalloutUtil.o -prd_obj += prdfCenAddress.o -prd_obj += prdfCenDqBitmap.o -prd_obj += prdfCenMbaCaptureData.o -prd_obj += prdfCenMbaCeTable.o -prd_obj += prdfCenMbaRceTable.o -prd_obj += prdfCenMbaTdCtlr_common.o -prd_obj += prdfCenMbaThresholds_common.o -prd_obj += prdfCenMbaUeTable.o -prd_obj += prdfCenMemUtils.o -prd_obj += prdfCenSymbol.o -prd_obj += prdfFabricDomain.o -prd_obj += prdfFsiCapUtil.o -prd_obj += prdfLaneRepair.o -prd_obj += prdfLineDelete.o -prd_obj += prdfMemoryMru.o -prd_obj += prdfPciOscSwitchDomain.o -prd_obj += prdfPegasusConfigurator.o -prd_obj += prdfPllDomain.o -prd_obj += prdfPhbUtils.o -prd_obj += prdfPlatUtil.o - -# common/plat/pegasus/ (rule plugin related) -prd_rule_plugin += prdfCenMba.o -prd_rule_plugin += prdfCenMembuf.o -prd_rule_plugin += prdfCenPll.o -prd_rule_plugin += prdfP8Ex.o -prd_rule_plugin += prdfP8Mcs.o -prd_rule_plugin += prdfP8Pll.o -prd_rule_plugin += prdfP8PllPcie.o -prd_rule_plugin += prdfP8Proc.o -prd_rule_plugin += prdfPllUtils.o - |
