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| author | Zane Shelley <zshelle@us.ibm.com> | 2018-12-10 16:47:45 -0600 |
|---|---|---|
| committer | Zane C. Shelley <zshelle@us.ibm.com> | 2018-12-12 21:52:39 -0600 |
| commit | 229ade5d23e7ab14710f973aa8983b55538260d9 (patch) | |
| tree | ed3454d64c440f19e417f41f4e7855711c948eb2 /src/usr/diag/prdf/common/plat | |
| parent | 96251f9d6aa97432329fcc518e54f563f3c5960a (diff) | |
| download | talos-hostboot-229ade5d23e7ab14710f973aa8983b55538260d9.tar.gz talos-hostboot-229ade5d23e7ab14710f973aa8983b55538260d9.zip | |
PRD: PLL analysis support for Axone
Change-Id: Icbfc1e29e9e1503a9874f278517f415eff4f2c3d
RTC: 202545
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69635
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69700
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/usr/diag/prdf/common/plat')
| -rw-r--r-- | src/usr/diag/prdf/common/plat/p9/prdfP9Pll.C | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/src/usr/diag/prdf/common/plat/p9/prdfP9Pll.C b/src/usr/diag/prdf/common/plat/p9/prdfP9Pll.C index 80ce46823..dbea8e026 100644 --- a/src/usr/diag/prdf/common/plat/p9/prdfP9Pll.C +++ b/src/usr/diag/prdf/common/plat/p9/prdfP9Pll.C @@ -86,6 +86,7 @@ void getChpltList ( ExtensibleChip * i_chip, o_cfgRegStr = "PCI_CONFIG_REG"; break; case TYPE_MCBIST: + case TYPE_MC: o_errRegStr = "MC_ERROR_REG"; o_cfgRegStr = "MC_CONFIG_REG"; break; @@ -345,7 +346,8 @@ int32_t CheckErrorType( ExtensibleChip * i_chip, uint32_t & o_errType ) if (CheckChipletPll(i_chip, TYPE_PROC) || CheckChipletPll(i_chip, TYPE_XBUS) || CheckChipletPll(i_chip, TYPE_OBUS) || - CheckChipletPll(i_chip, TYPE_MCBIST)) + CheckChipletPll(i_chip, TYPE_MCBIST) || + CheckChipletPll(i_chip, TYPE_MC)) { o_errType |= SYS_PLL_UNLOCK; } @@ -364,6 +366,7 @@ int32_t CheckErrorType( ExtensibleChip * i_chip, uint32_t & o_errType ) } PRDF_PLUGIN_DEFINE_NS( nimbus_proc, Proc, CheckErrorType ); PRDF_PLUGIN_DEFINE_NS( cumulus_proc, Proc, CheckErrorType ); +PRDF_PLUGIN_DEFINE_NS( axone_proc, Proc, CheckErrorType ); /** * @brief Clear Chiplet PCB slave reg parity errors @@ -382,6 +385,7 @@ int32_t clearParityError( ExtensibleChip * i_chip, ClearChipletParityError(i_chip, TYPE_XBUS); ClearChipletParityError(i_chip, TYPE_OBUS); ClearChipletParityError(i_chip, TYPE_MCBIST); + ClearChipletParityError(i_chip, TYPE_MC); ClearChipletParityError(i_chip, TYPE_PEC); ClearChipletParityError(i_chip, TYPE_EQ); ClearChipletParityError(i_chip, TYPE_CORE); @@ -392,6 +396,7 @@ int32_t clearParityError( ExtensibleChip * i_chip, } PRDF_PLUGIN_DEFINE_NS( nimbus_proc, Proc, clearParityError ); PRDF_PLUGIN_DEFINE_NS( cumulus_proc, Proc, clearParityError ); +PRDF_PLUGIN_DEFINE_NS( axone_proc, Proc, clearParityError ); /** * @brief Query the PLL chip for a PLL error on P9 @@ -428,6 +433,7 @@ int32_t QueryPll( ExtensibleChip * i_chip, } PRDF_PLUGIN_DEFINE_NS( nimbus_proc, Proc, QueryPll ); PRDF_PLUGIN_DEFINE_NS( cumulus_proc, Proc, QueryPll ); +PRDF_PLUGIN_DEFINE_NS( axone_proc, Proc, QueryPll ); /** * @brief Clear the PLL error for P9 Plugin @@ -449,6 +455,7 @@ int32_t ClearPll( ExtensibleChip * i_chip, ClearChipletPll(i_chip, TYPE_XBUS); ClearChipletPll(i_chip, TYPE_OBUS); ClearChipletPll(i_chip, TYPE_MCBIST); + ClearChipletPll(i_chip, TYPE_MC); // Clear TP_LFIR SCAN_COMM_REGISTER_CLASS * TP_LFIRand = @@ -471,6 +478,7 @@ int32_t ClearPll( ExtensibleChip * i_chip, } PRDF_PLUGIN_DEFINE_NS( nimbus_proc, Proc, ClearPll ); PRDF_PLUGIN_DEFINE_NS( cumulus_proc, Proc, ClearPll ); +PRDF_PLUGIN_DEFINE_NS( axone_proc, Proc, ClearPll ); int32_t ClearMfPll( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & i_sc) @@ -504,6 +512,7 @@ int32_t ClearMfPll( ExtensibleChip * i_chip, } PRDF_PLUGIN_DEFINE_NS( nimbus_proc, Proc, ClearMfPll ); PRDF_PLUGIN_DEFINE_NS( cumulus_proc, Proc, ClearMfPll ); +PRDF_PLUGIN_DEFINE_NS( axone_proc, Proc, ClearMfPll ); /** * @brief Mask the PLL error for P9 Plugin @@ -524,6 +533,7 @@ int32_t MaskPll( ExtensibleChip * i_chip, MaskChipletPll(i_chip, TYPE_XBUS); MaskChipletPll(i_chip, TYPE_OBUS); MaskChipletPll(i_chip, TYPE_MCBIST); + MaskChipletPll(i_chip, TYPE_MC); } if (PCI_PLL_UNLOCK & i_errType) @@ -564,6 +574,7 @@ int32_t MaskPll( ExtensibleChip * i_chip, } PRDF_PLUGIN_DEFINE_NS( nimbus_proc, Proc, MaskPll ); PRDF_PLUGIN_DEFINE_NS( cumulus_proc, Proc, MaskPll ); +PRDF_PLUGIN_DEFINE_NS( axone_proc, Proc, MaskPll ); /** * @brief capture additional PLL FFDC @@ -599,6 +610,7 @@ int32_t capturePllFfdc( ExtensibleChip * i_chip, } PRDF_PLUGIN_DEFINE_NS( nimbus_proc, Proc, capturePllFfdc ); PRDF_PLUGIN_DEFINE_NS( cumulus_proc, Proc, capturePllFfdc ); +PRDF_PLUGIN_DEFINE_NS( axone_proc, Proc, capturePllFfdc ); } // end namespace Proc |
