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| author | Zane Shelley <zshelle@us.ibm.com> | 2018-04-20 15:26:25 -0500 |
|---|---|---|
| committer | Zane C. Shelley <zshelle@us.ibm.com> | 2018-04-27 12:14:37 -0400 |
| commit | ab3cba6aa16d2c55296d8f1debcd0f732f85c498 (patch) | |
| tree | 54ce53a69cda4639d5e9069e3a062fb26cfef017 /src/usr/diag/prdf/common/plat/cen/cen_centaur_regs.rule | |
| parent | 5170952d14e34b287fdf78d8a28f811ae4582f3d (diff) | |
| download | talos-hostboot-ab3cba6aa16d2c55296d8f1debcd0f732f85c498.tar.gz talos-hostboot-ab3cba6aa16d2c55296d8f1debcd0f732f85c498.zip | |
PRD: single bit analysis support for MBA target
Change-Id: I1991f107f6b56a168656cacc216217b87d117810
RTC: 187481
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57527
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57881
CI-Ready: Zane C. Shelley <zshelle@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/usr/diag/prdf/common/plat/cen/cen_centaur_regs.rule')
| -rw-r--r-- | src/usr/diag/prdf/common/plat/cen/cen_centaur_regs.rule | 30 |
1 files changed, 23 insertions, 7 deletions
diff --git a/src/usr/diag/prdf/common/plat/cen/cen_centaur_regs.rule b/src/usr/diag/prdf/common/plat/cen/cen_centaur_regs.rule index bef16d5a2..0fa0f5557 100644 --- a/src/usr/diag/prdf/common/plat/cen/cen_centaur_regs.rule +++ b/src/usr/diag/prdf/common/plat/cen/cen_centaur_regs.rule @@ -36,12 +36,24 @@ }; ############################################################################ - # Additional regs for CEN target MBSECCFIR + # Centaur chip MBSFIR + ############################################################################ + + register MBSFIR_MASK_OR + { + name "Centaur chip MBSFIR MASK atomic OR"; + scomaddr 0x02011405; + capture group never; + access write_only; + }; + + ############################################################################ + # Centaur chip MBSECCFIR 0 ############################################################################ register MBSECCFIR_0_AND { - name "Centaur chip MBSECCFIR_0 atomic AND"; + name "Centaur chip MBSECCFIR 0 atomic AND"; scomaddr 0x02011441; capture group never; access write_only; @@ -49,7 +61,7 @@ register MBSECCFIR_0_MASK_AND { - name "MBU.MBS.ECC01.MBECCFIR_MASK_AND"; + name "Centaur chip MBSECCFIR 0 MASK atomic AND"; scomaddr 0x02011444; capture group never; access write_only; @@ -57,15 +69,19 @@ register MBSECCFIR_0_MASK_OR { - name "MBU.MBS.ECC01.MBECCFIR_MASK_OR"; + name "Centaur chip MBSECCFIR 0 MASK atomic OR"; scomaddr 0x02011445; capture group never; access write_only; }; + ############################################################################ + # Centaur chip MBSECCFIR 0 + ############################################################################ + register MBSECCFIR_1_AND { - name "Centaur chip MBSECCFIR_1 atomic AND"; + name "Centaur chip MBSECCFIR 1 atomic AND"; scomaddr 0x02011481; capture group never; access write_only; @@ -73,7 +89,7 @@ register MBSECCFIR_1_MASK_AND { - name "MBU.MBS.ECC23.MBECCFIR_MASK_AND"; + name "Centaur chip MBSECCFIR 1 MASK atomic AND"; scomaddr 0x02011484; capture group never; access write_only; @@ -81,7 +97,7 @@ register MBSECCFIR_1_MASK_OR { - name "MBU.MBS.ECC23.MBECCFIR_MASK_OR"; + name "Centaur chip MBSECCFIR 1 MASK atomic OR"; scomaddr 0x02011485; capture group never; access write_only; |
