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authorMatt Derksen <v2cibmd@us.ibm.com>2016-11-07 09:53:56 -0600
committerDaniel M. Crowell <dcrowell@us.ibm.com>2016-11-28 17:00:43 -0500
commit4a1d5adf82c8309d387b6b7fccb46f78224b41fe (patch)
tree0628ea877aad47e6505de9ddc03b101373ff52a3 /src/usr/devtree
parent2f193c6b29f2c3bcbdeff7fd8c590fb12ddfaa4c (diff)
downloadtalos-hostboot-4a1d5adf82c8309d387b6b7fccb46f78224b41fe.tar.gz
talos-hostboot-4a1d5adf82c8309d387b6b7fccb46f78224b41fe.zip
Remove old PROC_PCIE_LANE_EQUALIZATION attribute
Change-Id: I2a0d8831a797a227724089887525e8efe89122d1 RTC:160417 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32327 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/devtree')
-rw-r--r--src/usr/devtree/bld_devtree.C6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/usr/devtree/bld_devtree.C b/src/usr/devtree/bld_devtree.C
index ee2b15505..ca4e2b60f 100644
--- a/src/usr/devtree/bld_devtree.C
+++ b/src/usr/devtree/bld_devtree.C
@@ -802,9 +802,6 @@ void bld_xscom_node(devTree * i_dt, dtOffset_t & i_parentNode,
/*PCIE*/
uint8_t l_phbActive =
i_pProc->getAttr<TARGETING::ATTR_PROC_PCIE_PHB_ACTIVE>();
- TARGETING::ATTR_PROC_PCIE_LANE_EQUALIZATION_type l_laneEq = {{0}};
- assert(i_pProc->tryGetAttr<TARGETING::ATTR_PROC_PCIE_LANE_EQUALIZATION>(
- l_laneEq));
TRACFCOMP( g_trac_devtree, "Chip %X PHB Active mask %X",
i_chipid, l_phbActive);
@@ -831,9 +828,6 @@ void bld_xscom_node(devTree * i_dt, dtOffset_t & i_parentNode,
i_dt->addPropertyCells32(pcieNode, "reg", pcie_prop, 6);
i_dt->addPropertyCell32(pcieNode, "ibm,phb-index", l_phb);
i_dt->addProperty(pcieNode, "ibm,use-ab-detect");
- i_dt->addPropertyCells32(pcieNode, "ibm,lane-eq",
- reinterpret_cast<uint32_t*>(l_laneEq[l_phb]),
- (sizeof(l_laneEq[l_phb])/sizeof(uint32_t)));
}
/*I2C Masters*/
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