Code optimizations.

   - Reduce DCBZ and ICBI calls in memory copy and init functions.
   - Reduce strlen calls in trace.
   - Set thread to low priority while waiting on in-kernel barrier.

Change-Id: Ic9c23b1e26797ff393e5862819830de60554747e
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/871
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

1 files changed, 8 insertions, 9 deletions

diff --git a/src/lib/syscall_mm.C b/src/lib/syscall_mm.C
index 282b32c68..129f304da 100644
--- a/src/lib/syscall_mm.C
+++ b/src/lib/syscall_mm.C
@@ -55,21 +55,20 @@ void mm_icache_invalidate(void * i_addr, size_t i_cpu_word_count)
     uint64_t addr = (uint64_t)i_addr  & ~0x7ull;
     uint64_t * dest = (uint64_t*)addr;
 
-    for(size_t i = 0; i < i_cpu_word_count; ++i)
+    for(size_t i = 0; i < i_cpu_word_count; i += getCacheLineWords())
     {
         dcbst(dest);
-        ++dest;
+        dest += getCacheLineWords();
     }
 
     lwsync();
 
-    dest = (uint64_t*)addr;
-    for(size_t i = 0; i < i_cpu_word_count; ++i)
-    {
-        icbi(dest);
-        ++dest;
-    }
-
+    // According to core design team we only need to do a single icbi,
+    // since the i-cache is kept coherent with the d-cache.  The single
+    // icbi invalidates the "scoreboard" in the core which, in combination
+    // with the isync, causes the core to go back out to l2-cache for any
+    // instructions past this.
+    icbi(reinterpret_cast<void*>(addr));
     isync();
 }