P9 PSIHB Base Interrupt Support

This change includes the following:
   - Kernel Updates to handle hypervisor interrupt vector
   - Interrupt Resource Provider changes to setup and handle
     LSI Based interrupts
   - Kernel updates to handle modified interrupt flow for
     LSI Based interrupts
   - Attribute updates for Scom BAR Registers

Change-Id: If63f246a0090ab8c81c3fa8ac3ab6871a0af2e31
RTC:137561
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/20692
Tested-by: Jenkins Server
Tested-by: FSP CI Jenkins
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

5 files changed, 36 insertions, 22 deletions

diff --git a/src/kernel/exception.C b/src/kernel/exception.C
index 5c16d46cd..686d3012c 100644
--- a/src/kernel/exception.C
+++ b/src/kernel/exception.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2010,2015                        */
+/* Contributors Listed Below - COPYRIGHT 2010,2016                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
diff --git a/src/kernel/intmsghandler.C b/src/kernel/intmsghandler.C
index f203439be..10c1dcfd8 100644
--- a/src/kernel/intmsghandler.C
+++ b/src/kernel/intmsghandler.C
@@ -5,7 +5,9 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2011,2014              */
+/* Contributors Listed Below - COPYRIGHT 2011,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
 /*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
@@ -76,26 +78,22 @@ void InterruptMsgHdlr::handleInterrupt()
 
     if( cv_ipc_base_address != 0 )
     {
-        uint64_t xirrAddress = cv_ipc_base_address;
-
-        xirrAddress += mmio_offset(pir); // Add offset for this cpu
-        xirrAddress += XIRR_ADDR_OFFSET; // Add offset for XIRR register
+        uint64_t ackHypeInt2RegAddress = cv_ipc_base_address;
+        ackHypeInt2RegAddress += ACK_HYPERVISOR_INT_REG_OFFSET;
 
         // Ignore HRMOR setting
-        xirrAddress |= 0x8000000000000000ul;
-
-        uint32_t xirr = 0;
-        printkd ("XirrAddr %lx\n",xirrAddress);
+        ackHypeInt2RegAddress |= 0x8000000000000000ul;
+        uint16_t ackHypeInt2Reg = 0;
 
         // Reading this register acknowledges the interrupt and deactivates the
         // external interrupt signal to the processor. The XIRR is now locked
         // and can't be pre-empted by a "more favored" interrupt.
         // This is a cache-inhibited load from hypervisor state.
-        // lwzcix      BOP1,Ref_G0,BOP2
-        asm volatile("lwzcix %0, 0, %1"
-                     : "=r" (xirr)           // output, %0
-                     : "r" (xirrAddress)     // input,  %1
-                     : );                    // no impacts
+        // lhzcix      BOP1,Ref_G0,BOP2
+        asm volatile("lhzcix %0, 0, %1"
+                     : "=r" (ackHypeInt2Reg)           // output, %0
+                     : "r" (ackHypeInt2RegAddress)     // input,  %1
+                     : );                              // no impacts
 
         if(cv_instance)
         {
@@ -103,8 +101,9 @@ void InterruptMsgHdlr::handleInterrupt()
 
             //sendMessage needs a unique key, otherwise it
             //drops messages.  PIR is not unique enough, make
-            //it (xirr<<32) | PIR
-            uint64_t l_data0 = pir | (static_cast<uint64_t>(xirr) <<32);
+            //it (ackHypInt2Reg<<32) | PIR
+            uint64_t l_data0 =
+                             pir | (static_cast<uint64_t>(ackHypeInt2Reg) <<32);
             cv_instance->sendMessage(MSG_INTR_EXTERN,
                                      reinterpret_cast<void*>(l_data0),
                                      NULL,
@@ -115,7 +114,6 @@ void InterruptMsgHdlr::handleInterrupt()
     else
     {
         printk("InterrurptMsgHdlr got called before IPC was setup\n");
-
         // The INTR mmio base address is not yet available via the attributes.
         // If we get here during an MPIPL then the BAR value could be read
         // from the ICP BAR SCOM register, however, since this value will
@@ -142,9 +140,8 @@ void InterruptMsgHdlr::handleInterrupt()
         // There should not be any more interrupts until an eoi is sent
         // by writing the xirr back with the value read.
 
-        printk("XIRR @ %lx = %x\n",xirrAddress,xirr);
-
         //If this is an IPI -- clean it up
+        //TODO RTC 137564
         if((xirr & 0x00FFFFFF) == INTERPROC_XISR)
         {
             uint64_t mfrrAddress =
diff --git a/src/kernel/msghandler.C b/src/kernel/msghandler.C
index 5a3beefac..cb051eb88 100644
--- a/src/kernel/msghandler.C
+++ b/src/kernel/msghandler.C
@@ -5,7 +5,9 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2011,2014              */
+/* Contributors Listed Below - COPYRIGHT 2011,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
 /*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
diff --git a/src/kernel/start.S b/src/kernel/start.S
index 86c2d1c18..740f961e8 100644
--- a/src/kernel/start.S
+++ b/src/kernel/start.S
@@ -208,6 +208,7 @@ UNIMPL_INTERRUPT_STUB(hype_data_storage, 0xE00)
 UNIMPL_INTERRUPT_STUB(hype_inst_storage, 0xE20)
 STD_INTERRUPT_STUB(hype_emu_assist, 0xE40)
 UNIMPL_INTERRUPT_STUB(hype_maint, 0xE60)
+STD_INTERRUPT_STUB(hypervisor_external, 0xEA0)
 UNIMPL_INTERRUPT_STUB(perf_monitor, 0xF00)
 UNIMPL_INTERRUPT_STUB(vector_unavail, 0xF20)
 UNIMPL_INTERRUPT_STUB(vsx_unavail, 0xF40)
@@ -698,6 +699,20 @@ intvect_system_reset_external:
 
     b intvect_external
 
+    ;// @fn intvect_hypervisor_external
+    ;// Handle hypervisor external interrupt
+    ;//    This function moves the hypervisor external interrupt regs
+    ;//    into the external interrupt regs and then branches to the
+    ;//    external interrupt handler
+intvect_hypervisor_external:
+    mtsprg1 r1          ;// Save off R1 temporarily.
+    mfspr r1, HSRR0     ;// Move HSRR0 -> SRR0.
+    mtsrr0 r1
+    mfspr r1, HSRR1     ;// Move HSRR1 -> SRR1.
+    mtsrr1 r1
+    mfsprg1 r1          ;// Restore R1 and use external interrupt handler
+    b intvect_external
+
     ;// @fn system_call_fast_path
     ;// Handle fast path system calls.
     ;//         0x800 = HMER read (HMER -> r3).
diff --git a/src/kernel/syscall.C b/src/kernel/syscall.C
index 92907c3df..fe59ea0c3 100644
--- a/src/kernel/syscall.C
+++ b/src/kernel/syscall.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2010,2015                        */
+/* Contributors Listed Below - COPYRIGHT 2010,2016                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */