Set "high" thread priority as 2 rather than 3.

    The Power processor has instructions of the form 'or a,a,a'
    that allow code to change the priority of a hw-thread relative
    to the others.  We initially used 'or 1,1,1' as low priority
    and 'or 3,3,3' as high priority.  This is used in, for instance,
    spinlocks to reduce the priority of a hw-thread while waiting
    for another thread to perform an activity.

    This code originally came from HAL.  In reading the Power ISA
    closer I realized that 'or 3,3,3' has no effect when in
    user-space code, which means that a spinlock-like effect in
    user code is going to end up with the thread stuck at low
    priority until the next context switch.  To prevent this we
    are going to change from 1/3 to 1/2 as the priority levels.

Change-Id: I60ee866cde37499106f5e1e1d68a0b5ddeedf403
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1569
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

1 files changed, 4 insertions, 4 deletions

diff --git a/src/kernel/start.S b/src/kernel/start.S
index d7d4ec202..a97fd484f 100644
--- a/src/kernel/start.S
+++ b/src/kernel/start.S
@@ -50,7 +50,7 @@
 .global _start
 _start:
     ;// Set thread priority high.
-    or 3,3,3
+    or 2,2,2
 
     ;// Clear MSR[TA] (bit 63).
     mfmsr r2
@@ -146,7 +146,7 @@ finished_relocate:
 
 #define STD_INTERRUPT_NOADDR(name) \
     intvect_##name: \
-	or 3,3,3; /* Ensure thread priority is high. */ \
+	or 2,2,2; /* Ensure thread priority is high. */ \
 	mtsprg1 r1; /* Save GPR1 */ \
 	    ;/* Retrieve processing address for interrupt. */ \
 	lis r1, intvect_##name##_finish_save@h; \
@@ -299,7 +299,7 @@ _other_thread_spinlock:
     b 1b
 ;// Now released by primary thread.
 _other_thread_spinlock_complete:
-    or 3,3,3 ;// Raise thread priority.
+    or 2,2,2 ;// Raise thread priority.
     isync
     ;// Get CPU object from thread ID.
     mfspr r1, PIR
@@ -574,7 +574,7 @@ intvect_system_reset:
     ;//         - IPI wake-up from winkle of slave core.
 
     ;// Raise priority to high.
-    or 3,3,3
+    or 2,2,2
 
     ;// Free up two registers temporarily.
     mtsprg0 r1