diff options
| author | Andrew Geissler <andrewg@us.ibm.com> | 2016-07-26 14:21:15 -0500 |
|---|---|---|
| committer | William G. Hoffa <wghoffa@us.ibm.com> | 2016-08-16 15:43:07 -0400 |
| commit | 025298b52002867f1e3516ba9810fd4642262980 (patch) | |
| tree | 70ef20aabd7e1bb0d727e7f94d72ac74e522e62d /src/kernel/misc.C | |
| parent | 5d57720970f8c8ffcefee7bfa5f9ec24f141501d (diff) | |
| download | talos-hostboot-025298b52002867f1e3516ba9810fd4642262980.tar.gz talos-hostboot-025298b52002867f1e3516ba9810fd4642262980.zip | |
Updates for new scratch registers in P9
P9 moves us from 8 scratch registers to 4. This commit handles
this change and also adds the base support for partial cache.
Change-Id: Ibe050c663744285dd3e77850649236a669dadbd6
RTC: 150923
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27462
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/kernel/misc.C')
| -rw-r--r-- | src/kernel/misc.C | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/src/kernel/misc.C b/src/kernel/misc.C index 972a30a19..f7b6a0cc1 100644 --- a/src/kernel/misc.C +++ b/src/kernel/misc.C @@ -593,13 +593,17 @@ namespace KernelMisc case CORE_POWER8_MURANO: case CORE_POWER8_VENICE: case CORE_POWER8_NAPLES: + l_scratch_addr = l_scratch_addr + 0x40; + break; case CORE_POWER9_NIMBUS: case CORE_POWER9_CUMULUS: case CORE_UNKNOWN: - l_scratch_addr = l_scratch_addr + 0x40; - break; + default: + // See EX07.EC.CC.PCC0.COMMON.SPR_COMMON.SCOMC in scomdef for + // info on this offset - MODE_CX_SCOMC: 0000xxx = SCRATCH xx SPR + // It's 0 for P9 so just pass through scratch reg offset + break; } - writeScratchReg(l_scratch_addr, data); }; |
