summaryrefslogtreecommitdiffstats
path: root/src/include
diff options
context:
space:
mode:
authorIlya Smirnov <ismirno@us.ibm.com>2019-11-15 16:57:52 -0600
committerDaniel M Crowell <dcrowell@us.ibm.com>2019-11-18 08:14:14 -0600
commit1cee7cd499df2521027dacef1f03375688db935c (patch)
tree49838417f4137e39f7ca0ef8ab0853e330f0a127 /src/include
parent6d6b8ced5f998e51cadb247b0c79ec5252804f7e (diff)
downloadtalos-hostboot-1cee7cd499df2521027dacef1f03375688db935c.tar.gz
talos-hostboot-1cee7cd499df2521027dacef1f03375688db935c.zip
Fix UVBWLIST SBE Chip Op
The address where SBE is to populate the ultravisor white/blacklist is to be put in Mbox reg1, which means that the register needs to be masked in the command we're sending. Before this change, only Mbox reg0 was masked, and SBE was not getting the correct address at which to populate the UVBWLIST. This change masks Mbox Reg 1 so that SBE can receive the correct address for the UVBWLIST. Change-Id: I841db74dc407f51c14f005b9ccd457d5641ffa7e Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/87102 Reviewed-by: Nicholas E Bofferding <bofferdn@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/usr/sbeio/sbe_psudd.H2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/usr/sbeio/sbe_psudd.H b/src/include/usr/sbeio/sbe_psudd.H
index 3a21ad122..688c9086b 100644
--- a/src/include/usr/sbeio/sbe_psudd.H
+++ b/src/include/usr/sbeio/sbe_psudd.H
@@ -338,7 +338,7 @@ class SbePsu
*/
enum psuSecurityListBinDumpNonReservedMsgs
{
- SBE_SECURITY_LIST_BIN_DUMP_REQ_USED_REGS = 0x01,
+ SBE_SECURITY_LIST_BIN_DUMP_REQ_USED_REGS = 0x03,
SBE_SECURITY_LIST_BIN_DUMP_RSP_USED_REGS = 0x01,
};
OpenPOWER on IntegriCloud