diff options
| author | Brian Bakke <bbakke@us.ibm.com> | 2017-11-17 10:51:24 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-11-30 09:33:28 -0500 |
| commit | 3a88f18bc7386abaaceedca9b327806d85734f67 (patch) | |
| tree | c4351bac24ee26d90c977a0bd1d766217f8817e2 /src/include | |
| parent | c5c12e6e0ae9160e15f7ff07d123cb9033103947 (diff) | |
| download | talos-hostboot-3a88f18bc7386abaaceedca9b327806d85734f67.tar.gz talos-hostboot-3a88f18bc7386abaaceedca9b327806d85734f67.zip | |
Enable ATTN prior to OPAL handoff
Change-Id: Iadfded90c09b149948348ee462ab34f9c2431982
RTC: 182134
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49865
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/arch/ppc.H | 7 | ||||
| -rw-r--r-- | src/include/kernel/syscalls.H | 4 | ||||
| -rw-r--r-- | src/include/sys/misc.h | 7 | ||||
| -rw-r--r-- | src/include/usr/isteps/istep_reasoncodes.H | 1 |
4 files changed, 18 insertions, 1 deletions
diff --git a/src/include/arch/ppc.H b/src/include/arch/ppc.H index a4c3afbed..36b514f04 100644 --- a/src/include/arch/ppc.H +++ b/src/include/arch/ppc.H @@ -364,6 +364,13 @@ inline uint64_t getHID() } ALWAYS_INLINE +inline void setHID(uint64_t _hid) +{ + register uint64_t hid = _hid; + asm volatile("mtspr 1008, %0; isync" :: "r" (hid)); +} + +ALWAYS_INLINE inline size_t getCacheLineBytes() { return 128; diff --git a/src/include/kernel/syscalls.H b/src/include/kernel/syscalls.H index 951f55fac..35c6a5fe8 100644 --- a/src/include/kernel/syscalls.H +++ b/src/include/kernel/syscalls.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2010,2014 */ +/* Contributors Listed Below - COPYRIGHT 2010,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -93,6 +93,8 @@ namespace Systemcalls MISC_CPUSTARTCORE, /** cpu_spr_value() */ MISC_CPUSPRVALUE, + /** cpu_spr_set() */ + MISC_CPUSPRSET, /** cpu_nap() - Hidden syscall */ MISC_CPUNAP, /** cpu_master_winkle() */ diff --git a/src/include/sys/misc.h b/src/include/sys/misc.h index 8255aa3b5..6b57e7e4e 100644 --- a/src/include/sys/misc.h +++ b/src/include/sys/misc.h @@ -202,6 +202,13 @@ enum CpuSprNames */ uint64_t cpu_spr_value(CpuSprNames spr); +/** @fn cpu_spr_set + * @brief Writes an SPR. + * + * @return rc: true = success, false = unsupported SPR. + */ +uint64_t cpu_spr_set(CpuSprNames spr, uint64_t newValue ); + /** @fn cpu_master_winkle * @brief Winkle the master core so runtime SLW image can be applied. * diff --git a/src/include/usr/isteps/istep_reasoncodes.H b/src/include/usr/isteps/istep_reasoncodes.H index 5895c11ee..1b661f17c 100644 --- a/src/include/usr/isteps/istep_reasoncodes.H +++ b/src/include/usr/isteps/istep_reasoncodes.H @@ -125,6 +125,7 @@ namespace ISTEP RC_RETURNED_FFDC = ISTEP_COMP_ID | 0x34, RC_P9N_DD1_NOT_SUPPORTED = ISTEP_COMP_ID | 0x35, RC_PREVENT_REBOOT_IN_MFG_TERM_MODE = ISTEP_COMP_ID | 0x36, + RC_FAILED_WRITE_SPR = ISTEP_COMP_ID | 0x37, }; }; |
