Support Verifying and Moving PAYLOAD and HDAT when TCEs are Enabled

This commit makes changes in istep 16 to set up temporary memory
regions that the FSP will use to DMA-via-TCEs the PAYLOAD and HDAT
sections into memory in istep 20.  Then in istep 21 Hostboot will
verify and move these sections to the final memory locations.

Change-Id: I3c9e026a8e2c3c40008364c4229915b4a661d0fe
RTC:181900
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50624
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com>
Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 34 insertions, 16 deletions

diff --git a/src/include/usr/isteps/istep_reasoncodes.H b/src/include/usr/isteps/istep_reasoncodes.H
index 1b661f17c..9f75bcfe3 100644
--- a/src/include/usr/isteps/istep_reasoncodes.H
+++ b/src/include/usr/isteps/istep_reasoncodes.H
@@ -63,6 +63,7 @@ namespace ISTEP
         MOD_SBE_GET_FFDC_HANDLER                          = 0x1C,
         MOD_SET_IPL_PARMS                                 = 0x1D,
         MOD_OCC_XSTOP_HANDLER                             = 0x1E,
+        MOD_VERIFY_AND_MOVE_PAYLOAD                       = 0x1F,
     };
 
     /**
diff --git a/src/include/usr/util/utiltce.H b/src/include/usr/util/utiltce.H
index 0aaffacf1..b0aaf48ae 100644
--- a/src/include/usr/util/utiltce.H
+++ b/src/include/usr/util/utiltce.H
@@ -50,10 +50,11 @@ namespace TCE
  *                     Size must be less than (512K * PAGESIZE) or will fail.
  *                     Assert if not greater than zero.
  *
- * @param[out] o_startingToken - Starting Entry into the table.
- *                               (This is an offset into the array based on the
- *                                TCE index * PAGESIZE.  Each TCE entry maps to
- *                                a pagesize of memory)
+ * @param[out] o_startingToken - Key to the Starting Entry into the table.
+ *                               This is an offset into the array based on the
+ *                               TCE Index * PAGESIZE.
+ *                               FSP uses the token as a DMA Address.
+ *                               Each TCE entry maps to a pagesize of memory.
  *
  * Note:  First time this is called will cause TCE Table to be created and
  *        the Processors to be setup to point at the TCE Table
@@ -97,7 +98,7 @@ errlHndl_t utilDisableTces(void);
 /******************************************************/
 
 /**
- * @brief Responsible for Setting up TCEs for PAYLOAD
+ * @brief Responsible for Setting up TCEs for PAYLOAD, including HDAT
  *
  * @return errlHndl_t - Return Error Handle if failed
  *
@@ -105,7 +106,7 @@ errlHndl_t utilDisableTces(void);
 errlHndl_t utilSetupPayloadTces(void);
 
 /**
- * @brief Responsible for closing the TCEs for PAYLOAD
+ * @brief Responsible for closing the TCEs for PAYLOAD, including HDAT
  *
  * @return errlHndl_t - Return Error Handle if failed
  *
diff --git a/src/include/usr/vmmconst.h b/src/include/usr/vmmconst.h
index ed773da09..32be069d6 100644
--- a/src/include/usr/vmmconst.h
+++ b/src/include/usr/vmmconst.h
@@ -206,7 +206,7 @@ enum BlockPriority
  *  Need to add (ATTR_HB_HRMOR_NODAL_BASE * hbinstance_num) to this
  *  address to get the physical address
  */
-#define VMM_INTERNODE_PRESERVED_MEMORY_ADDR (96 * MEGABYTE)
+#define VMM_INTERNODE_PRESERVED_MEMORY_ADDR (120 * MEGABYTE)
 
 /**
  * Test Constants
@@ -222,6 +222,31 @@ enum BlockPriority
  * Physical Memory Constants
  */
 
+/** Layout
+ * 0MB-4MB: reserved/open
+ * 4MB-87MB:    MCL_ADDR, MCL_TMP_ADDR, HDAT_TMP_ADDR
+ * 88MB-120MB:  TCE Table (needs to be 4-byte aligned)
+ * 120MB:       VMM_INTERNODE_PRESERVED_MEMORY_ADDR (see above)
+ * 128MB-256MB: See HB_HRMOR info above (with HOMERs, OCC, etc)
+ */
+
+/** Two memory locations for MCL processing **/
+// Note: 2 spaces needed so the MCL can be initialized without wiping out PHYP
+// Location for the MCL itself to sit in.
+#define MCL_ADDR (4*MEGABYTE)
+#define MCL_SIZE (16*KILOBYTE)
+// Location for PHYP to be loaded into and reused for all Master Container Lids
+// Verification is done in a temporary, non-secure area of mainstore memory,
+// then relocated to its final, secure location in mainstore.
+#define MCL_TMP_ADDR (MCL_ADDR + MCL_SIZE)
+#define MCL_TMP_SIZE ( (64 * MEGABYTE) + PAGESIZE )
+
+// Location for HDAT to be loaded into via TCEs by FSP
+// Verification is done in a temporary, non-secure area of mainstore memory,
+// then relocated to its final, secure location in mainstore.
+#define HDAT_TMP_ADDR (MCL_TMP_ADDR + MCL_TMP_SIZE)
+#define HDAT_TMP_SIZE (16 * MEGABYTE)
+
 /** Physical memory location of the TCE Table */
 /** - needs to be aligned on 4MB boundary     */
 #define TCE_TABLE_ADDR  (88*MEGABYTE)
@@ -235,15 +260,6 @@ enum BlockPriority
 
 #define UNSECURE_MEM_REGION_SIZE_TEST (1*KILOBYTE)
 
-/** Two memory locations for MCL processing **/
-// Note: 2 spaces needed so the MCL can be initialized without wiping out PHYP
-// Location for the MCL itself to sit in.
-#define MCL_ADDR (20*MEGABYTE)
-#define MCL_SIZE (16*KILOBYTE)
-// Location for PHYP to be loaded into and reused for all Master Container Lids
-// Verification is done in the temp space and then loaded into mainstore memory
-#define MCL_TMP_ADDR (MCL_ADDR + MCL_SIZE)
-#define MCL_TMP_SIZE ( (64 * MEGABYTE) + PAGESIZE )
 
 /** PreVerifiedLidMgr test space */
 #define PREVERLIDMGR_TEST_ADDR  (512*MEGABYTE)