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| author | Marty Gloff <mgloff@us.ibm.com> | 2017-07-26 11:27:45 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-08-09 13:34:40 -0400 |
| commit | 7c53973849de64198de72fcdd680e1424832a4e0 (patch) | |
| tree | 4a4b8daa6f29cc1fc75025b24b4e2010756b0600 /src/include/usr/sbe | |
| parent | e276a9bbce83803dca7fb399c5b69a174b4ade4b (diff) | |
| download | talos-hostboot-7c53973849de64198de72fcdd680e1424832a4e0.tar.gz talos-hostboot-7c53973849de64198de72fcdd680e1424832a4e0.zip | |
SBE update plan for OpenPOWER
We need to have a new way to handle the SBE update flow for OpenPOWER.
Update the SBE code one side at a time to avoid a scenario where a bad
code load bricks the system. Start by loading side 0 (primary), then
re-IPL, and finally load side 1 (backup). A new config flag is used,
SBE_UPDATE_CONSECUTIVE.
Change-Id: Icf18ebec173c2f42fe200fb9cd547b9ebc580acc
RTC: 176755
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43893
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/include/usr/sbe')
| -rw-r--r-- | src/include/usr/sbe/sbe_update.H | 16 | ||||
| -rw-r--r-- | src/include/usr/sbe/sbereasoncodes.H | 1 |
2 files changed, 17 insertions, 0 deletions
diff --git a/src/include/usr/sbe/sbe_update.H b/src/include/usr/sbe/sbe_update.H index a831df5d8..25d7448af 100644 --- a/src/include/usr/sbe/sbe_update.H +++ b/src/include/usr/sbe/sbe_update.H @@ -115,7 +115,11 @@ namespace SBE const uint8_t REIPL_SEEPROM_1_VALUE = 0x40; // Situation constants -- bits numbered from left to right +#ifndef CONFIG_SBE_UPDATE_CONSECUTIVE const uint8_t SITUATION_ALL_BITS_MASK = 0xE0; +#else + const uint8_t SITUATION_ALL_BITS_MASK = 0x0E; +#endif // Bit 0: current side is permanent (=0) or temp (=1) const uint8_t SITUATION_CUR_IS_PERM = 0x00; const uint8_t SITUATION_CUR_IS_TEMP = 0x80; @@ -128,6 +132,18 @@ namespace SBE const uint8_t SITUATION_ALT_IS_CLEAN = 0x00; const uint8_t SITUATION_ALT_IS_DIRTY = 0x20; + // Bit 4: side 0 clean (=0) or dirty (=1) + const uint8_t SITUATION_SIDE_0_CLEAN = 0x00; + const uint8_t SITUATION_SIDE_0_DIRTY = 0x08; + + // Bit 5: side 1 clean (=0) or dirty (=1) + const uint8_t SITUATION_SIDE_1_CLEAN = 0x00; + const uint8_t SITUATION_SIDE_1_DIRTY = 0x04; + + // Bit 6: boot side is side 0 (=0) or side 1 (=1) + const uint8_t SITUATION_BOOT_SIDE_0 = 0x00; + const uint8_t SITUATION_BOOT_SIDE_1 = 0x02; + // For mbox messages to FSP const uint32_t MSG_IPL_DUE_TO_SBE_UPDATE = 0x40000012; const uint32_t MSG_IPL_MASTER_CORE = 0x40000005; diff --git a/src/include/usr/sbe/sbereasoncodes.H b/src/include/usr/sbe/sbereasoncodes.H index 57c21ce1d..4dee3c6ea 100644 --- a/src/include/usr/sbe/sbereasoncodes.H +++ b/src/include/usr/sbe/sbereasoncodes.H @@ -105,6 +105,7 @@ enum sbeReasonCode ERROR_FROM_XIP_FIND = SBE_COMP_ID | 0x19, SBE_MISMATCHED_HW_KEY_HASH = SBE_COMP_ID | 0x1A, SBE_UPDATE_DURING_MPIPL = SBE_COMP_ID | 0x1B, + SBE_BOOT_SIDE_DIRTY_BAD_PATH = SBE_COMP_ID | 0x1C, }; }; // end SBE |
