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| author | CamVan Nguyen <ctnguyen@us.ibm.com> | 2012-08-15 16:01:22 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2012-08-16 13:54:43 -0500 |
| commit | 1681d8660846d58472bb717917ec383b49d69faf (patch) | |
| tree | 9d5449b8aab65fc06bd7c4967db7953be12b8116 /src/include/usr/isteps/istep13list.H | |
| parent | 3afee991ccf79716b952706edfdf128b16154810 (diff) | |
| download | talos-hostboot-1681d8660846d58472bb717917ec383b49d69faf.tar.gz talos-hostboot-1681d8660846d58472bb717917ec383b49d69faf.zip | |
Updates to IPL flow v1.08
Change-Id: I496b5739f625dd5111a5cdd144e89dcd43ad1986
RTC: 45712
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1533
Tested-by: Jenkins Server
Reviewed-by: Van H. Lee <vanlee@us.ibm.com>
Reviewed-by: MIKE J. JONES <mjjones@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/include/usr/isteps/istep13list.H')
| -rw-r--r-- | src/include/usr/isteps/istep13list.H | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/src/include/usr/isteps/istep13list.H b/src/include/usr/isteps/istep13list.H index 870427d8d..fe982d0e9 100644 --- a/src/include/usr/isteps/istep13list.H +++ b/src/include/usr/isteps/istep13list.H @@ -28,28 +28,28 @@ * @file istep13list.H * * IStep 13 Step 13 DRAM Training - * IPL FLow Doc v0.99 (02/10/12) + * IPL FLow Doc v1.08 (08/13/12) * - * 13.1 host_disable_vddr - * : Disable VDDR on CanContinue loops - * 13.2 mc_pll_setup - * : Setup PLL for MBAs - * 13.3 mem_startclocks - * : Start clocks on MBAs - * 13.4 host_enable_vddr - * : Enable the VDDR3 Voltage Rail - * 13.5 mss_scominit - * : Perform scom inits to MC and PHY - * 13.6 mss_ddr_phy_reset - * : Soft reset of DDR PHY macros - * 13.7 mss_draminit - * : Dram initialize - * 13.8 mss_draminit_training - * : Dram training - * 13.9 mss_draminit_trainadv - * : Advanced dram training - * 13.10 mss_draminit_mc - * : Hand off control to MC + * 13.1 host_disable_vddr + * : Disable VDDR on CanContinue loops + * 13.2 mem_pll_setup + * : Setup PLL for MBAs + * 13.3 mem_startclocks + * : Start clocks on MBAs + * 13.4 host_enable_vddr + * : Enable the VDDR3 Voltage Rail + * 13.5 mss_scominit + * : Perform scom inits to MC and PHY + * 13.6 mss_ddr_phy_reset + * : Soft reset of DDR PHY macros + * 13.7 mss_draminit + * : Dram initialize + * 13.8 mss_draminit_training + * : Dram training + * 13.9 mss_draminit_trainadv + * : Advanced dram training + * 13.10 mss_draminit_mc + * : Hand off control to MC * * ***************************************************************** * THIS FILE WAS GENERATED ON 2012-02-27:2142 @@ -88,8 +88,8 @@ const TaskInfo g_istep13[] = { } }, { - ISTEPNAME(13,02,"mc_pll_setup"), - DRAM_TRAINING::call_mc_pll_setup, + ISTEPNAME(13,02,"mem_pll_setup"), + DRAM_TRAINING::call_mem_pll_setup, { START_FN, EXT_IMAGE, |
