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authorDan Crowell <dcrowell@us.ibm.com>2015-02-11 11:04:51 -0600
committerA. Patrick Williams III <iawillia@us.ibm.com>2015-02-18 15:06:42 -0600
commit79ea7abf6d31c146c680d39b9f3ae007e434a573 (patch)
tree359506a770bde98bb88930c71723b17371ec5937 /src/include/usr/fsi
parent84023756531d9c48d2e4939326f4048f2dadbe28 (diff)
downloadtalos-hostboot-79ea7abf6d31c146c680d39b9f3ae007e434a573.tar.gz
talos-hostboot-79ea7abf6d31c146c680d39b9f3ae007e434a573.zip
New interfaces to get FSI and PNOR info for Xstop code
Added new external interfaces to retrieve information about the FSI topology and the PNOR characteristics in order to enable the checkstop analysis code that runs on the OCC. RTC: 108820 Change-Id: Ibbe9bca8eee4c8ac86006b1ad881bd8b2c3b8280 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/15726 Tested-by: Jenkins Server Reviewed-by: Zane Shelley <zshelle@us.ibm.com> Reviewed-by: William H. Schwartz <whs@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/include/usr/fsi')
-rw-r--r--src/include/usr/fsi/fsiif.H7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/include/usr/fsi/fsiif.H b/src/include/usr/fsi/fsiif.H
index 756dbb7b0..5ab2e449e 100644
--- a/src/include/usr/fsi/fsiif.H
+++ b/src/include/usr/fsi/fsiif.H
@@ -5,7 +5,9 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* COPYRIGHT International Business Machines Corp. 2011,2014 */
+/* Contributors Listed Below - COPYRIGHT 2011,2015 */
+/* [+] International Business Machines Corp. */
+/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
@@ -109,10 +111,11 @@ struct FsiLinkInfo_t
uint8_t link; ///< Which link is this chip hanging off of
uint8_t cascade; ///< Slave cascade position
uint8_t mPort; ///< FSI Master port (0=A,1=B)
+ uint32_t baseAddr; ///< Base FSI Address for this chip
FsiLinkInfo_t() :
master(NULL), type(TARGETING::FSI_MASTER_TYPE_NO_MASTER),
- link(0xFF), cascade(0), mPort(0)
+ link(0xFF), cascade(0), mPort(0), baseAddr(UINT32_MAX)
{};
};
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