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| author | Dean Sanner <dsanner@us.ibm.com> | 2018-03-07 08:23:19 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-03-08 21:25:27 -0500 |
| commit | d6f9a2206311d4b7e67462215e736253d9c6a5b1 (patch) | |
| tree | a42536a33ed83a58ceb896b40b160e94ac31eb85 /src/include/arch | |
| parent | b98f4c6b59fa881b95d1022333ffafb2f927427b (diff) | |
| download | talos-hostboot-d6f9a2206311d4b7e67462215e736253d9c6a5b1.tar.gz talos-hostboot-d6f9a2206311d4b7e67462215e736253d9c6a5b1.zip | |
Force 25G Nvlink speed on P9N DD2.1
Normally the OBUS PLL frequency is controlled via the MRW,
however P9NDD2.1 has a bug that forces the OBus freq to 25G.
Desire is to allow the MRW to set to a higher freq, but MRW
doesn't have entries for per chip EC, so this commit just
handles down leveling P9N DD2.1 (as a chip restriction)
Change-Id: I542f7810a69facb919cc3889ae3ed5ca0a233445
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55195
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
CI-Ready: Dean Sanner <dsanner@us.ibm.com>
CI-Ready: Corey V. Swenson <cswenson@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: ERICH J. HAUPTLI <ejhauptl@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/include/arch')
| -rw-r--r-- | src/include/arch/pvrformat.H | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/src/include/arch/pvrformat.H b/src/include/arch/pvrformat.H index 2a2616dd4..3e233c50d 100644 --- a/src/include/arch/pvrformat.H +++ b/src/include/arch/pvrformat.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -115,6 +115,8 @@ struct PVR_t { NIMBUS_DD1_MASK = 0x00FF2F0F, IS_NIMBUS_DD1 = 0x004E0100, + IS_NIMBUS_DD20 = 0x004E0200, + IS_NIMBUS_DD21 = 0x004E0201, // Field: chipType NIMBUS_CHIP = 0, @@ -138,6 +140,22 @@ struct PVR_t inline bool isNimbusDD1() { return ((word & NIMBUS_DD1_MASK) == IS_NIMBUS_DD1); } + + /** + * @brief Check if DD2.0 + * @return true if DD2.0, else false + */ + inline bool isNimbusDD20() { + return ((word & NIMBUS_DD1_MASK) == IS_NIMBUS_DD20); + } + + /** + * @brief Check if DD2.1 + * @return true if DD2.1, else false + */ + inline bool isNimbusDD21() { + return ((word & NIMBUS_DD1_MASK) == IS_NIMBUS_DD21); + } }; #endif //_PVRFORMAT_H |
