Update Core Scratch Reg 6 with L3 vs Mainstore for FSP to query

RTC:64829
Change-Id: Ic8e7983f6838b79c359c4cee2647b7676493cb1e
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3564
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

1 files changed, 13 insertions, 0 deletions

diff --git a/src/include/arch/ppc.H b/src/include/arch/ppc.H
index ebb1f0f02..46c78d754 100644
--- a/src/include/arch/ppc.H
+++ b/src/include/arch/ppc.H
@@ -317,6 +317,19 @@ inline size_t getCacheLineWords()
     return getCacheLineBytes() / sizeof(uint64_t);
 }
 
+ALWAYS_INLINE
+inline void writeScratchReg(uint64_t _scratch_addr, uint64_t _data)
+{
+    register uint64_t scratch_addr = _scratch_addr;
+    register uint64_t data = _data;
+
+    asm volatile("mtspr 276, %0\n"
+                 "isync\n"
+                 "mtspr 277, %1"
+                 :: "r" (scratch_addr), "r" (data));
+
+}
+
 /** @brief  This is a special assembler instruction that is a nop on
  *  regular hardware, but has special meaning to Simics.  Code that
  *  executes this instruction in Simics will cause a "hap," a