cpu_spr_value syscall for SLW image build.

    Task 44887

Change-Id: If87b6e80b974bb4cbff13844d8a3f055a17282d2
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1378
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Mark W. Wenning <wenning@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

1 files changed, 46 insertions, 22 deletions

diff --git a/src/include/arch/ppc.H b/src/include/arch/ppc.H
index 7807b5743..9ba62ff9e 100644
--- a/src/include/arch/ppc.H
+++ b/src/include/arch/ppc.H
@@ -1,25 +1,26 @@
-//  IBM_PROLOG_BEGIN_TAG
-//  This is an automatically generated prolog.
-//
-//  $Source: src/include/arch/ppc.H $
-//
-//  IBM CONFIDENTIAL
-//
-//  COPYRIGHT International Business Machines Corp. 2011
-//
-//  p1
-//
-//  Object Code Only (OCO) source materials
-//  Licensed Internal Code Source Materials
-//  IBM HostBoot Licensed Internal Code
-//
-//  The source code for this program is not published or other-
-//  wise divested of its trade secrets, irrespective of what has
-//  been deposited with the U.S. Copyright Office.
-//
-//  Origin: 30
-//
-//  IBM_PROLOG_END
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/include/arch/ppc.H $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2011-2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
 #ifndef __KERNEL_PPCARCH_H
 #define __KERNEL_PPCARCH_H
 
@@ -213,6 +214,29 @@ inline uint64_t getHEIR()
 }
 
 ALWAYS_INLINE
+inline uint64_t getLPCR()
+{
+    register uint64_t lpcr = 0;
+    asm volatile("mfspr %0, 318" : "=r" (lpcr));
+    return lpcr;
+}
+
+ALWAYS_INLINE
+inline void setLPCR(uint64_t _lpcr)
+{
+    register uint64_t lpcr = _lpcr;
+    asm volatile("mtspr 318, %0; isync" :: "r" (lpcr));
+}
+
+ALWAYS_INLINE
+inline uint64_t getHRMOR()
+{
+    register uint64_t hrmor = 0;
+    asm volatile("mfspr %0, 313" : "=r" (hrmor));
+    return hrmor;
+}
+
+ALWAYS_INLINE
 inline void setThreadPriorityLow()
 {
     asm volatile("or 1,1,1");