diff options
| author | Stephen Glancy <sglancy@us.ibm.com> | 2019-08-06 13:04:44 -0400 |
|---|---|---|
| committer | Christian R Geddes <crgeddes@us.ibm.com> | 2019-08-12 08:36:10 -0500 |
| commit | cfad3552a96071e7e0ea912e9cfa351cdc707d6e (patch) | |
| tree | fb46c4295382e106141ed7634ee6466d6d60f882 /src/import | |
| parent | 4b5c78b95f25d054ad9ed80d9f1ac95b7dc056fe (diff) | |
| download | talos-hostboot-cfad3552a96071e7e0ea912e9cfa351cdc707d6e.tar.gz talos-hostboot-cfad3552a96071e7e0ea912e9cfa351cdc707d6e.zip | |
Fixes maintenance pattern load bug
Explorer and Nimbus have different locations within
the buffers for the maintenance patterns. This commit
fixes a bug where only the Nimbus locations were used.
Change-Id: Id8f617191b1ae9a4b09b893a1507d299f240c50f
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81774
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81915
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import')
4 files changed, 11 insertions, 24 deletions
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H index fd587a502..631a3c930 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H @@ -601,6 +601,10 @@ class mcbistTraits< mss::mc_type::EXPLORER, fapi2::TARGET_TYPE_MEM_PORT> static constexpr uint64_t XLTATE1 = EXPLR_MCBIST_MBXLT1; static constexpr uint64_t XLTATE2 = EXPLR_MCBIST_MBXLT2; + // Maintenance data location within the array + static constexpr uint64_t MAINT_DATA_INDEX_START = 0b000000000; + static constexpr uint64_t MAINT_DATA_INDEX_END = 0b000001000; + enum { // Register field constants diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist_traits.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist_traits.H index 9add5ceb8..2a576acc8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist_traits.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist_traits.H @@ -589,6 +589,10 @@ class mcbistTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA> static constexpr uint64_t XLTATE1 = MCA_MBA_MCP0XLT1; static constexpr uint64_t XLTATE2 = MCA_MBA_MCP0XLT2; + // Maintenance data location within the array + static constexpr uint64_t MAINT_DATA_INDEX_START = 0b111110000; + static constexpr uint64_t MAINT_DATA_INDEX_END = 0b111111000; + enum { // Register field constants diff --git a/src/import/generic/memory/lib/utils/mcbist/gen_mss_mcbist.H b/src/import/generic/memory/lib/utils/mcbist/gen_mss_mcbist.H index f18aacccf..32f1d79c3 100644 --- a/src/import/generic/memory/lib/utils/mcbist/gen_mss_mcbist.H +++ b/src/import/generic/memory/lib/utils/mcbist/gen_mss_mcbist.H @@ -3009,7 +3009,7 @@ fapi2::ReturnCode load_maint_pattern( const fapi2::Target<T>& i_target, const pa // set ecc mode bit on l_aacr .template writeBit<PT::RMW_WRT_BUFFER_SEL>(mss::states::OFF) - .template insertFromRight<PT::RMW_WRT_ADDRESS, PT::RMW_WRT_ADDRESS_LEN>(mss::mcbist::rmw_address::DW0) + .template insertFromRight<PT::RMW_WRT_ADDRESS, PT::RMW_WRT_ADDRESS_LEN>(PT::MAINT_DATA_INDEX_START) .template writeBit<PT::RMW_WRT_AUTOINC>(mss::states::ON) .template writeBit<PT::RMW_WRT_ECCGEN>(mss::states::ON); @@ -3021,7 +3021,7 @@ fapi2::ReturnCode load_maint_pattern( const fapi2::Target<T>& i_target, const pa for (const auto& p : l_ports) { - l_aacr.template insertFromRight<PT::RMW_WRT_ADDRESS, PT::RMW_WRT_ADDRESS_LEN>(mss::mcbist::rmw_address::DW0); + l_aacr.template insertFromRight<PT::RMW_WRT_ADDRESS, PT::RMW_WRT_ADDRESS_LEN>(PT::MAINT_DATA_INDEX_START); for (auto l_num_writes = 0; l_num_writes < 2; ++l_num_writes) { @@ -3049,7 +3049,7 @@ fapi2::ReturnCode load_maint_pattern( const fapi2::Target<T>& i_target, const pa FAPI_TRY( fapi2::putScom(p, PT::RMW_WRT_BUF_ECC_REG, 0) ); } - l_aacr.template insertFromRight<PT::RMW_WRT_ADDRESS, PT::RMW_WRT_ADDRESS_LEN>(mss::mcbist::rmw_address::DW8); + l_aacr.template insertFromRight<PT::RMW_WRT_ADDRESS, PT::RMW_WRT_ADDRESS_LEN>(PT::MAINT_DATA_INDEX_END); } } diff --git a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H index 1b916c902..2a80655c6 100644 --- a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H +++ b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H @@ -397,27 +397,6 @@ enum broadcast_timebase TB_COUNT_128 = 0b1111111, }; -enum rmw_address -{ - // 32B block addresses into the maint portion of the rmw buffer - DW0 = 0b111110000, - DW1 = 0b111110001, - DW2 = 0b111110010, - DW3 = 0b111110011, - DW4 = 0b111110100, - DW5 = 0b111110101, - DW6 = 0b111110110, - DW7 = 0b111110111, - DW8 = 0b111111000, - DW9 = 0b111111001, - DWA = 0b111111010, - DWB = 0b111111011, - DWC = 0b111111100, - DWD = 0b111111101, - DWE = 0b111111110, - DWF = 0b111111111, -}; - enum data_rotate_mode { // MCBIST data rotate modes refer to register MCBDRCR bits 0:3 |
