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authorMark Pizzutillo <Mark.Pizzutillo@ibm.com>2019-10-02 18:08:02 -0400
committerDaniel M Crowell <dcrowell@us.ibm.com>2019-10-08 11:17:27 -0500
commit104c2dc5963a11e6b0d15888705eeb6c18a4c314 (patch)
treea49d6278f4d924dce74e29e94c110c4ba24da36a /src/import
parentc349ba997ee75adb76762c073f11e79c301e5a8e (diff)
downloadtalos-hostboot-104c2dc5963a11e6b0d15888705eeb6c18a4c314.tar.gz
talos-hostboot-104c2dc5963a11e6b0d15888705eeb6c18a4c314.zip
Disable & clear PMIC status codes in beginning of pmic_enable
Change-Id: I64b025443395c842f68dbaa1fb58909a4695f31a Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/84680 Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/84792 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import')
-rw-r--r--src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_common_utils.C22
-rw-r--r--src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_common_utils.H8
-rw-r--r--src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.C35
-rw-r--r--src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.H8
-rw-r--r--src/import/chips/ocmb/common/procedures/hwp/pmic/pmic_enable.C3
5 files changed, 76 insertions, 0 deletions
diff --git a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_common_utils.C b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_common_utils.C
index 06487ffbd..fe5e54c0d 100644
--- a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_common_utils.C
+++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_common_utils.C
@@ -296,6 +296,28 @@ fapi_try_exit:
}
///
+/// @brief Clear PMIC status registers
+///
+/// @param[in] i_pmic_target PMIC to clear
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code
+///
+fapi2::ReturnCode clear(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_pmic_target)
+{
+ using REGS = pmicRegs<mss::pmic::product::JEDEC_COMPLIANT>;
+ using FIELDS = pmicFields<mss::pmic::product::JEDEC_COMPLIANT>;
+
+ fapi2::buffer<uint8_t> l_reg_contents;
+ FAPI_TRY(mss::pmic::i2c::reg_read_reverse_buffer(i_pmic_target, REGS::R14, l_reg_contents));
+
+ // Write to clear
+ l_reg_contents.setBit<FIELDS::R14_GLOBAL_CLEAR_STATUS>();
+ FAPI_TRY(mss::pmic::i2c::reg_write_reverse_buffer(i_pmic_target, REGS::R14, l_reg_contents));
+
+fapi_try_exit:
+ return fapi2::current_err;
+}
+
+///
/// @brief Check an individual set of PMIC status codes
///
/// @param[in] i_pmic_target PMIC target
diff --git a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_common_utils.H b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_common_utils.H
index 4b73203cd..b2a7c60d7 100644
--- a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_common_utils.H
+++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_common_utils.H
@@ -301,6 +301,14 @@ fapi2::ReturnCode check_all_pmics(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CH
fapi2::ReturnCode check_pmic(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_pmic_target, bool& o_error);
///
+/// @brief Clear PMIC status registers
+///
+/// @param[in] i_pmic_target PMIC to clear
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code
+///
+fapi2::ReturnCode clear(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_pmic_target);
+
+///
/// @brief Check the IDT specific status codes
///
/// @param[in] i_pmic_target PMIC target
diff --git a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.C b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.C
index d77805122..70951fb89 100644
--- a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.C
+++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.C
@@ -521,6 +521,41 @@ fapi_try_exit:
}
///
+/// @brief Disable PMICs and clear status bits in preparation for enable
+///
+/// @param[in] i_pmics vector of PMIC targets
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code
+///
+fapi2::ReturnCode disable_and_reset_pmics(const std::vector<fapi2::Target<fapi2::TARGET_TYPE_PMIC>>& i_pmics)
+{
+ using REGS = pmicRegs<mss::pmic::product::JEDEC_COMPLIANT>;
+ using FIELDS = pmicFields<mss::pmic::product::JEDEC_COMPLIANT>;
+
+ for (const auto& l_pmic : i_pmics)
+ {
+ // Make sure PMIC is alive
+ FAPI_TRY(mss::pmic::poll_for_pbulk_good(l_pmic));
+
+ // First, disable
+ {
+ fapi2::buffer<uint8_t> l_reg_contents;
+
+ // Redundant clearBit, but just so it's clear what we're doing
+ l_reg_contents.clearBit<FIELDS::R32_VR_ENABLE>();
+
+ FAPI_TRY(mss::pmic::i2c::reg_write_reverse_buffer(l_pmic, REGS::R32, l_reg_contents));
+ }
+
+ // Now that it's disabled, let's clear the status bits so errors don't hang over into the next enable
+ {
+ FAPI_TRY(mss::pmic::status::clear(l_pmic));
+ }
+ }
+
+fapi_try_exit:
+ return fapi2::current_err;
+}
+///
/// @brief Enable PMIC for SPD mode
///
/// @param[in] i_pmics vector of PMICs sorted by mss::index
diff --git a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.H b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.H
index 680bb8f9b..9220993b5 100644
--- a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.H
+++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.H
@@ -765,6 +765,14 @@ fapi2::ReturnCode enable_chip_1U_2U(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>
const uint16_t i_vendor_id);
///
+/// @brief Disable PMICs and clear status bits in preparation for enable
+///
+/// @param[in] i_pmics vector of PMIC targets
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code
+///
+fapi2::ReturnCode disable_and_reset_pmics(const std::vector<fapi2::Target<fapi2::TARGET_TYPE_PMIC>>& i_pmics);
+
+///
/// @brief Enable PMIC for SPD mode
///
/// @param[in] i_pmics vector of PMICs sorted by mss::index
diff --git a/src/import/chips/ocmb/common/procedures/hwp/pmic/pmic_enable.C b/src/import/chips/ocmb/common/procedures/hwp/pmic/pmic_enable.C
index bec758f65..eaab19cd5 100644
--- a/src/import/chips/ocmb/common/procedures/hwp/pmic/pmic_enable.C
+++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/pmic_enable.C
@@ -63,6 +63,9 @@ extern "C"
return fapi2::FAPI2_RC_SUCCESS;
}
+ // Disable PMICs and clear status bits so we are starting at a known off state
+ FAPI_TRY(mss::pmic::disable_and_reset_pmics(l_pmics));
+
// // If we're enabling via internal settings, we can just run VR ENABLE down the line
if (i_mode == mss::pmic::enable_mode::MANUAL)
{
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