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| author | Brian Vanderpool <vanderp@us.ibm.com> | 2018-01-18 07:35:14 -0600 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-01-22 16:17:36 -0500 |
| commit | 0c093d57ac2a3b209b79be4fca749017aefbfefb (patch) | |
| tree | 74f67444748975830c499d1c8f241ec0bde0ab96 /src/import | |
| parent | d52d893e3aa25f405713200f372e53057382f2d1 (diff) | |
| download | talos-hostboot-0c093d57ac2a3b209b79be4fca749017aefbfefb.tar.gz talos-hostboot-0c093d57ac2a3b209b79be4fca749017aefbfefb.zip | |
PM - use OJCFG[6] instead of OCR[10] to halt the 405 before reset
Key_Cronus_Test=PM_REGRESS
Change-Id: I8c0714a09def9f424dbe69fdae0e14f55e442fda
CQ: HW434437
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52162
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52172
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.C | 39 |
1 files changed, 20 insertions, 19 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.C index 1f5ce85fc..fc2895942 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -83,7 +83,7 @@ enum DELAY_VALUE // OCR Register Bits static const uint32_t OCB_PIB_OCR_CORE_RESET_BIT = 0; -static const uint32_t OCB_PIB_OCR_OCR_DBG_HALT_BIT = 10; +static const uint32_t OCB_PIB_OCR_OCR_DBG_HALT_BIT = 10; // HW434437 this bit isn't connected // OCC JTAG Register Bits static const uint32_t JTG_PIB_OJCFG_DBG_HALT_BIT = 6; @@ -331,13 +331,13 @@ fapi2::ReturnCode p9_pm_occ_control case p9occ_ctrl::PPC405_HALT_OFF: FAPI_TRY(fapi2::putScom(i_target, PU_JTG_PIB_OJCFG_AND, - ~BIT(OCB_PIB_OCR_OCR_DBG_HALT_BIT))); + ~BIT(JTG_PIB_OJCFG_DBG_HALT_BIT))); break; case p9occ_ctrl::PPC405_HALT_ON: FAPI_TRY(fapi2::putScom(i_target, PU_JTG_PIB_OJCFG_OR, - BIT(OCB_PIB_OCR_OCR_DBG_HALT_BIT))); + BIT(JTG_PIB_OJCFG_DBG_HALT_BIT))); break; case p9occ_ctrl::PPC405_RESET_SEQUENCE: @@ -379,8 +379,8 @@ fapi2::ReturnCode p9_pm_occ_control // Halt the 405 and verify that it is halted FAPI_TRY(fapi2::putScom(i_target, - PU_OCB_PIB_OCR_OR, - BIT(OCB_PIB_OCR_OCR_DBG_HALT_BIT))); + PU_JTG_PIB_OJCFG_OR, + BIT(JTG_PIB_OJCFG_DBG_HALT_BIT))); FAPI_TRY(fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY)); @@ -402,8 +402,8 @@ fapi2::ReturnCode p9_pm_occ_control PU_OCB_PIB_OCR_OR, BIT(OCB_PIB_OCR_CORE_RESET_BIT))); FAPI_TRY(fapi2::putScom(i_target, - PU_OCB_PIB_OCR_CLEAR, - BIT(OCB_PIB_OCR_OCR_DBG_HALT_BIT))); + PU_JTG_PIB_OJCFG_AND, + ~BIT(JTG_PIB_OJCFG_DBG_HALT_BIT))); FAPI_TRY(fapi2::putScom(i_target, PERV_TP_OCC_SCOM_OCCLFIR_AND, ~BIT(OCCLFIR_PPC405_DBGSTOPACK_BIT))); @@ -415,21 +415,22 @@ fapi2::ReturnCode p9_pm_occ_control case p9occ_ctrl::PPC405_START: - // Check the JTAG Halt bit is off as the the PPC405 won't actually start - // if this bit is on (controlled by RiscWatch) - FAPI_TRY(fapi2::getScom(i_target, PU_JTG_PIB_OJCFG, l_jtagcfg)); - - FAPI_ASSERT (!(l_jtagcfg.getBit<JTG_PIB_OJCFG_DBG_HALT_BIT>()), - fapi2::OCC_CONTROL_NONSTART_DUE_TO_RISCWATCH() - .set_JTAGCFG(l_jtagcfg) - .set_TARGET(i_target), - "OCC will not start as the JTAG halt from RiscWatch is currently set"); + // Need to remove this due to HW434437 + // // Check the JTAG Halt bit is off as the the PPC405 won't actually start + // // if this bit is on (controlled by RiscWatch) + // FAPI_TRY(fapi2::getScom(i_target, PU_JTG_PIB_OJCFG, l_jtagcfg)); + // + // FAPI_ASSERT (!(l_jtagcfg.getBit<JTG_PIB_OJCFG_DBG_HALT_BIT>()), + // fapi2::OCC_CONTROL_NONSTART_DUE_TO_RISCWATCH() + // .set_JTAGCFG(l_jtagcfg) + // .set_TARGET(i_target), + // "OCC will not start as the JTAG halt from RiscWatch is currently set"); FAPI_INF("Starting the PPC405"); // Clear the halt bit FAPI_TRY(fapi2::putScom(i_target, - PU_OCB_PIB_OCR_CLEAR, - BIT(OCB_PIB_OCR_OCR_DBG_HALT_BIT))); + PU_JTG_PIB_OJCFG_AND, + ~BIT(JTG_PIB_OJCFG_DBG_HALT_BIT))); // Set the reset bit FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCR_OR, |
