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| author | Joe McGill <jmcgill@us.ibm.com> | 2017-11-25 11:59:18 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-03-13 10:20:47 -0400 |
| commit | f20b37d483c4bcd7d587132c590d7cf48240670d (patch) | |
| tree | b31794d98b420ab68781f9181a30435cd7e02c07 /src/import | |
| parent | 55b4dac7353b677dc6e120042dec1648b89ac942 (diff) | |
| download | talos-hostboot-f20b37d483c4bcd7d587132c590d7cf48240670d.tar.gz talos-hostboot-f20b37d483c4bcd7d587132c590d7cf48240670d.zip | |
remove NV iovalid assertion from FW and add scan inits to resolve glsmux xstate
p9_sbe_chiplet_reset
remove deassertion of OBUS clk async reset, shift to
p9_sbe_startclock_chiplets
p9_sbe_startclock_chiplets
conditionally remove workaround (assert iovalid, clock, deassert iovalid)
instituted to flush DL glmux select pipeline, these will be set via scan
for supported chips
deassert OBUS clk async reset
p9_chiplet_scominit
remove assertion of NV iovalid from HB
p9.npu.scan.initfile
alter flush state of NVDL glsmux select pipe latches to 0b10
p9.obus.scan.initfile
alter flush state of IOO PHY logic to enable lane clocks
clear RX_LANE_ANA_PDWN
clear RX_CLKDIST_PDWN
set RX_IREF_PDWN_B
Change-Id: I3ae74efba822aa4fa5dba2cca9d4f25fb21415ba
Original-Change-Id: Ib9d4bf18a181ed1cf55eaf92e1486c494757d657
CQ: HW404391
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50027
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55596
CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index a99b3ac8f..f9893ef3c 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -5671,4 +5671,47 @@ </chipEcFeature> </attribute> <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW404391_SCAN</id>> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Nimbus DD2.1+: Workaround glxmux xstate issue by adjusting scan flush + state of selected latches in NVDL and PHY logic + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x21</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW404391_SCOM</id>> + <targetType>TARGET_TYPE_PROC_CHIP,TARGET_TYPE_PROC_CHIP</targetType> + <description> + Nimbus DD2.0 + Cumulus: Workaround glxmux xstate issue by applying SCOM + sequence + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> </attributes> |
