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authorSangeetha T S <sangeet2@in.ibm.com>2016-04-21 00:20:19 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2016-06-10 15:12:55 -0400
commitb9c4c1a515fea41bdb28809e0cb5d8fb801145c5 (patch)
tree644f0f8694733a1cf3612498bef2692a7650bf0e /src/import
parentf1d5c51ab1ef52f2898be22b88e63fef177db204 (diff)
downloadtalos-hostboot-b9c4c1a515fea41bdb28809e0cb5d8fb801145c5.tar.gz
talos-hostboot-b9c4c1a515fea41bdb28809e0cb5d8fb801145c5.zip
p9_pm_ppm_firinit & p9_pm_cme_firinit L2 delivery
Change-Id: I1531d77ad38f8a6a6525247e8e048c6d3232a7af Original-Change-Id: I6ff8d8d714419939b41a1a01e7ebafa339f3c9e0 RTC:136790 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23524 Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25644 Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import')
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.C247
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.H69
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.mk20
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_pm_ppm_firinit.C198
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_pm_ppm_firinit.H70
5 files changed, 525 insertions, 79 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.C
new file mode 100644
index 000000000..0f08f231d
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.C
@@ -0,0 +1,247 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.C $ */
+/* */
+/* IBM CONFIDENTIAL */
+/* */
+/* EKB Project */
+/* */
+/* COPYRIGHT 2016 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* The source code for this program is not published or otherwise */
+/* divested of its trade secrets, irrespective of what has been */
+/* deposited with the U.S. Copyright Office. */
+/* */
+/* IBM_PROLOG_END_TAG */
+///
+/// @file p9_pm_cme_firinit.C
+/// @brief Configures the CME FIRs, Mask & Actions
+///
+// *HWP HW Owner: Amit Kumar <akumar3@us.ibm.com>
+// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com>
+// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team: PM
+// *HWP Level: 2
+// *HWP Consumed by: FSP:HS
+
+/// High-level procedure flow:
+/// \verbatim
+/// if reset:
+/// loop over all functional chiplets {
+/// Mask all bits of FIR
+/// }
+/// else if init:
+/// loop over all functional chiplets {
+/// Establish the mask/action bits for the following settings:
+/// 1) Checkstop
+/// 2) Malf Alert
+/// 3) Recoverable Attention
+/// 4) Recoverable Interrupt
+/// }
+///
+/// Procedure Prereq:
+/// o System clocks are running
+/// \endverbatim
+
+// ----------------------------------------------------------------------
+// Includes
+// ----------------------------------------------------------------------
+#include <p9_pm_cme_firinit.H>
+
+// ----------------------------------------------------------------------
+// Constant Definitions
+// ----------------------------------------------------------------------
+
+enum CME_FIRS
+{
+ PPE_INT_ERR, // 0
+ PPE_EXT_ERR, // 1
+ PPE_PROG_ERR, // 2
+ PPE_BRKPT_ERR, // 3
+ PPE_WATCHDOG, // 4
+ PPE_HALT, // 5
+ PPE_DBGTRG, // 6
+ CME_SRAM_UE, // 7
+ CME_SRAM_CE, // 8
+ BCE_ERR, // 9
+ SRAM_SCRUB_ERR, // 10
+ CME_SPARE_11, // 11
+ CME_SPARE_12, // 12
+ C0_iVRM_DPOUT, // 13
+ C1_iVRM_DPOUT, // 14
+ CACHE_iVRM_DPOUT, // 15
+ EXTRM_DROOP_ERR, // 16
+ LARGE_DROOP_ERR, // 17
+ SMALL_DROOP_ERR, // 18
+ UNEXP_DROOP_ENCODE, // 19
+ CME_FIR_PAR_ERR_DUP, // 20
+ CME_FIR_PAR_ERR // 21
+};
+
+// ----------------------------------------------------------------------
+// Function prototype
+// ----------------------------------------------------------------------
+
+/// @brief Initialize the actions for CME FIR, MASK and Action registers
+///
+/// @param[in] i_target Chip target
+///
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode pm_cme_fir_init(
+ const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+/// @brief Reset the actions for CME FIR, MASK and Action registers
+///
+/// @param[in] i_target Chip target
+///
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode pm_cme_fir_reset(
+ const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+// ----------------------------------------------------------------------
+// Function definitions
+// ----------------------------------------------------------------------
+
+fapi2::ReturnCode p9_pm_cme_firinit(
+ const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+ const p9pm::PM_FLOW_MODE i_mode)
+{
+ FAPI_IMP("p9_pm_cme_firinit start");
+
+ if(i_mode == p9pm::PM_RESET)
+ {
+ FAPI_TRY(pm_cme_fir_reset(i_target),
+ "ERROR: Failed to reset the CME FIRs");
+ }
+ else if(i_mode == p9pm::PM_INIT)
+ {
+ FAPI_TRY(pm_cme_fir_init(i_target),
+ "ERROR: Failed to initialize the CME FIRs");
+ }
+ else
+ {
+ FAPI_ASSERT(false, fapi2::PM_CME_FIRINIT_BAD_MODE().set_BADMODE(i_mode),
+ "ERROR; Unknown mode passed to p9_pm_cme_firinit. Mode %x",
+ i_mode);
+ }
+
+fapi_try_exit:
+ FAPI_INF("p9_pm_cme_firinit end");
+ return fapi2::current_err;
+}
+
+fapi2::ReturnCode pm_cme_fir_init(
+ const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+ FAPI_IMP("pm_cme_fir_init start");
+
+ uint8_t l_firinit_done_flag;
+ auto l_exChiplets = i_target.getChildren<fapi2::TARGET_TYPE_EX>
+ (fapi2::TARGET_STATE_FUNCTIONAL);
+
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PM_FIRINIT_DONE_ONCE_FLAG,
+ i_target, l_firinit_done_flag),
+ "ERROR: Failed to fetch the entry status of FIRINIT");
+
+ for (auto l_ex_chplt : l_exChiplets)
+ {
+ p9pmFIR::PMFir <p9pmFIR::FIRTYPE_CME_LFIR> l_cmeFir(l_ex_chplt);
+
+ /* Clear the FIR and action buffers */
+ FAPI_TRY(l_cmeFir.clearAllRegBits(p9pmFIR::REG_FIR),
+ "ERROR: Failed to clear CME FIR");
+ FAPI_TRY(l_cmeFir.clearAllRegBits(p9pmFIR::REG_ACTION0),
+ "ERROR: Failed to clear CME FIR");
+ FAPI_TRY(l_cmeFir.clearAllRegBits(p9pmFIR::REG_ACTION1),
+ "ERROR: Failed to clear CME FIR");
+
+ /* Set the action and mask for the CME LFIR bits */
+ FAPI_TRY(l_cmeFir.setRecvIntr(PPE_INT_ERR),
+ "ERROR: Failed to set recovery on interrupt");
+ FAPI_TRY(l_cmeFir.setRecvIntr(PPE_EXT_ERR),
+ "ERROR: Failed to set recovery on interrupt");
+ FAPI_TRY(l_cmeFir.setRecvIntr(PPE_PROG_ERR),
+ "ERROR: Failed to set recovery on interrupt");
+ FAPI_TRY(l_cmeFir.setRecvIntr(PPE_BRKPT_ERR),
+ "ERROR: Failed to set recovery on interrupt");
+ FAPI_TRY(l_cmeFir.mask(PPE_WATCHDOG), "ERROR: Failed to mask");
+ FAPI_TRY(l_cmeFir.mask(PPE_HALT), "ERROR: Failed to mask");
+ FAPI_TRY(l_cmeFir.mask(PPE_DBGTRG), "ERROR: Failed to mask");
+ FAPI_TRY(l_cmeFir.setRecvIntr(CME_SRAM_UE),
+ "ERROR: Failed to set recovery on interrupt");
+ FAPI_TRY(l_cmeFir.mask(CME_SRAM_CE), "ERROR: Failed to mask");
+ FAPI_TRY(l_cmeFir.setRecvIntr(BCE_ERR),
+ "ERROR: Failed to set recovery on interrupt");
+ FAPI_TRY(l_cmeFir.mask(CME_SPARE_11), "ERROR: Failed to mask");
+ FAPI_TRY(l_cmeFir.mask(CME_SPARE_12), "ERROR: Failed to mask");
+ FAPI_TRY(l_cmeFir.setRecvAttn(CME_FIR_PAR_ERR_DUP),
+ "ERROR: Failed to set the attention as recoverable");
+ FAPI_TRY(l_cmeFir.setRecvAttn(CME_FIR_PAR_ERR),
+ "ERROR: Failed to set the attention as recoverable");
+
+ //todo: Yet to confirm on the action for the following bits
+ FAPI_TRY(l_cmeFir.mask(SRAM_SCRUB_ERR), "ERROR: Failed to mask");
+ FAPI_TRY(l_cmeFir.mask(C0_iVRM_DPOUT), "ERROR: Failed to mask");
+ FAPI_TRY(l_cmeFir.mask(C1_iVRM_DPOUT), "ERROR: Failed to mask");
+ FAPI_TRY(l_cmeFir.mask(CACHE_iVRM_DPOUT), "ERROR: Failed to mask");
+ FAPI_TRY(l_cmeFir.mask(EXTRM_DROOP_ERR), "ERROR: Failed to mask");
+ FAPI_TRY(l_cmeFir.mask(LARGE_DROOP_ERR), "ERROR: Failed to mask");
+ FAPI_TRY(l_cmeFir.mask(SMALL_DROOP_ERR), "ERROR: Failed to mask");
+ FAPI_TRY(l_cmeFir.mask(UNEXP_DROOP_ENCODE), "ERROR: Failed to mask");
+
+ if (l_firinit_done_flag)
+ {
+ FAPI_TRY(l_cmeFir.restoreSavedMask(),
+ "ERROR: Failed to restore the CME mask saved");
+ }
+
+ FAPI_TRY(l_cmeFir.put(),
+ "ERROR:Failed to write to the CME FIR MASK");
+ }
+
+fapi_try_exit:
+ return fapi2::current_err;
+}
+
+fapi2::ReturnCode pm_cme_fir_reset(
+ const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+ FAPI_IMP("pm_cme_fir_reset start");
+
+ uint8_t l_firinit_done_flag;
+ auto l_exChiplets = i_target.getChildren<fapi2::TARGET_TYPE_EX>
+ (fapi2::TARGET_STATE_FUNCTIONAL);
+
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PM_FIRINIT_DONE_ONCE_FLAG,
+ i_target, l_firinit_done_flag),
+ "ERROR: Failed to fetch the entry status of FIRINIT");
+
+ for (auto l_ex_chplt : l_exChiplets)
+ {
+ p9pmFIR::PMFir <p9pmFIR::FIRTYPE_CME_LFIR> l_cmeFir(l_ex_chplt);
+
+ if (l_firinit_done_flag == 1)
+ {
+ FAPI_TRY(l_cmeFir.get(p9pmFIR::REG_FIRMASK),
+ "ERROR: Failed to get the CME FIR MASK value");
+
+ /* Fetch the CME FIR MASK; Save it to HWP attribute; clear it */
+ FAPI_TRY(l_cmeFir.saveMask(),
+ "ERROR: Failed to save CME FIR Mask to the attribute");
+ }
+
+ FAPI_TRY(l_cmeFir.setAllRegBits(p9pmFIR::REG_FIRMASK),
+ "ERROR: Faled to set the CME FIR MASK");
+
+ FAPI_TRY(l_cmeFir.put(),
+ "ERROR:Failed to write to the CME FIR MASK");
+ }
+
+fapi_try_exit:
+ return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.H
new file mode 100644
index 000000000..ed93b1354
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.H
@@ -0,0 +1,69 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.H $ */
+/* */
+/* IBM CONFIDENTIAL */
+/* */
+/* EKB Project */
+/* */
+/* COPYRIGHT 2016 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* The source code for this program is not published or otherwise */
+/* divested of its trade secrets, irrespective of what has been */
+/* deposited with the U.S. Copyright Office. */
+/* */
+/* IBM_PROLOG_END_TAG */
+///
+/// @file p9_pm_cme_firinit.H
+/// @brief Configures the CME FIRs, Mask & actions
+///
+// *HWP HW Owner: Amit Kumar <akumar3@us.ibm.com>
+// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com>
+// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team: PM
+// *HWP Level: 2
+// *HWP Consumed by: FSP:HS
+
+#ifndef _P9_PM_CME_FIRINIT_H_
+#define _P9_PM_CME_FIRINIT_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <fapi2.H>
+#include <p9_pm.H>
+#include <p9_pm_fir_class.H>
+#include <p9_quad_scom_addresses.H>
+
+// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_pm_cme_firinit_FP_t) (
+ const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
+ const p9pm::PM_FLOW_MODE);
+
+extern "C"
+{
+
+//------------------------------------------------------------------------------
+// Function prototype
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+///
+/// @brief Reset/init the CME FIRs, Actions and Masks
+///
+/// @param[in] i_target Chip target
+/// @param[in] i_mode Control mode for the procedure
+///
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+
+ fapi2::ReturnCode p9_pm_cme_firinit(
+ const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+ const p9pm::PM_FLOW_MODE i_mode);
+
+} // extern "C"
+
+#endif // _P9_PM_CME_FIRINIT_H_
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.mk b/src/import/chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.mk
new file mode 100644
index 000000000..dfcd3f80b
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.mk
@@ -0,0 +1,20 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: chips/p9/procedures/hwp/pm/p9_pm_cme_firinit.mk $
+#
+# IBM CONFIDENTIAL
+#
+# EKB Project
+#
+# COPYRIGHT 2016
+# [+] International Business Machines Corp.
+#
+#
+# The source code for this program is not published or otherwise
+# divested of its trade secrets, irrespective of what has been
+# deposited with the U.S. Copyright Office.
+#
+# IBM_PROLOG_END_TAG
+PROCEDURE=p9_pm_cme_firinit
+$(call BUILD_PROCEDURE)
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ppm_firinit.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ppm_firinit.C
index c03fcb2ef..76ddde020 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ppm_firinit.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ppm_firinit.C
@@ -7,7 +7,7 @@
/* */
/* EKB Project */
/* */
-/* COPYRIGHT 2015 */
+/* COPYRIGHT 2015,2016 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -18,31 +18,28 @@
/* IBM_PROLOG_END_TAG */
///
/// @file p9_pm_ppm_firinit.C
-/// @brief Configures the PPM FIR errors
+/// @brief Configures the CME FIRs, Mask & Actions
///
// *HWP HW Owner: Amit Kumar <akumar3@us.ibm.com>
// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com>
// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
// *HWP Team: PM
-// *HWP Level: 1
+// *HWP Level: 2
// *HWP Consumed by: FSP:HS
-///
-/// \verbatim
-///
-/// Procedure Prereq:
-/// - completed istep procedure
-///
/// High-level procedure flow:
+/// \verbatim
+/// if reset:
+/// loop over all functional chiplets (core and quad){
+/// Mask all bits of error mask
+/// }
+/// else if init:
+/// loop over all functional chiplets (core and quad) {
+/// Mask the required bits
+/// }
///
-/// get all functional child chiplets
-///
-/// loop over all functional chiplets {
-/// calculate address
-/// set the error mask in order to mask all errors
-///
-/// }
-///
+/// Procedure Prereq:
+/// o System clocks are running
/// \endverbatim
// ----------------------------------------------------------------------
@@ -51,6 +48,32 @@
#include <p9_pm_ppm_firinit.H>
// ----------------------------------------------------------------------
+// Constant Definitions
+// ----------------------------------------------------------------------
+
+// ----------------------------------------------------------------------
+// Function prototype
+// ----------------------------------------------------------------------
+
+/// @brief Initialize the core and quad's error mask registers
+///
+/// @param[in] i_target Chip target
+///
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode pm_ppm_fir_init(
+ const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+/// @brief Reset the core and quad's error mask registers
+///
+/// @param[in] i_target Chip target
+///
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode pm_ppm_fir_reset(
+ const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+// ----------------------------------------------------------------------
// Function definitions
// ----------------------------------------------------------------------
@@ -60,6 +83,147 @@ fapi2::ReturnCode p9_pm_ppm_firinit(
{
FAPI_IMP("p9_pm_ppm_firinit start");
+ if(i_mode == p9pm::PM_RESET)
+ {
+ FAPI_TRY(pm_ppm_fir_reset(i_target),
+ "ERROR: Failed to reset the Core and Quad error masks");
+ }
+ else if(i_mode == p9pm::PM_INIT)
+ {
+ FAPI_TRY(pm_ppm_fir_init(i_target),
+ "ERROR: Failed to initialize Core and Quad error masks");
+ }
+ else
+ {
+ FAPI_ASSERT(false, fapi2::PM_PPM_FIRINIT_BAD_MODE().set_BADMODE(i_mode),
+ "ERROR; Unknown mode passed to p9_pm_ppm_firinit. Mode %x",
+ i_mode);
+ }
+
+fapi_try_exit:
FAPI_INF("p9_pm_ppm_firinit end");
return fapi2::current_err;
}
+
+fapi2::ReturnCode pm_ppm_fir_init(
+ const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+ FAPI_IMP("pm_ppm_fir_init start");
+
+ uint8_t l_firinit_done_flag;
+ auto l_eqChiplets = i_target.getChildren<fapi2::TARGET_TYPE_EQ>
+ (fapi2::TARGET_STATE_FUNCTIONAL);
+
+ auto l_coreChiplets = i_target.getChildren<fapi2::TARGET_TYPE_CORE>
+ (fapi2::TARGET_STATE_FUNCTIONAL);
+
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PM_FIRINIT_DONE_ONCE_FLAG,
+ i_target, l_firinit_done_flag),
+ "ERROR: Failed to fetch the entry status of FIRINIT");
+
+ for (auto l_eq_chplt : l_eqChiplets)
+ {
+ p9pmFIR::PMFir <p9pmFIR::FIRTYPE_PPM_LFIR> l_qppmFir(l_eq_chplt);
+
+ // As of now I am just masking all the bits.
+ // The exact details about which bits to be masked/unmasked
+ // is yet to be known
+ FAPI_TRY(l_qppmFir.setAllRegBits(p9pmFIR::REG_ERRMASK),
+ "ERROR: Faled to set the Quad Error MASK");
+
+ if (l_firinit_done_flag)
+ {
+ /* Restore Quad PPM Error Mask */
+ FAPI_TRY(l_qppmFir.restoreSavedMask(),
+ "ERROR: Failed to restore the Quad Error mask saved");
+ }
+
+ FAPI_TRY(l_qppmFir.put(),
+ "ERROR:Failed to write to the Quad Error mask FIR MASK");
+ }
+
+ for (auto l_core_chplt : l_coreChiplets)
+ {
+ p9pmFIR::PMFir <p9pmFIR::FIRTYPE_PPM_LFIR> l_cppmFir(l_core_chplt);
+
+ // As of now I am just masking all the bits.
+ // The exact details about which bits to be masked/unmasked
+ // is yet to be known
+ FAPI_TRY(l_cppmFir.setAllRegBits(p9pmFIR::REG_ERRMASK),
+ "ERROR: Failed to set the Core Error MASK");
+
+ if (l_firinit_done_flag)
+ {
+ /* Restore Core PPM Error Mask */
+ FAPI_TRY(l_cppmFir.restoreSavedMask(),
+ "ERROR: Failed to restore the Core Error mask saved");
+ }
+
+ FAPI_TRY(l_cppmFir.put(),
+ "ERROR:Failed to write to the Core Error mask");
+ }
+
+fapi_try_exit:
+ return fapi2::current_err;
+}
+
+fapi2::ReturnCode pm_ppm_fir_reset(
+ const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+ FAPI_IMP("pm_ppm_fir_reset start");
+
+ uint8_t l_firinit_done_flag;
+ auto l_eqChiplets = i_target.getChildren<fapi2::TARGET_TYPE_EQ>
+ (fapi2::TARGET_STATE_FUNCTIONAL);
+ auto l_coreChiplets = i_target.getChildren<fapi2::TARGET_TYPE_CORE>
+ (fapi2::TARGET_STATE_FUNCTIONAL);
+
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PM_FIRINIT_DONE_ONCE_FLAG,
+ i_target, l_firinit_done_flag),
+ "ERROR: Failed to fetch the entry status of FIRINIT");
+
+ for (auto l_eq_chplt : l_eqChiplets)
+ {
+ p9pmFIR::PMFir <p9pmFIR::FIRTYPE_PPM_LFIR> l_ppmFir(l_eq_chplt);
+
+ if (l_firinit_done_flag == 1)
+ {
+ FAPI_TRY(l_ppmFir.get(p9pmFIR::REG_ERRMASK),
+ "ERROR: Failed to get the QUAD ERROR MASK value");
+
+ /* Fetch the QUAD ERROR MASK; Save it to HWP attribute; clear it */
+ FAPI_TRY(l_ppmFir.saveMask(),
+ "ERROR: Failed to save Quad ERROR Mask to the attribute");
+ }
+
+ FAPI_TRY(l_ppmFir.setAllRegBits(p9pmFIR::REG_ERRMASK),
+ "ERROR: Faled to set the Quad Error MASK");
+
+ FAPI_TRY(l_ppmFir.put(),
+ "ERROR:Failed to write to the Quad Error MASK");
+ }
+
+ for (auto l_c_chplt : l_coreChiplets)
+ {
+ p9pmFIR::PMFir <p9pmFIR::FIRTYPE_PPM_LFIR> l_cppmFir(l_c_chplt);
+
+ if (l_firinit_done_flag == 1)
+ {
+ FAPI_TRY(l_cppmFir.get(p9pmFIR::REG_ERRMASK),
+ "ERROR: Failed to get the Core ERROR MASK value");
+
+ /* Fetch the core ERROR MASK; Save it to HWP attribute; clear it */
+ FAPI_TRY(l_cppmFir.saveMask(),
+ "ERROR: Failed to save Core ERROR Mask to the attribute");
+ }
+
+ FAPI_TRY(l_cppmFir.setAllRegBits(p9pmFIR::REG_ERRMASK),
+ "ERROR: Faled to set the Core Error MASK");
+
+ FAPI_TRY(l_cppmFir.put(),
+ "ERROR:Failed to write to the Core Error MASK");
+ }
+
+fapi_try_exit:
+ return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ppm_firinit.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ppm_firinit.H
index c920fcddb..1c1074cb3 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ppm_firinit.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ppm_firinit.H
@@ -7,7 +7,7 @@
/* */
/* EKB Project */
/* */
-/* COPYRIGHT 2015 */
+/* COPYRIGHT 2015,2016 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -18,79 +18,25 @@
/* IBM_PROLOG_END_TAG */
///
/// @file p9_pm_ppm_firinit.H
-/// @brief Configures the PPM FIR errors
+/// @brief Configures the PPM FIRs, Mask & actions
///
// *HWP HW Owner: Amit Kumar <akumar3@us.ibm.com>
// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com>
// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
// *HWP Team: PM
-// *HWP Level: 1
+// *HWP Level: 2
// *HWP Consumed by: FSP:HS
#ifndef _P9_PM_PPM_FIRINIT_H_
#define _P9_PM_PPM_FIRINIT_H_
+
//------------------------------------------------------------------------------
// Includes
//------------------------------------------------------------------------------
#include <fapi2.H>
#include <p9_pm.H>
-#include <p9_pm_utils.H>
-
-//------------------------------------------------------------------------------
-// Global Constants
-//------------------------------------------------------------------------------
-
-#define PPM_FIR_REGISTER_LENGTH 43
-
-namespace PMFIR
-{
-enum PPM_FIRS
-{
- PPM_SLEEP_ENTRY_NOTIFY_PMC_HANG_ERR_MASK = 0,
- PPM_SLEEP_ENTRY_NOTIFY_PMC_ASSIST_HANG_ERR_MASK = 1,
- PPM_SLEEP_ENTRY_NOTIFY_PMC_ERR_MASK = 2,
- PPM_SLEEP_EXIT_INVOKE_PORE_ERR_MASK = 3,
- PPM_WINKLE_ENTRY_NOTIFY_PMC_ERR_MASK = 4,
- PPM_WINKLE_ENTRY_SEND_INT_ASSIST_ERR_MASK = 5,
- PPM_WINKLE_EXIT_NOTIFY_PMC_ERR_MASK = 6,
- PPM_WAIT_DPLL_LOCK_ERR_MASK = 7,
- PPM_SPARE8_ERR_MASK = 8,
- PPM_WINKLE_EXIT_SEND_INT_ASSIST_ERR_MASK = 9,
- PPM_WINKLE_EXIT_SEND_INT_POWUP_ASSIST_ERR_MASK = 10,
- PPM_WRITE_FSM_GOTO_REG_IN_INVALID_STATE_ERR_MASK = 11,
- PPM_WRITE_PMGP0_IN_INVALID_STATE_ERR_MASK = 12,
- PPM_FREQ_OVERFLOW_IN_PSTATE_MODE_ERR_MASK = 13,
- PPM_ECO_RS_BYPASS_CONFUSION_ERR_MASK = 14,
- PPM_CORE_RS_BYPASS_CONFUSION_ERR_MASK = 15,
- PPM_READ_LPST_IN_PSTATE_MODE_ERR_MASK = 16,
- PPM_LPST_READ_CORR_ERR_MASK = 17,
- PPM_LPST_READ_UNCORR_ERR_MASK = 18,
- PPM_PFET_STRENGTH_OVERFLOW_ERR_MASK = 19,
- PPM_VDS_LOOKUP_ERR_MASK = 20,
- PPM_IDLE_INTERRUPT_TIMEOUT_ERR_MASK = 21,
- PPM_PSTATE_INTERRUPT_TIMEOUT_ERR_MASK = 22,
- PPM_GLOBAL_ACTUAL_SYNC_INTERRUPT_TIMEOUT_ERR_MASK = 23,
- PPM_PMAX_SYNC_INTERRUPT_TIMEOUT_ERR_MASK = 24,
- PPM_GLOBAL_ACTUAL_PSTATE_PROTOCOL_ERR_MASK = 25,
- PPM_PMAX_PROTOCOL_ERR_MASK = 26,
- PPM_IVRM_GROSS_OR_FINE_ERR_MASK = 27,
- PPM_IVRM_RANGE_ERR_MASK = 28,
- PPM_DPLL_CPM_FMIN_ERR_MASK = 29,
- PPM_DPLL_DCO_FULL_ERR_MASK = 30,
- PPM_DPLL_DCO_EMPTY_ERR_MASK = 31,
- PPM_DPLL_INT_ERR_MASK = 32,
- PPM_FMIN_AND_NOT_CPMBIT_ERR_MASK = 33,
- PPM_DPLL_FASTER_THAN_FMAX_PLUS_DELTA1_ERR_MASK = 34,
- PPM_DPLL_SLOWER_THAN_FMIN_MINUS_DELTA2_ERR_MASK = 35,
- PPM_RESCLK_CSB_INSTR_VECTOR_CHG_IN_INVALID_STATE_ERR_MASK = 36,
- PPM_RESLKC_BAND_BOUNDARY_CHG_IN_INVALID_STATE_ERR_MASK = 37,
- PPM_OCC_HEARTBEAT_LOSS_ERR_MASK = 38,
- PPM_SPARE39_ERR_MASK = 39,
- PPM_SPARE40_ERR_MASK = 40,
- PPM_SPARE41_ERR_MASK = 41,
- PPM_SPARE42_ERR_MASK = 42
-};
-}
+#include <p9_pm_fir_class.H>
+#include <p9_quad_scom_addresses.H>
// function pointer typedef definition for HWP call support
typedef fapi2::ReturnCode (*p9_pm_ppm_firinit_FP_t) (
@@ -106,10 +52,10 @@ extern "C"
//------------------------------------------------------------------------------
///
-/// @brief Configures the PPM FIR in each PPM macro
+/// @brief Reset/init the PPM FIRs, Actions and Masks
///
/// @param[in] i_target Chip target
-/// @param[in] i_mode Control mode for the procedure: PM_RESET
+/// @param[in] i_mode Control mode for the procedure
///
/// @return FAPI2_RC_SUCCESS if success, else error code.
///
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