diff options
| author | Jeremy Neaton <jrneaton@us.ibm.com> | 2018-03-26 14:47:24 -0500 |
|---|---|---|
| committer | William G. Hoffa <wghoffa@us.ibm.com> | 2018-04-10 15:21:16 -0400 |
| commit | b10263aeedd30c991c5b20926a3ac1a4f5a4c70f (patch) | |
| tree | e68d47cda65d312a84fded8288863950d15038f4 /src/import | |
| parent | a4e9bdd5d47c4ac48377c12cae6952cb3101b657 (diff) | |
| download | talos-hostboot-b10263aeedd30c991c5b20926a3ac1a4f5a4c70f.tar.gz talos-hostboot-b10263aeedd30c991c5b20926a3ac1a4f5a4c70f.zip | |
TSV Updates for CL14 Support
CQ: SW423561
Change-Id: I5c508eaeb5b54cfa2d6984958a6d5b54ff78ea3e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56265
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: LUCAS W. MULKEY <lwmulkey@us.ibm.com>
Dev-Ready: JEREMY R. NEATON <jrneaton@us.ibm.com>
Reviewed-by: JEREMY R. NEATON <jrneaton@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: BRIANA E. FOXWORTH <befoxwor@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56274
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/import')
4 files changed, 268 insertions, 95 deletions
diff --git a/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mba_scom.C b/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mba_scom.C index 5773995af..baa6e5b42 100644 --- a/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mba_scom.C +++ b/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mba_scom.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -49,11 +49,11 @@ constexpr uint64_t literal_1333 = 1333; constexpr uint64_t literal_1066 = 1066; constexpr uint64_t literal_4 = 4; constexpr uint64_t literal_0b001110 = 0b001110; -constexpr uint64_t literal_9 = 9; -constexpr uint64_t literal_1866 = 1866; -constexpr uint64_t literal_0b010100 = 0b010100; constexpr uint64_t literal_1400 = 1400; +constexpr uint64_t literal_1866 = 1866; +constexpr uint64_t literal_14 = 14; constexpr uint64_t literal_0b011001 = 0b011001; +constexpr uint64_t literal_9 = 9; constexpr uint64_t literal_0b001111 = 0b001111; constexpr uint64_t literal_0b011100 = 0b011100; constexpr uint64_t literal_0b001101 = 0b001101; @@ -69,6 +69,7 @@ constexpr uint64_t literal_0b001100 = 0b001100; constexpr uint64_t literal_0b010101 = 0b010101; constexpr uint64_t literal_0b010011 = 0b010011; constexpr uint64_t literal_0b011011 = 0b011011; +constexpr uint64_t literal_0b010100 = 0b010100; constexpr uint64_t literal_5 = 5; constexpr uint64_t literal_0b000011 = 0b000011; constexpr uint64_t literal_0b0 = 0b0; @@ -197,7 +198,6 @@ constexpr uint64_t literal_0x7777777777777777 = 0x7777777777777777; constexpr uint64_t literal_0x8888888888888888 = 0x8888888888888888; constexpr uint64_t literal_0x9999999999999999 = 0x9999999999999999; constexpr uint64_t literal_0xAAAAAAAAAAAAAAAA = 0xAAAAAAAAAAAAAAAA; -constexpr uint64_t literal_14 = 14; constexpr uint64_t literal_0b001001 = 0b001001; constexpr uint64_t literal_0b000110 = 0b000110; constexpr uint64_t literal_0b001010 = 0b001010; @@ -289,47 +289,6 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& uint64_t l_def_mba_dsm0q_cfg_rdtag_dly14 = ((l_def_ddr3_1066_7_7_7_2N || l_def_ddr3_1066_6_6_6R) || l_def_ddr3_1333_8_8_8_2N); uint64_t l_def_margin_rdtag = literal_4; - uint64_t l_def_ddr4_1600_9_9_9_LR = (((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_2) - && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1600)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_9)) - && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_9)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_9)) - && (l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_0)) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_3)); - uint64_t l_def_ddr4_1866_11_11_11 = ((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_2) - && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1866)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_11)) - && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_11)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_11)) - && (((l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_0) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_2)) - || ((l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_1) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_1)))); - uint64_t l_def_ddr4_1600_11_11_11 = ((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_2) - && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1600)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_11)) - && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_11)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_11)) - && (((l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_0) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_2)) - || ((l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_1) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_1)))); - uint64_t l_def_ddr3_1333_9_9_9_L2 = (((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_1) - && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1333)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_9)) - && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_9)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_9)) - && (l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_1)) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_3)); - uint64_t l_def_ddr3_1600_9_9_9_LR = (((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_1) - && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1600)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_9)) - && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_9)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_9)) - && (l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_0)) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_3)); - uint64_t l_def_ddr3_1866_12_12_12_2N = (((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_1) - && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1866)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_12)) - && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_12)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_12)) - && (l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_1)) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_2)); - uint64_t l_def_ddr3_1866_11_11_11 = (((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_1) - && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1866)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_11)) - && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_11)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_11)) - && (l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_0)) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_2)); - uint64_t l_def_ddr3_1600_11_11_11 = (((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_1) - && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1600)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_11)) - && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_11)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_11)) - && (l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_0)) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_2)); - uint64_t l_def_ddr3_1066_8_8_8_LR = (((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_1) - && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1066)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_8)) - && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_8)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_8)) - && (l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_0)) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_3)); - uint64_t l_def_mba_dsm0q_cfg_rdtag_dly20 = ((((((((l_def_ddr3_1066_8_8_8_LR || l_def_ddr3_1600_11_11_11) - || l_def_ddr3_1866_11_11_11) || l_def_ddr3_1866_12_12_12_2N) || l_def_ddr3_1600_9_9_9_LR) || l_def_ddr3_1333_9_9_9_L2) - || l_def_ddr4_1600_11_11_11) || l_def_ddr4_1866_11_11_11) || l_def_ddr4_1600_9_9_9_LR); uint64_t l_def_ddr4_2133_12_12_12_L2 = (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1400); uint64_t l_def_ddr4_1866_12_12_12_L2 = (((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_2) && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1866)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_12)) @@ -349,9 +308,13 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1866)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_13)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_13)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_13)) && (l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_0)) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_1)); - uint64_t l_def_mba_dsm0q_cfg_rdtag_dly25 = ((((((l_def_ddr4_1866_13_13_13R || l_def_ddr4_1600_12_12_12_L2) - || l_def_ddr3_1866_12_12_12_L2) || l_def_ddr4_2400_14_14_14) || l_def_ddr4_2133_13_13_13R) - || l_def_ddr4_1866_12_12_12_L2) || l_def_ddr4_2133_12_12_12_L2); + uint64_t l_def_ddr4_1600_14_13_12 = (((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_2) + && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1600)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_14)) + && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_13)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_12)) + && (l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_0)) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_2)); + uint64_t l_def_mba_dsm0q_cfg_rdtag_dly25 = (((((((l_def_ddr4_1600_14_13_12 || l_def_ddr4_1866_13_13_13R) + || l_def_ddr4_1600_12_12_12_L2) || l_def_ddr3_1866_12_12_12_L2) || l_def_ddr4_2400_14_14_14) + || l_def_ddr4_2133_13_13_13R) || l_def_ddr4_1866_12_12_12_L2) || l_def_ddr4_2133_12_12_12_L2); uint64_t l_def_ddr4_1600_9_9_9_2N = (((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_2) && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1600)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_9)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_9)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_9)) @@ -444,9 +407,13 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1600)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_12)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_12)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_12)) && (l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_0)) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_3)); - uint64_t l_def_mba_dsm0q_cfg_rdtag_dly26 = (((((l_def_ddr4_1600_12_12_12_LR || l_def_ddr3_1866_12_12_12_LR) - || l_def_ddr4_2400_14_14_14R) || l_def_ddr4_1866_12_12_12_LR) || l_def_ddr4_2133_12_12_12_LR) - || l_def_ddr4_2400_13_13_13_L2); + uint64_t l_def_ddr4_1600_14_13_12R = (((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_2) + && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1600)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_14)) + && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_13)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_12)) + && (l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_0)) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_1)); + uint64_t l_def_mba_dsm0q_cfg_rdtag_dly26 = ((((((l_def_ddr4_1600_14_13_12R || l_def_ddr4_1600_12_12_12_LR) + || l_def_ddr3_1866_12_12_12_LR) || l_def_ddr4_2400_14_14_14R) || l_def_ddr4_1866_12_12_12_LR) + || l_def_ddr4_2133_12_12_12_LR) || l_def_ddr4_2400_13_13_13_L2); uint64_t l_def_ddr4_1600_10_10_10 = ((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_2) && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1600)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_10)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_10)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_10)) @@ -705,6 +672,47 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& && (l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_1)) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_3)); uint64_t l_def_mba_dsm0q_cfg_rdtag_dly27 = (((l_def_ddr4_1600_13_12_11_L2 || l_def_ddr4_1866_13_13_13_L2) || l_def_ddr4_2400_13_13_13_LR) || l_def_ddr4_2133_13_13_13_L2); + uint64_t l_def_ddr4_1600_9_9_9_LR = (((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_2) + && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1600)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_9)) + && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_9)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_9)) + && (l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_0)) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_3)); + uint64_t l_def_ddr4_1866_11_11_11 = ((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_2) + && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1866)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_11)) + && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_11)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_11)) + && (((l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_0) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_2)) + || ((l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_1) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_1)))); + uint64_t l_def_ddr4_1600_11_11_11 = ((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_2) + && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1600)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_11)) + && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_11)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_11)) + && (((l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_0) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_2)) + || ((l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_1) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_1)))); + uint64_t l_def_ddr3_1333_9_9_9_L2 = (((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_1) + && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1333)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_9)) + && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_9)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_9)) + && (l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_1)) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_3)); + uint64_t l_def_ddr3_1600_9_9_9_LR = (((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_1) + && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1600)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_9)) + && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_9)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_9)) + && (l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_0)) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_3)); + uint64_t l_def_ddr3_1866_12_12_12_2N = (((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_1) + && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1866)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_12)) + && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_12)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_12)) + && (l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_1)) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_2)); + uint64_t l_def_ddr3_1866_11_11_11 = (((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_1) + && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1866)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_11)) + && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_11)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_11)) + && (l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_0)) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_2)); + uint64_t l_def_ddr3_1600_11_11_11 = (((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_1) + && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1600)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_11)) + && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_11)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_11)) + && (l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_0)) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_2)); + uint64_t l_def_ddr3_1066_8_8_8_LR = (((((((l_TGT0_ATTR_CEN_EFF_DRAM_GEN == literal_1) + && (l_TGT1_ATTR_CEN_MSS_FREQ == literal_1066)) && (l_TGT0_ATTR_CEN_EFF_DRAM_CL == literal_8)) + && (l_TGT0_ATTR_CEN_EFF_DRAM_TRCD == literal_8)) && (l_TGT0_ATTR_CEN_EFF_DRAM_TRP == literal_8)) + && (l_TGT0_ATTR_CEN_VPD_DRAM_2N_MODE_ENABLED == literal_0)) && (l_TGT0_ATTR_CEN_EFF_DIMM_TYPE == literal_3)); + uint64_t l_def_mba_dsm0q_cfg_rdtag_dly20 = ((((((((l_def_ddr3_1066_8_8_8_LR || l_def_ddr3_1600_11_11_11) + || l_def_ddr3_1866_11_11_11) || l_def_ddr3_1866_12_12_12_2N) || l_def_ddr3_1600_9_9_9_LR) || l_def_ddr3_1333_9_9_9_L2) + || l_def_ddr4_1600_11_11_11) || l_def_ddr4_1866_11_11_11) || l_def_ddr4_1600_9_9_9_LR); uint64_t l_def_RDODT_duration = literal_5; uint64_t l_def_margin2 = literal_0; fapi2::ATTR_CEN_EFF_STACK_TYPE_Type l_TGT0_ATTR_CEN_EFF_STACK_TYPE; @@ -749,9 +757,10 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& || l_def_ddr4_1866_11_11_11) || l_def_ddr4_2133_12_12_12) || l_def_ddr4_1600_11_11_11_2N) || l_def_ddr4_1866_11_11_11_2N) || l_def_ddr4_2133_12_12_12_2N) || l_def_ddr4_1600_11_11_11R) || l_def_ddr4_1866_11_11_11R) || l_def_ddr4_2133_12_12_12R); - uint64_t l_def_mba_tmr0q_RW_dlys12 = ((((((((l_def_ddr4_1600_13_12_11_2N || l_def_ddr3_1066_7_7_7_L2) - || l_def_ddr3_1066_7_7_7_LR) || l_def_ddr3_1333_8_8_8_LR) || l_def_ddr3_1600_9_9_9_LR) || l_def_ddr3_1333_8_8_8_L2) - || l_def_ddr3_1600_9_9_9_L2) || l_def_ddr4_1600_10_10_10_LR) || l_def_ddr4_1600_10_10_10_L2); + uint64_t l_def_mba_tmr0q_RW_dlys12 = ((((((((((l_def_ddr4_1600_14_13_12 || l_def_ddr4_1600_14_13_12R) + || l_def_ddr4_1600_13_12_11_2N) || l_def_ddr3_1066_7_7_7_L2) || l_def_ddr3_1066_7_7_7_LR) || l_def_ddr3_1333_8_8_8_LR) + || l_def_ddr3_1600_9_9_9_LR) || l_def_ddr3_1333_8_8_8_L2) || l_def_ddr3_1600_9_9_9_L2) || l_def_ddr4_1600_10_10_10_LR) + || l_def_ddr4_1600_10_10_10_L2); uint64_t l_def_mba_tmr0q_WRSM_dlys23 = ((((l_def_ddr3_1333_8_8_8 || l_def_ddr3_1333_8_8_8_2N) || l_def_ddr3_1333_8_8_8R) || l_def_ddr3_1333_8_8_8_LR) || l_def_ddr3_1333_8_8_8_L2); uint64_t l_def_ddr3_1066_8_8_8_group = ((((l_def_ddr3_1066_8_8_8 || l_def_ddr3_1066_8_8_8_2N) @@ -771,9 +780,9 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& || l_def_ddr4_2400_14_14_14R) || l_def_ddr4_2400_14_14_14_LR) || l_def_ddr4_2400_14_14_14_L2); uint64_t l_def_mba_tmr0q_WRSM_dlys27 = ((((l_def_ddr3_1600_10_10_10 || l_def_ddr3_1600_10_10_10_2N) || l_def_ddr3_1600_10_10_10R) || l_def_ddr3_1600_10_10_10_LR) || l_def_ddr3_1600_10_10_10_L2); - uint64_t l_def_mba_tmr0q_WRSM_dlys15 = (((((((l_def_ddr4_1600_11_11_11 || l_def_ddr4_1600_11_11_11_2N) + uint64_t l_def_mba_tmr0q_WRSM_dlys15 = ((((((((l_def_ddr4_1600_11_11_11 || l_def_ddr4_1600_11_11_11_2N) || l_def_ddr4_1600_11_11_11R) || l_def_ddr4_1600_11_11_11_LR) || l_def_ddr4_1600_11_11_11_L2) - || l_def_ddr4_1600_13_12_11) || l_def_ddr4_1600_13_12_11_2N) || l_def_ddr4_1600_13_12_11R); + || l_def_ddr4_1600_13_12_11) || l_def_ddr4_1600_13_12_11_2N) || l_def_ddr4_1600_14_13_12) || l_def_ddr4_1600_14_13_12R); uint64_t l_def_mba_tmr0q_WRSM_dlys32 = ((((((((((((((l_def_ddr4_1866_13_13_13 || l_def_ddr4_1866_13_13_13_2N) || l_def_ddr4_1866_13_13_13R) || l_def_ddr4_1866_13_13_13_LR) || l_def_ddr4_1866_13_13_13_L2) || l_def_ddr3_1866_12_12_12) || l_def_ddr3_1866_12_12_12_2N) || l_def_ddr3_1866_12_12_12R) @@ -807,12 +816,12 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& || l_def_ddr4_2133_12_12_12_L2) || l_def_ddr4_2400_14_14_14_L2); uint64_t l_def_mba_tmr0q_WRDM_dlys8 = ((((l_def_ddr4_2400_13_13_13 || l_def_ddr4_2400_13_13_13_2N) || l_def_ddr4_2400_13_13_13R) || l_def_ddr4_2400_13_13_13_LR) || l_def_ddr4_2400_13_13_13_L2); - uint64_t l_def_mba_tmr0q_WRDM_dlys4 = ((((((((((((((l_def_ddr4_1600_13_12_11 || l_def_ddr4_1600_13_12_11R) - || l_def_ddr4_1600_13_12_11_2N) || l_def_ddr4_1600_13_12_11_L2) || l_def_ddr4_1600_13_12_11_LR) - || l_def_ddr4_1600_12_12_12) || l_def_ddr4_1600_12_12_12_2N) || l_def_ddr4_1600_12_12_12R) - || l_def_ddr4_1600_12_12_12_LR) || l_def_ddr4_1600_12_12_12_L2) || l_def_ddr3_1600_11_11_11) - || l_def_ddr3_1600_11_11_11_2N) || l_def_ddr3_1600_11_11_11R) || l_def_ddr3_1600_11_11_11_LR) - || l_def_ddr3_1600_11_11_11_L2); + uint64_t l_def_mba_tmr0q_WRDM_dlys4 = ((((((((((((((((l_def_ddr4_1600_14_13_12 || l_def_ddr4_1600_14_13_12R) + || l_def_ddr4_1600_13_12_11) || l_def_ddr4_1600_13_12_11R) || l_def_ddr4_1600_13_12_11_2N) + || l_def_ddr4_1600_13_12_11_L2) || l_def_ddr4_1600_13_12_11_LR) || l_def_ddr4_1600_12_12_12) + || l_def_ddr4_1600_12_12_12_2N) || l_def_ddr4_1600_12_12_12R) || l_def_ddr4_1600_12_12_12_LR) + || l_def_ddr4_1600_12_12_12_L2) || l_def_ddr3_1600_11_11_11) || l_def_ddr3_1600_11_11_11_2N) + || l_def_ddr3_1600_11_11_11R) || l_def_ddr3_1600_11_11_11_LR) || l_def_ddr3_1600_11_11_11_L2); uint64_t l_def_mba_tmr0q_WRDM_dlys5 = (((((((((((((((((((((((((l_def_ddr4_1866_13_13_13 || l_def_ddr4_1866_13_13_13_2N) || l_def_ddr4_1866_13_13_13R) || l_def_ddr4_1866_13_13_13_LR) || l_def_ddr4_1866_13_13_13_L2) || l_def_ddr3_1066_8_8_8_group) || l_def_ddr3_1333_9_9_9) || l_def_ddr3_1600_10_10_10) || l_def_ddr3_1866_12_12_12) @@ -842,8 +851,9 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& || l_def_ddr3_1333_8_8_8_2N) || l_def_ddr3_1333_8_8_8R) || l_def_ddr3_1333_8_8_8_LR) || l_def_ddr3_1333_8_8_8_L2); uint64_t l_def_mba_tmr1q_cfg_trap46 = ((((l_def_ddr4_1866_13_13_13 || l_def_ddr4_1866_13_13_13_2N) || l_def_ddr4_1866_13_13_13R) || l_def_ddr4_1866_13_13_13_LR) || l_def_ddr4_1866_13_13_13_L2); - uint64_t l_def_mba_tmr1q_cfg_trap42 = ((((l_def_ddr4_1600_12_12_12 || l_def_ddr4_1600_12_12_12_2N) - || l_def_ddr4_1600_12_12_12R) || l_def_ddr4_1600_12_12_12_LR) || l_def_ddr4_1600_12_12_12_L2); + uint64_t l_def_mba_tmr1q_cfg_trap42 = ((((((l_def_ddr4_1600_14_13_12 || l_def_ddr4_1600_14_13_12R) + || l_def_ddr4_1600_12_12_12) || l_def_ddr4_1600_12_12_12_2N) || l_def_ddr4_1600_12_12_12R) + || l_def_ddr4_1600_12_12_12_LR) || l_def_ddr4_1600_12_12_12_L2); uint64_t l_def_mba_tmr1q_cfg_trap38 = (((((((((l_def_ddr3_1600_10_10_10 || l_def_ddr3_1600_10_10_10_2N) || l_def_ddr3_1600_10_10_10R) || l_def_ddr3_1600_10_10_10_LR) || l_def_ddr3_1600_10_10_10_L2) || l_def_ddr4_1600_10_10_10) || l_def_ddr4_1600_10_10_10_2N) || l_def_ddr4_1600_10_10_10R) @@ -903,9 +913,10 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& || l_def_ddr3_1866_11_11_11_L2); uint64_t l_def_mba_tmr1q_WRSBG_dlys30 = ((((l_def_ddr4_1866_11_11_11 || l_def_ddr4_1866_11_11_11_2N) || l_def_ddr4_1866_11_11_11R) || l_def_ddr4_1866_11_11_11_LR) || l_def_ddr4_1866_11_11_11_L2); - uint64_t l_def_mba_tmr1q_WRSBG_dlys19 = (((((((l_def_ddr4_1600_11_11_11 || l_def_ddr4_1600_11_11_11_2N) + uint64_t l_def_mba_tmr1q_WRSBG_dlys19 = (((((((((l_def_ddr4_1600_11_11_11 || l_def_ddr4_1600_11_11_11_2N) || l_def_ddr4_1600_11_11_11R) || l_def_ddr4_1600_11_11_11_LR) || l_def_ddr4_1600_11_11_11_L2) - || l_def_ddr4_1600_13_12_11) || l_def_ddr4_1600_13_12_11_2N) || l_def_ddr4_1600_13_12_11R); + || l_def_ddr4_1600_13_12_11) || l_def_ddr4_1600_13_12_11_2N) || l_def_ddr4_1600_13_12_11R) || l_def_ddr4_1600_14_13_12) + || l_def_ddr4_1600_14_13_12R); uint64_t l_def_mba_tmr1q_WRSBG_dlys31 = ((((l_def_ddr4_1866_12_12_12 || l_def_ddr4_1866_12_12_12_2N) || l_def_ddr4_1866_12_12_12R) || l_def_ddr4_1866_12_12_12_LR) || l_def_ddr4_1866_12_12_12_L2); uint64_t l_def_mba_tmr1q_WRSBG_dlys29 = ((((l_def_ddr4_1600_12_12_12 || l_def_ddr4_1600_12_12_12_2N) @@ -941,10 +952,11 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& uint64_t l_def_mba_tmr1q_cfg_twap42 = l_def_mba_tmr1q_cfg_trap37; uint64_t l_def_mba_tmr1q_cfg_twap34 = l_def_ddr3_1066_8_8_8_group; uint64_t l_def_mba_tmr1q_cfg_twap37 = l_def_mba_tmr1q_cfg_trap32; - uint64_t l_def_mba_tmr1q_cfg_twap49 = (((((((((l_def_ddr3_1866_11_11_11 || l_def_ddr3_1866_11_11_11_2N) - || l_def_ddr3_1866_11_11_11R) || l_def_ddr3_1866_11_11_11_LR) || l_def_ddr3_1866_11_11_11_L2) - || l_def_ddr4_1866_11_11_11) || l_def_ddr4_1866_11_11_11_2N) || l_def_ddr4_1866_11_11_11R) - || l_def_ddr4_1866_11_11_11_LR) || l_def_ddr4_1866_11_11_11_L2); + uint64_t l_def_mba_tmr1q_cfg_twap49 = (((((((((((l_def_ddr4_1600_14_13_12 || l_def_ddr4_1600_14_13_12R) + || l_def_ddr3_1866_11_11_11) || l_def_ddr3_1866_11_11_11_2N) || l_def_ddr3_1866_11_11_11R) + || l_def_ddr3_1866_11_11_11_LR) || l_def_ddr3_1866_11_11_11_L2) || l_def_ddr4_1866_11_11_11) + || l_def_ddr4_1866_11_11_11_2N) || l_def_ddr4_1866_11_11_11R) || l_def_ddr4_1866_11_11_11_LR) + || l_def_ddr4_1866_11_11_11_L2); uint64_t l_def_mba_tmr1q_cfg_twap32 = l_def_ddr3_1066_7_7_7_group; uint64_t l_def_mba_tmr1q_cfg_twap30 = l_def_ddr3_1066_6_6_6_group; uint64_t l_def_mba_tmr1q_cfg_twap39 = l_def_mba_tmr1q_cfg_trap33; @@ -4102,10 +4114,6 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& { l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_0b001110 + l_def_margin_rdtag) ); } - else if ((l_def_mba_dsm0q_cfg_rdtag_dly20 == literal_1)) - { - l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_0b010100 + l_def_margin_rdtag) ); - } else if ((l_def_mba_dsm0q_cfg_rdtag_dly25 == literal_1)) { l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_0b011001 + l_def_margin_rdtag) ); @@ -4170,6 +4178,10 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& { l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_0b011011 + l_def_margin_rdtag) ); } + else if ((l_def_mba_dsm0q_cfg_rdtag_dly20 == literal_1)) + { + l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_0b010100 + l_def_margin_rdtag) ); + } if (literal_1) { @@ -5347,6 +5359,14 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& { l_scom_buffer.insert<0, 6, 58, uint64_t>(literal_0b010000 ); } + else if ((l_def_ddr4_1600_14_13_12 == literal_1)) + { + l_scom_buffer.insert<0, 6, 58, uint64_t>(literal_0b010000 ); + } + else if ((l_def_ddr4_1600_14_13_12R == literal_1)) + { + l_scom_buffer.insert<0, 6, 58, uint64_t>(literal_0b010000 ); + } else if ((l_def_ddr4_1600_13_12_11_2N == literal_1)) { l_scom_buffer.insert<0, 6, 58, uint64_t>(literal_0b010000 ); @@ -5404,6 +5424,14 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& { l_scom_buffer.insert<12, 6, 58, uint64_t>(literal_0b010100 ); } + else if ((l_def_ddr4_1600_14_13_12 == literal_1)) + { + l_scom_buffer.insert<12, 6, 58, uint64_t>(literal_0b010100 ); + } + else if ((l_def_ddr4_1600_14_13_12R == literal_1)) + { + l_scom_buffer.insert<12, 6, 58, uint64_t>(literal_0b010100 ); + } else if ((l_def_ddr4_1600_13_12_11_2N == literal_1)) { l_scom_buffer.insert<12, 6, 58, uint64_t>(literal_0b010100 ); @@ -5453,6 +5481,14 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& { l_scom_buffer.insert<18, 6, 58, uint64_t>(literal_0b011100 ); } + else if ((l_def_ddr4_1600_14_13_12 == literal_1)) + { + l_scom_buffer.insert<18, 6, 58, uint64_t>(literal_0b011100 ); + } + else if ((l_def_ddr4_1600_14_13_12R == literal_1)) + { + l_scom_buffer.insert<18, 6, 58, uint64_t>(literal_0b011100 ); + } else if ((l_def_ddr4_1600_13_12_11_2N == literal_1)) { l_scom_buffer.insert<18, 6, 58, uint64_t>(literal_0b011100 ); @@ -5769,6 +5805,14 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& { l_scom_buffer.insert<6, 6, 58, uint64_t>(literal_0b011000 ); } + else if ((l_def_ddr4_1600_14_13_12 == literal_1)) + { + l_scom_buffer.insert<6, 6, 58, uint64_t>(literal_0b011000 ); + } + else if ((l_def_ddr4_1600_14_13_12R == literal_1)) + { + l_scom_buffer.insert<6, 6, 58, uint64_t>(literal_0b011000 ); + } else if ((l_def_ddr4_1600_13_12_11_2N == literal_1)) { l_scom_buffer.insert<6, 6, 58, uint64_t>(literal_0b011000 ); @@ -6336,7 +6380,8 @@ fapi2::ReturnCode centaur_mba_scom(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& l_scom_buffer.insert<9, 11, 53, uint64_t>(l_def_mba23_refresh_interval ); } - if (((l_def_ddr4_1600_13_12_11 == literal_1) || (l_def_IS3A_IS3B == literal_1))) + if (((((l_def_ddr4_1600_13_12_11 == literal_1) || (l_def_ddr4_1600_14_13_12 == literal_1)) + || (l_def_ddr4_1600_14_13_12R == literal_1)) || (l_def_IS3A_IS3B == literal_1))) { l_scom_buffer.insert<40, 10, 54, uint64_t>(literal_0b0001100000 ); } diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config.C index 8ce32268d..bc137313d 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -46,6 +46,27 @@ constexpr uint32_t MSS_EFF_EMPTY = 0; constexpr uint32_t MSS_EFF_VALID = 255; constexpr uint32_t TWO_MHZ = 2000000; +//---------------------------------------------------------------------- +// ENUMs +//---------------------------------------------------------------------- +enum DDR4_3DS_SPEEDBIN +{ + MSS_EFF_CL_12_11_10 = 0x0C, + MSS_EFF_CL_13_12_11 = 0x0D, + MSS_EFF_CL_14_13_12 = 0x0E, + MSS_EFF_TRCD_12_11_10 = 0x0B, + MSS_EFF_TRCD_13_12_11 = 0x0C, + MSS_EFF_TRCD_14_13_12 = 0x0D, + MSS_EFF_TRP_12_11_10 = 0x0A, + MSS_EFF_TRP_13_12_11 = 0x0B, + MSS_EFF_TRP_14_13_12 = 0x0C, + MSS_EFF_TRAS_12_11_10 = 0x0000001C, + MSS_EFF_TRAS_13_12_11 = 0x0000001C, + MSS_EFF_TRAS_14_13_12 = 0x0000001C, + MSS_EFF_TRC_12_11_10 = 0x00000026, + MSS_EFF_TRC_13_12_11 = 0x00000027, + MSS_EFF_TRC_14_13_12 = 0x00000028, +}; extern "C" { @@ -741,6 +762,7 @@ extern "C" mss_eff_config_spd_data* i_data, mss_eff_config_atts* o_atts) { + uint8_t l_eff_dram_cl = 0; uint8_t l_vpd_dram_address_mirroring[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT] = {0}; uint8_t l_mss_dram_2n_mode_enable = 0; uint8_t l_attr_vpd_dram_wrddr4_vref[MAX_PORTS_PER_MBA] = {0}; @@ -765,6 +787,7 @@ extern "C" // Transfer powerdown request from system attr to DRAM attr FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MRW_POWER_CONTROL_REQUESTED, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_mss_power_control_requested)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_DRAM_CL, i_target_mba, l_eff_dram_cl)); if ( l_mss_power_control_requested == fapi2::ENUM_ATTR_CEN_MRW_POWER_CONTROL_REQUESTED_FASTEXIT) { @@ -1400,6 +1423,7 @@ extern "C" if (i_data->dram_device_type[l_cur_mba_port][l_cur_mba_dimm] == fapi2::ENUM_ATTR_CEN_SPD_DRAM_DEVICE_TYPE_DDR3) { + i_mss_eff_config_data->dram_twtr = calc_timing_in_clk ( i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port] @@ -1982,15 +2006,41 @@ extern "C" } } - //Adding timer overrides for 1600 DDR4 TSV DIMMs - //TSV tRCD Override when requiring 1600 freq override (i.e. using 2666 parts) + // DDR4-1600 3DS CL-RCD-RP Settings if ((i_mss_eff_config_data->mss_freq == 1600) - && (o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] == fapi2::ENUM_ATTR_CEN_EFF_STACK_TYPE_STACK_3DS)) + && (o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] == fapi2::ENUM_ATTR_CEN_EFF_STACK_TYPE_STACK_3DS) + && (o_atts->eff_dram_gen == fapi2::ENUM_ATTR_CEN_EFF_DRAM_GEN_DDR4)) { - o_atts->eff_dram_trcd = 0x0C; - o_atts->eff_dram_trp = 0x0B; - o_atts->eff_dram_tras_u32 = 0x0000001C; - o_atts->eff_dram_trc_u32 = 0x00000027; + switch(l_eff_dram_cl) + { + case MSS_EFF_CL_12_11_10: + o_atts->eff_dram_trcd = MSS_EFF_TRCD_12_11_10; + o_atts->eff_dram_trp = MSS_EFF_TRP_12_11_10; + o_atts->eff_dram_tras_u32 = MSS_EFF_TRAS_12_11_10; + o_atts->eff_dram_trc_u32 = MSS_EFF_TRC_12_11_10; + break; + + case MSS_EFF_CL_13_12_11: + o_atts->eff_dram_trcd = MSS_EFF_TRCD_13_12_11; + o_atts->eff_dram_trp = MSS_EFF_TRP_13_12_11; + o_atts->eff_dram_tras_u32 = MSS_EFF_TRAS_13_12_11; + o_atts->eff_dram_trc_u32 = MSS_EFF_TRC_13_12_11; + break; + + case MSS_EFF_CL_14_13_12: + o_atts->eff_dram_trcd = MSS_EFF_TRCD_14_13_12; + o_atts->eff_dram_trp = MSS_EFF_TRP_14_13_12; + o_atts->eff_dram_tras_u32 = MSS_EFF_TRAS_14_13_12; + o_atts->eff_dram_trc_u32 = MSS_EFF_TRC_14_13_12; + break; + + default: + FAPI_ASSERT(false, + fapi2::CEN_MSS_EFF_CONFIG_DIMM_INVALID_3DS_CL(). + set_TARGET_MBA(i_target_mba). + set_UNSUPPORTED_VAL(l_eff_dram_cl), + "Invalid CAS Latency for 3DS DIMM Type on %s!", mss::c_str(i_target_mba)); + } } // AST HERE: Needed SPD byte33[7,1:0], for expanded IBM_TYPE diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_freq.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_freq.C index 18a1201d3..d15ff2063 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_freq.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_freq.C @@ -59,7 +59,28 @@ constexpr uint8_t DDR4_MTB_DIVISOR = 8; constexpr uint8_t DDR4_FTB_DIVIDEND = 1; constexpr uint8_t DDR4_FTB_DIVISOR = 1; constexpr uint8_t NUM_CL_SUPPORTED = 21; - +constexpr uint8_t DDR3_CL_SUPPORT_OFFSET = 4; +constexpr uint8_t DDR4_CL_SUPPORT_OFFSET = 7; +constexpr uint8_t MAX_CL_SUPPORTED = 14; +constexpr uint64_t DDR3_TAA_MAX = 20000; +constexpr uint64_t DDR4_TAA_MAX = 18000; +constexpr uint64_t DDR4_3DS_TAA_MAX = 21500; + +///Bool function for DDR3/DDR4 CL Supported Check +/// +/// @brief Checks calculated CL against supported list in SPD +/// @param[in] i_spd_cas_lat_supported_all List of CL supported in SPD +/// @param[in] i_cl_support_offset Offset for DDR3/DDR4 decode +/// @param[in] i_cas_latency Calculated CAS Latency +/// @return 1 if unsupported, 0 if supported +/// +bool mss_freq_unsupported_cl( + const uint32_t i_spd_cas_lat_supported_all, + const uint8_t i_cl_support_offset, + const uint8_t i_cas_latency) +{ + return (!( i_spd_cas_lat_supported_all & (0x00000001 << (i_cas_latency - i_cl_support_offset)))); +} /// /// @brief DIMM SPD attributes are read to determine optimal DRAM frequency @@ -114,6 +135,10 @@ fapi2::ReturnCode p9c_mss_freq(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHI uint8_t l_highest_cl_count = 0; uint8_t l_lowest_common_cl = 0; uint32_t l_lowest_cl_count = 0xFFFFFFFF; + uint8_t l_cl_support_offset = 0; + uint64_t l_taa_max = 0; + uint8_t l_spd_sdram_dev_type = 0; + uint8_t l_spd_sdram_dev_type_sig_loading = 0; for(uint8_t i = 0; i < NUM_CL_SUPPORTED; i++) { @@ -132,6 +157,9 @@ fapi2::ReturnCode p9c_mss_freq(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHI for (const auto& l_dimm : l_dimm_targets) { FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_SPD_DRAM_DEVICE_TYPE, l_dimm, l_spd_dram_dev_type)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_SPD_SDRAM_DEVICE_TYPE, l_dimm, l_spd_sdram_dev_type)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_SPD_SDRAM_DEVICE_TYPE_SIGNAL_LOADING, l_dimm, l_spd_sdram_dev_type_sig_loading)); + if (l_spd_dram_dev_type == fapi2::ENUM_ATTR_CEN_SPD_DRAM_DEVICE_TYPE_DDR4) { @@ -604,25 +632,44 @@ fapi2::ReturnCode p9c_mss_freq(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHI FAPI_INF( "After rounding up ... CL: %d", l_cas_latency); } - //Setting Max CL = 13 for 1600 DDR4 TSV - if (l_dimm_freq_min == 1600 && l_cas_latency > 13) + l_cl_mult_tck = l_cas_latency * l_spd_min_tck_max; + + + l_cl_support_offset = (l_spd_dram_dev_type == fapi2::ENUM_ATTR_CEN_SPD_DRAM_DEVICE_TYPE_DDR3) ? + DDR3_CL_SUPPORT_OFFSET : DDR4_CL_SUPPORT_OFFSET; + + if(l_spd_dram_dev_type == fapi2::ENUM_ATTR_CEN_SPD_DRAM_DEVICE_TYPE_DDR4) { - FAPI_INF( "Setting CL to 13 from %d", l_cas_latency); - l_cas_latency = 13; + if((l_spd_sdram_dev_type == fapi2::ENUM_ATTR_CEN_SPD_SDRAM_DEVICE_TYPE_NON_STANDARD) + && (l_spd_sdram_dev_type_sig_loading == fapi2::ENUM_ATTR_CEN_SPD_SDRAM_DEVICE_TYPE_SIGNAL_LOADING_SINGLE_LOAD_STACK)) + { + l_taa_max = DDR4_3DS_TAA_MAX; + } + else + { + l_taa_max = DDR4_TAA_MAX; + } + } + else + { + l_taa_max = DDR3_TAA_MAX; } - l_cl_mult_tck = l_cas_latency * l_spd_min_tck_max; + FAPI_INF("taa_max = %d", l_taa_max); // If the CL proposed is not supported or the TAA exceeds TAA max // Spec defines tAAmax as 20 ns for all DDR3 speed grades. // Break loop if we have an override condition without a solution. - while ( ( (!( l_spd_cas_lat_supported_all & (0x00000001 << (l_cas_latency - 4)))) || (l_cl_mult_tck > 20000) ) - && ( l_override_path == 0 ) ) + + while ( ( ( mss_freq_unsupported_cl(l_spd_cas_lat_supported_all, l_cl_support_offset, l_cas_latency) ) + || (l_cl_mult_tck > l_taa_max) ) + && ( l_override_path == 0) ) { FAPI_INF( "Warning calculated CL is not supported in VPD. Searching for a new CL."); // If not supported, increment the CL up to 18 (highest supported CL) looking for Supported CL - while ((!( l_spd_cas_lat_supported_all & (0x00000001 << (l_cas_latency - 4)))) && (l_cas_latency < 18)) + while ( ( mss_freq_unsupported_cl(l_spd_cas_lat_supported_all, l_cl_support_offset, l_cas_latency) ) + && (l_cas_latency < MAX_CL_SUPPORTED) ) { l_cas_latency++; } @@ -631,9 +678,11 @@ fapi2::ReturnCode p9c_mss_freq(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHI l_cl_mult_tck = l_cas_latency * l_spd_min_tck_max; // Do not move freq if using an override freq. Just continue. Hence the overide in this if statement - if ( ( (!( l_spd_cas_lat_supported_all & (0x00000001 << (l_cas_latency - 4)))) || (l_cl_mult_tck > 20000) ) + if ( ( ( mss_freq_unsupported_cl(l_spd_cas_lat_supported_all, l_cl_support_offset, l_cas_latency) ) + || (l_cl_mult_tck > l_taa_max) ) && ( l_freq_override == 0) ) { + FAPI_INF( "No Supported CL works for calculating frequency. Lowering frequency and trying CL Algorithm again."); if (l_spd_min_tck_max < 1500) @@ -655,6 +704,7 @@ fapi2::ReturnCode p9c_mss_freq(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHI { //This is minimum frequency and cannot be lowered //Therefore we will deconfig the minority dimms. + //Any CL 20+ is unsupported speed bin for Centaur for(uint8_t i = 0; i < 20; i++) { if (l_cl_count_array[i] > l_lowest_cl_count) @@ -700,7 +750,8 @@ fapi2::ReturnCode p9c_mss_freq(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHI // Need to break the loop in case we reach this condition because no longer modify freq and CL // With an overrride - if ( ( (!( l_spd_cas_lat_supported_all & (0x00000001 << (l_cas_latency - 4)))) || (l_cl_mult_tck > 20000) ) + if ( ( ( mss_freq_unsupported_cl(l_spd_cas_lat_supported_all, l_cl_support_offset, l_cas_latency) ) + || (l_cl_mult_tck > l_taa_max) ) && ( l_freq_override != 0) ) { FAPI_INF( "No Supported CL works for override frequency. Using override frequency with an unsupported CL."); diff --git a/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_eff_config_errors.xml b/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_eff_config_errors.xml index 4757c2aab..a42bc0062 100644 --- a/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_eff_config_errors.xml +++ b/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_eff_config_errors.xml @@ -956,6 +956,33 @@ <!-- *********************************************************************** --> <hwpError> + <rc>RC_CEN_MSS_EFF_CONFIG_DIMM_INVALID_3DS_CL</rc> + <description>Invalid CAS Latency for 3DS DIMM Type + </description> + <ffdc>UNSUPPORTED_VAL</ffdc> + <FFDC>TARGET_MBA</FFDC> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> + <priority>HIGH</priority> + </callout> + <deconfigure> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> + </deconfigure> + +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> <rc>RC_CEN_MSS_EFF_CONFIG_MSS_FREQ</rc> <description>Invalid ATTR_MSS_FREQ </description> |
