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| author | Tsung Yeung <tyeung@us.ibm.com> | 2019-02-07 12:08:29 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-04-10 12:14:42 -0500 |
| commit | ff832044c09e8520d1b3475025af09c147b8d813 (patch) | |
| tree | 7f31b22743d26af8ad5408d1d17d27aed7fcd6fc /src/import | |
| parent | d4dae0f8372590e905302b9882e05fcf7b4487f4 (diff) | |
| download | talos-hostboot-ff832044c09e8520d1b3475025af09c147b8d813.tar.gz talos-hostboot-ff832044c09e8520d1b3475025af09c147b8d813.zip | |
Adjust STR enter sequence to enable immediate entry
Change-Id: I4d873164914ae877ceba885f2621f6dc71b97d13
Original-Change-Id: Id6f2e59fbc3feb7cae69e39685b3c183fba6f2a1
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71532
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75753
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/workarounds/nvdimm_workarounds.C | 33 |
1 files changed, 25 insertions, 8 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/nvdimm_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/nvdimm_workarounds.C index a48bbaa6d..86e2cce75 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/nvdimm_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/nvdimm_workarounds.C @@ -32,7 +32,7 @@ // *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory // *HWP Level: 3 -// *HWP Consumed by: FSP:HB +// *HWP Consumed by: FSP:SBE #include <fapi2.H> #include <vector> @@ -89,6 +89,13 @@ constexpr const uint64_t FARB5Q_REG[] = MCA_7_MBA_FARB5Q, }; +// MCB_CNTLQ +constexpr const uint64_t MCB_CNTLQ_REG[] = +{ + MCBIST_0_MCB_CNTLQ, + MCBIST_1_MCB_CNTLQ, +}; + constexpr uint8_t PORTS_PER_MODULE = 8; /// @@ -111,22 +118,32 @@ fapi2::ReturnCode self_refresh_entry( const fapi2::Target<fapi2::TARGET_TYPE_PRO FAPI_DBG("Entering STR on port %u.", l_mca_pos); { - fapi2::buffer<uint64_t> l_mbarpc0_data, l_mbastr0_data; + fapi2::buffer<uint64_t> l_mbarpc0_data, l_mbastr0_data, l_mcbcntlq_data; constexpr uint64_t ENABLE = 1; constexpr uint64_t DISABLE = 0; - constexpr uint64_t MINALL_MAXALL = 0b000; - - // Step 1 - In MBARPC0Q, disable power domain control, set domain to MAXALL_MINALL, - // and enable minimum domain reduction + constexpr uint64_t MAXALL_MIN0 = 0b010; + constexpr uint64_t STOP = 1; + constexpr uint64_t PORTS_PER_MCBIST = 4; + constexpr uint64_t TIME_0 = 0; + const uint8_t l_mcbist = l_mca_pos < PORTS_PER_MCBIST ? 0 : 1; + + // Stop mcbist first otherwise it can kick the DIMM out of STR + FAPI_TRY(fapi2::getScom(i_target, MCB_CNTLQ_REG[l_mcbist], l_mcbcntlq_data)); + l_mcbcntlq_data.writeBit<MCBIST_CCS_CNTLQ_STOP>(STOP); + FAPI_TRY(fapi2::putScom(i_target, MCB_CNTLQ_REG[l_mcbist], l_mcbcntlq_data)); + + // Step 1 - In MBARPC0Q, disable power domain control, set domain to MAXALL_MIN0, + // and disable minimum domain reduction (allow immediate entry of STR) FAPI_TRY(fapi2::getScom(i_target, MBARPC0Q_REG[l_mca_pos], l_mbarpc0_data)); l_mbarpc0_data.writeBit<MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_ENABLE>(DISABLE); - l_mbarpc0_data.insertFromRight<MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS, MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_LEN>(MINALL_MAXALL); - l_mbarpc0_data.writeBit<MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_ENABLE>(ENABLE); + l_mbarpc0_data.insertFromRight<MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS, MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_LEN>(MAXALL_MIN0); + l_mbarpc0_data.writeBit<MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_ENABLE>(DISABLE); FAPI_TRY(fapi2::putScom(i_target, MBARPC0Q_REG[l_mca_pos], l_mbarpc0_data)); // Step 2 - In MBASTR0Q, enable STR entry FAPI_TRY(fapi2::getScom(i_target, MBASTR0Q_REG[l_mca_pos], l_mbastr0_data)); l_mbastr0_data.writeBit<MCA_MBASTR0Q_CFG_STR_ENABLE>(ENABLE); + l_mbastr0_data.insertFromRight<MCA_MBASTR0Q_CFG_ENTER_STR_TIME, MCA_MBASTR0Q_CFG_ENTER_STR_TIME_LEN>(TIME_0); FAPI_TRY(fapi2::putScom(i_target, MBASTR0Q_REG[l_mca_pos], l_mbastr0_data)); // Step 3 - In MBARPC0Q, enable power domain control. |
