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| author | Yue Du <daviddu@us.ibm.com> | 2016-04-07 13:33:10 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-08-20 09:57:33 -0400 |
| commit | ee19a5588e397b23a58e7d983cf8e820141fadf4 (patch) | |
| tree | a39ac2606dd7a4f7d4dbc8d3bf52d140ac82eb82 /src/import | |
| parent | 87f4965f4130e44079596a5aa6249550439dda41 (diff) | |
| download | talos-hostboot-ee19a5588e397b23a58e7d983cf8e820141fadf4.tar.gz talos-hostboot-ee19a5588e397b23a58e7d983cf8e820141fadf4.zip | |
Cache/Core: Istep4 procedure changes for model 9038 and above
Change-Id: Ib79018380346fc5aac7b15a15ed664d7e53dfb34
Original-Change-Id: I997537274ea9538330d9fb1ce240de793d90feec
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23019
Tested-by: Jenkins Server
Tested-by: PPE CI
Tested-by: Hostboot CI
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44851
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import')
3 files changed, 28 insertions, 4 deletions
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml index e5bdc5ed3..9b32d2373 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml @@ -60,7 +60,7 @@ <description> dpll clock start timed out. </description> - <ffdc>EQCLKSTAT</ffdc> + <ffdc>EQCPLTSTAT</ffdc> <callout> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> @@ -86,11 +86,19 @@ </hwpError> <!-- ********************************************************************* --> <hwpError> + <rc>RC_PMPROC_DPLLCLKSTART_FAILED</rc> + <description> + dpll clock start failed. + </description> + <ffdc>EQCLKSTAT</ffdc> + </hwpError> + <!-- ********************************************************************* --> + <hwpError> <rc>RC_PMPROC_ANEPCLKSTART_TIMEOUT</rc> <description> anep clock start timed out. </description> - <ffdc>EQCLKSTAT</ffdc> + <ffdc>EQCPLTSTAT</ffdc> <callout> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml index f796b6b3d..60221feb2 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml @@ -50,11 +50,19 @@ </hwpError> <!-- ********************************************************************* --> <hwpError> + <rc>RC_PMPROC_CACHECLKSTART_FAILED</rc> + <description> + cache clock start failed. + </description> + <ffdc>EQCLKSTAT</ffdc> + </hwpError> + <!-- ********************************************************************* --> + <hwpError> <rc>RC_PMPROC_CACHECLKSTART_TIMEOUT</rc> <description> cache clock start timed out. </description> - <ffdc>EQCLKSTAT</ffdc> + <ffdc>EQCPLTSTAT</ffdc> <callout> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml index 248b857fd..25e75af50 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml @@ -66,11 +66,19 @@ </hwpError> <!-- ********************************************************************* --> <hwpError> + <rc>RC_PMPROC_CORECLKSTART_FAILED</rc> + <description> + core clock start failed. + </description> + <ffdc>CORECLKSTAT</ffdc> + </hwpError> + <!-- ********************************************************************* --> + <hwpError> <rc>RC_PMPROC_CORECLKSTART_TIMEOUT</rc> <description> core clock start timed out. </description> - <ffdc>CORECLKSTAT</ffdc> + <ffdc>CORECPLTSTAT</ffdc> <callout> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> |
